1 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Module.h"
24 #include "llvm/MDNode.h"
25 #include "llvm/CodeGen/AsmPrinter.h"
26 #include "llvm/CodeGen/DwarfWriter.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringExtras.h"
36 #include "llvm/ADT/StringSet.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/Mangler.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(EmittedInsts, "Number of machine instrs printed");
48 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
51 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
52 /// make the right decision when printing asm code for different targets.
53 const ARMSubtarget *Subtarget;
55 /// AFI - Keep a pointer to ARMFunctionInfo for the current
59 /// MCP - Keep a pointer to constantpool entries of the current
61 const MachineConstantPool *MCP;
63 /// We name each basic block in a Function with a unique number, so
64 /// that we can consistently refer to them later. This is cleared
65 /// at the beginning of each call to runOnMachineFunction().
67 typedef std::map<const Value *, unsigned> ValueMapTy;
68 ValueMapTy NumberForBB;
70 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
71 /// non-lazy-pointers for indirect access.
72 StringSet<> GVNonLazyPtrs;
74 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
75 /// visibility that require non-lazy-pointers for indirect access.
76 StringSet<> HiddenGVNonLazyPtrs;
78 /// FnStubs - Keeps the set of external function GlobalAddresses that the
79 /// asm printer should generate stubs for.
82 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
85 explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
86 const TargetAsmInfo *T, bool V)
87 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
89 Subtarget = &TM.getSubtarget<ARMSubtarget>();
92 virtual const char *getPassName() const {
93 return "ARM Assembly Printer";
96 void printOperand(const MachineInstr *MI, int OpNum,
97 const char *Modifier = 0);
98 void printSOImmOperand(const MachineInstr *MI, int OpNum);
99 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
100 void printSORegOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
104 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
105 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
108 const char *Modifier = 0);
109 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
111 const char *Modifier = 0);
112 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOImmOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
138 unsigned AsmVariant, const char *ExtraCode);
139 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
141 const char *ExtraCode);
143 void printModuleLevelGV(const GlobalVariable* GVar);
144 bool printInstruction(const MachineInstr *MI); // autogenerated.
145 void printMachineInstruction(const MachineInstr *MI);
146 bool runOnMachineFunction(MachineFunction &F);
147 bool doInitialization(Module &M);
148 bool doFinalization(Module &M);
150 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
152 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
153 printDataDirective(MCPV->getType());
155 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
156 GlobalValue *GV = ACPV->getGV();
157 std::string Name = GV ? Mang->getValueName(GV) : TAI->getGlobalPrefix();
159 Name += ACPV->getSymbol();
160 if (ACPV->isNonLazyPointer()) {
161 if (GV->hasHiddenVisibility())
162 HiddenGVNonLazyPtrs.insert(Name);
164 GVNonLazyPtrs.insert(Name);
165 printSuffixedName(Name, "$non_lazy_ptr");
166 } else if (ACPV->isStub()) {
167 FnStubs.insert(Name);
168 printSuffixedName(Name, "$stub");
171 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
172 if (ACPV->getPCAdjustment() != 0) {
173 O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
174 << utostr(ACPV->getLabelId())
175 << "+" << (unsigned)ACPV->getPCAdjustment();
176 if (ACPV->mustAddCurrentAddress())
183 void getAnalysisUsage(AnalysisUsage &AU) const {
184 AsmPrinter::getAnalysisUsage(AU);
185 AU.setPreservesAll();
186 AU.addRequired<MachineModuleInfo>();
187 AU.addRequired<DwarfWriter>();
190 } // end of anonymous namespace
192 #include "ARMGenAsmWriter.inc"
194 /// runOnMachineFunction - This uses the printInstruction()
195 /// method to print assembly for each instruction.
197 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
200 AFI = MF.getInfo<ARMFunctionInfo>();
201 MCP = MF.getConstantPool();
203 SetupMachineFunction(MF);
206 // NOTE: we don't print out constant pools here, they are handled as
210 // Print out labels for the function.
211 const Function *F = MF.getFunction();
212 switch (F->getLinkage()) {
213 default: LLVM_UNREACHABLE("Unknown linkage type!");
214 case Function::PrivateLinkage:
215 case Function::InternalLinkage:
216 SwitchToTextSection("\t.text", F);
218 case Function::ExternalLinkage:
219 SwitchToTextSection("\t.text", F);
220 O << "\t.globl\t" << CurrentFnName << "\n";
222 case Function::WeakAnyLinkage:
223 case Function::WeakODRLinkage:
224 case Function::LinkOnceAnyLinkage:
225 case Function::LinkOnceODRLinkage:
226 if (Subtarget->isTargetDarwin()) {
228 ".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
229 O << "\t.globl\t" << CurrentFnName << "\n";
230 O << "\t.weak_definition\t" << CurrentFnName << "\n";
232 O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
237 printVisibility(CurrentFnName, F->getVisibility());
239 if (AFI->isThumbFunction()) {
240 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
241 O << "\t.code\t16\n";
242 O << "\t.thumb_func";
243 if (Subtarget->isTargetDarwin())
244 O << "\t" << CurrentFnName;
248 EmitAlignment(MF.getAlignment(), F);
251 O << CurrentFnName << ":\n";
252 // Emit pre-function debug information.
253 DW->BeginFunction(&MF);
255 if (Subtarget->isTargetDarwin()) {
256 // If the function is empty, then we need to emit *something*. Otherwise,
257 // the function's label might be associated with something that it wasn't
258 // meant to be associated with. We emit a noop in this situation.
259 MachineFunction::iterator I = MF.begin();
261 if (++I == MF.end() && MF.front().empty())
265 // Print out code for the function.
266 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
268 // Print a label for the basic block.
269 if (I != MF.begin()) {
270 printBasicBlockLabel(I, true, true, VerboseAsm);
273 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
275 // Print the assembly for the instruction.
276 printMachineInstruction(II);
280 if (TAI->hasDotTypeDotSizeDirective())
281 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
283 // Emit post-function debug information.
284 DW->EndFunction(&MF);
291 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
292 const char *Modifier) {
293 const MachineOperand &MO = MI->getOperand(OpNum);
294 switch (MO.getType()) {
295 case MachineOperand::MO_Register: {
296 unsigned Reg = MO.getReg();
297 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
298 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
299 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
300 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
302 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
304 } else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
305 O << '{' << TRI->getAsmName(Reg) << '}';
307 O << TRI->getAsmName(Reg);
310 LLVM_UNREACHABLE("not implemented");
313 case MachineOperand::MO_Immediate: {
314 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
320 case MachineOperand::MO_MachineBasicBlock:
321 printBasicBlockLabel(MO.getMBB());
323 case MachineOperand::MO_GlobalAddress: {
324 bool isCallOp = Modifier && !strcmp(Modifier, "call");
325 GlobalValue *GV = MO.getGlobal();
326 std::string Name = Mang->getValueName(GV);
327 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
328 GV->hasLinkOnceLinkage());
329 if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
330 TM.getRelocationModel() != Reloc::Static) {
331 printSuffixedName(Name, "$stub");
332 FnStubs.insert(Name);
336 printOffset(MO.getOffset());
338 if (isCallOp && Subtarget->isTargetELF() &&
339 TM.getRelocationModel() == Reloc::PIC_)
343 case MachineOperand::MO_ExternalSymbol: {
344 bool isCallOp = Modifier && !strcmp(Modifier, "call");
345 std::string Name(TAI->getGlobalPrefix());
346 Name += MO.getSymbolName();
347 if (isCallOp && Subtarget->isTargetDarwin() &&
348 TM.getRelocationModel() != Reloc::Static) {
349 printSuffixedName(Name, "$stub");
350 FnStubs.insert(Name);
353 if (isCallOp && Subtarget->isTargetELF() &&
354 TM.getRelocationModel() == Reloc::PIC_)
358 case MachineOperand::MO_ConstantPoolIndex:
359 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
360 << '_' << MO.getIndex();
362 case MachineOperand::MO_JumpTableIndex:
363 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
364 << '_' << MO.getIndex();
367 O << "<unknown operand type>"; abort (); break;
371 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
372 const TargetAsmInfo *TAI) {
373 assert(V < (1 << 12) && "Not a valid so_imm value!");
374 unsigned Imm = ARM_AM::getSOImmValImm(V);
375 unsigned Rot = ARM_AM::getSOImmValRot(V);
377 // Print low-level immediate formation info, per
378 // A5.1.3: "Data-processing operands - Immediate".
380 O << "#" << Imm << ", " << Rot;
381 // Pretty printed version.
383 O << ' ' << TAI->getCommentString()
384 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
390 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
391 /// immediate in bits 0-7.
392 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
393 const MachineOperand &MO = MI->getOperand(OpNum);
394 assert(MO.isImm() && "Not a valid so_imm value!");
395 printSOImm(O, MO.getImm(), VerboseAsm, TAI);
398 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
399 /// followed by an 'orr' to materialize.
400 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
401 const MachineOperand &MO = MI->getOperand(OpNum);
402 assert(MO.isImm() && "Not a valid so_imm value!");
403 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
404 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
405 printSOImm(O, ARM_AM::getSOImmVal(V1), VerboseAsm, TAI);
407 printPredicateOperand(MI, 2);
413 printSOImm(O, ARM_AM::getSOImmVal(V2), VerboseAsm, TAI);
416 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
417 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
419 // REG REG 0,SH_OPC - e.g. R5, ROR R3
420 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
421 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
422 const MachineOperand &MO1 = MI->getOperand(Op);
423 const MachineOperand &MO2 = MI->getOperand(Op+1);
424 const MachineOperand &MO3 = MI->getOperand(Op+2);
426 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
427 O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
429 // Print the shift opc.
431 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
435 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
436 O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
437 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
439 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
443 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
444 const MachineOperand &MO1 = MI->getOperand(Op);
445 const MachineOperand &MO2 = MI->getOperand(Op+1);
446 const MachineOperand &MO3 = MI->getOperand(Op+2);
448 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
449 printOperand(MI, Op);
453 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
456 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
458 << (char)ARM_AM::getAM2Op(MO3.getImm())
459 << ARM_AM::getAM2Offset(MO3.getImm());
465 << (char)ARM_AM::getAM2Op(MO3.getImm())
466 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
468 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
470 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
475 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
476 const MachineOperand &MO1 = MI->getOperand(Op);
477 const MachineOperand &MO2 = MI->getOperand(Op+1);
480 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
481 assert(ImmOffs && "Malformed indexed load / store!");
483 << (char)ARM_AM::getAM2Op(MO2.getImm())
488 O << (char)ARM_AM::getAM2Op(MO2.getImm())
489 << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
491 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
493 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
497 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
498 const MachineOperand &MO1 = MI->getOperand(Op);
499 const MachineOperand &MO2 = MI->getOperand(Op+1);
500 const MachineOperand &MO3 = MI->getOperand(Op+2);
502 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
503 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
507 << (char)ARM_AM::getAM3Op(MO3.getImm())
508 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
513 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
515 << (char)ARM_AM::getAM3Op(MO3.getImm())
520 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
521 const MachineOperand &MO1 = MI->getOperand(Op);
522 const MachineOperand &MO2 = MI->getOperand(Op+1);
525 O << (char)ARM_AM::getAM3Op(MO2.getImm())
526 << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
530 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
531 assert(ImmOffs && "Malformed indexed load / store!");
533 << (char)ARM_AM::getAM3Op(MO2.getImm())
537 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
538 const char *Modifier) {
539 const MachineOperand &MO1 = MI->getOperand(Op);
540 const MachineOperand &MO2 = MI->getOperand(Op+1);
541 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
542 if (Modifier && strcmp(Modifier, "submode") == 0) {
543 if (MO1.getReg() == ARM::SP) {
544 bool isLDM = (MI->getOpcode() == ARM::LDM ||
545 MI->getOpcode() == ARM::LDM_RET);
546 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
548 O << ARM_AM::getAMSubModeStr(Mode);
550 printOperand(MI, Op);
551 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
556 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
557 const char *Modifier) {
558 const MachineOperand &MO1 = MI->getOperand(Op);
559 const MachineOperand &MO2 = MI->getOperand(Op+1);
561 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
562 printOperand(MI, Op);
566 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
568 if (Modifier && strcmp(Modifier, "submode") == 0) {
569 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
570 if (MO1.getReg() == ARM::SP) {
571 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
572 MI->getOpcode() == ARM::FLDMS);
573 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
575 O << ARM_AM::getAMSubModeStr(Mode);
577 } else if (Modifier && strcmp(Modifier, "base") == 0) {
578 // Used for FSTM{D|S} and LSTM{D|S} operations.
579 O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
580 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
585 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
587 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
589 << (char)ARM_AM::getAM5Op(MO2.getImm())
595 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
596 const MachineOperand &MO1 = MI->getOperand(Op);
597 const MachineOperand &MO2 = MI->getOperand(Op+1);
598 const MachineOperand &MO3 = MI->getOperand(Op+2);
600 // FIXME: No support yet for specifying alignment.
601 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
603 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
604 if (MO2.getReg() == 0)
607 O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
611 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
612 const char *Modifier) {
613 if (Modifier && strcmp(Modifier, "label") == 0) {
614 printPCLabel(MI, Op+1);
618 const MachineOperand &MO1 = MI->getOperand(Op);
619 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
620 O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
624 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
625 const MachineOperand &MO = MI->getOperand(Op);
626 uint32_t v = ~MO.getImm();
627 int32_t lsb = CountTrailingZeros_32(v);
628 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
629 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
630 O << "#" << lsb << ", #" << width;
633 //===--------------------------------------------------------------------===//
636 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
637 const MachineOperand &MO1 = MI->getOperand(Op);
638 const MachineOperand &MO2 = MI->getOperand(Op+1);
639 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
640 O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
644 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
646 const MachineOperand &MO1 = MI->getOperand(Op);
647 const MachineOperand &MO2 = MI->getOperand(Op+1);
648 const MachineOperand &MO3 = MI->getOperand(Op+2);
650 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
651 printOperand(MI, Op);
655 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
657 O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
658 else if (unsigned ImmOffs = MO2.getImm()) {
659 O << ", #" << ImmOffs;
667 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
668 printThumbAddrModeRI5Operand(MI, Op, 1);
671 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
672 printThumbAddrModeRI5Operand(MI, Op, 2);
675 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
676 printThumbAddrModeRI5Operand(MI, Op, 4);
679 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
680 const MachineOperand &MO1 = MI->getOperand(Op);
681 const MachineOperand &MO2 = MI->getOperand(Op+1);
682 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
683 if (unsigned ImmOffs = MO2.getImm())
684 O << ", #" << ImmOffs << " * 4";
688 //===--------------------------------------------------------------------===//
690 /// printT2SOImmOperand - T2SOImm is:
691 /// 1. a 4-bit splat control value and 8 bit immediate value
692 /// 2. a 5-bit rotate amount and a non-zero 8-bit immediate value
693 /// represented by a normalizedin 7-bit value (msb is always 1)
694 void ARMAsmPrinter::printT2SOImmOperand(const MachineInstr *MI, int OpNum) {
695 const MachineOperand &MO = MI->getOperand(OpNum);
696 assert(MO.isImm() && "Not a valid so_imm value!");
698 unsigned Imm = ARM_AM::getT2SOImmValDecode(MO.getImm());
699 // Always print the immediate directly, as the "rotate" form
700 // is deprecated in some contexts.
704 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
705 // register with shift forms.
707 // REG IMM, SH_OPC - e.g. R5, LSL #3
708 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
709 const MachineOperand &MO1 = MI->getOperand(OpNum);
710 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
712 unsigned Reg = MO1.getReg();
713 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
714 O << TM.getRegisterInfo()->getAsmName(Reg);
716 // Print the shift opc.
718 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
721 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
722 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
725 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
727 const MachineOperand &MO1 = MI->getOperand(OpNum);
728 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
730 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
732 unsigned OffImm = MO2.getImm();
733 if (OffImm) // Don't print +0.
734 O << ", #+" << OffImm;
738 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
740 const MachineOperand &MO1 = MI->getOperand(OpNum);
741 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
743 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
745 int32_t OffImm = (int32_t)MO2.getImm();
748 O << ", #-" << -OffImm;
750 O << ", #+" << OffImm;
754 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
756 const MachineOperand &MO1 = MI->getOperand(OpNum);
757 int32_t OffImm = (int32_t)MO1.getImm();
760 O << "#-" << -OffImm;
765 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
767 const MachineOperand &MO1 = MI->getOperand(OpNum);
768 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
769 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
771 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
775 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
777 unsigned ShAmt = MO3.getImm();
779 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
780 O << ", lsl #" << ShAmt;
787 //===--------------------------------------------------------------------===//
789 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
790 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
792 O << ARMCondCodeToString(CC);
795 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
796 unsigned Reg = MI->getOperand(OpNum).getReg();
798 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
803 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
804 int Id = (int)MI->getOperand(OpNum).getImm();
805 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
808 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
810 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
812 if (i != e-1) O << ", ";
817 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
818 const char *Modifier) {
819 assert(Modifier && "This operand only works with a modifier!");
820 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
822 if (!strcmp(Modifier, "label")) {
823 unsigned ID = MI->getOperand(OpNum).getImm();
824 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
825 << '_' << ID << ":\n";
827 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
828 unsigned CPI = MI->getOperand(OpNum).getIndex();
830 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
832 if (MCPE.isMachineConstantPoolEntry()) {
833 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
835 EmitGlobalConstant(MCPE.Val.ConstVal);
840 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
841 const MachineOperand &MO1 = MI->getOperand(OpNum);
842 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
843 unsigned JTI = MO1.getIndex();
844 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
845 << '_' << JTI << '_' << MO2.getImm() << ":\n";
847 const char *JTEntryDirective = TAI->getJumpTableDirective();
848 if (!JTEntryDirective)
849 JTEntryDirective = TAI->getData32bitsDirective();
851 const MachineFunction *MF = MI->getParent()->getParent();
852 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
853 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
854 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
855 bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
856 std::set<MachineBasicBlock*> JTSets;
857 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
858 MachineBasicBlock *MBB = JTBBs[i];
859 if (UseSet && JTSets.insert(MBB).second)
860 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
862 O << JTEntryDirective << ' ';
864 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
865 << '_' << JTI << '_' << MO2.getImm()
866 << "_set_" << MBB->getNumber();
867 else if (TM.getRelocationModel() == Reloc::PIC_) {
868 printBasicBlockLabel(MBB, false, false, false);
869 // If the arch uses custom Jump Table directives, don't calc relative to JT
870 if (!TAI->getJumpTableDirective())
871 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
872 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
874 printBasicBlockLabel(MBB, false, false, false);
881 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
882 unsigned AsmVariant, const char *ExtraCode){
883 // Does this asm operand have a single letter operand modifier?
884 if (ExtraCode && ExtraCode[0]) {
885 if (ExtraCode[1] != 0) return true; // Unknown modifier.
887 switch (ExtraCode[0]) {
888 default: return true; // Unknown modifier.
889 case 'a': // Don't print "#" before a global var name or constant.
890 case 'c': // Don't print "$" before a global var name or constant.
891 printOperand(MI, OpNum, "no_hash");
893 case 'P': // Print a VFP double precision register.
894 printOperand(MI, OpNum);
897 if (TM.getTargetData()->isLittleEndian())
901 if (TM.getTargetData()->isBigEndian())
904 case 'H': // Write second word of DI / DF reference.
905 // Verify that this operand has two consecutive registers.
906 if (!MI->getOperand(OpNum).isReg() ||
907 OpNum+1 == MI->getNumOperands() ||
908 !MI->getOperand(OpNum+1).isReg())
910 ++OpNum; // Return the high-part.
914 printOperand(MI, OpNum);
918 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
919 unsigned OpNum, unsigned AsmVariant,
920 const char *ExtraCode) {
921 if (ExtraCode && ExtraCode[0])
922 return true; // Unknown modifier.
923 printAddrMode2Operand(MI, OpNum);
927 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
930 int Opc = MI->getOpcode();
932 case ARM::CONSTPOOL_ENTRY:
933 if (!InCPMode && AFI->isThumbFunction()) {
939 if (InCPMode && AFI->isThumbFunction())
943 // Call the autogenerated instruction printer routines.
944 printInstruction(MI);
947 bool ARMAsmPrinter::doInitialization(Module &M) {
949 bool Result = AsmPrinter::doInitialization(M);
950 DW = getAnalysisIfAvailable<DwarfWriter>();
952 // Thumb-2 instructions are supported only in unified assembler syntax mode.
953 if (Subtarget->hasThumb2())
954 O << "\t.syntax unified\n";
956 // Emit ARM Build Attributes
957 if (Subtarget->isTargetELF()) {
959 std::string CPUString = Subtarget->getCPUString();
960 if (CPUString != "generic")
961 O << "\t.cpu " << CPUString << '\n';
963 // FIXME: Emit FPU type
964 if (Subtarget->hasVFP2())
965 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
967 // Signal various FP modes.
969 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
970 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
972 if (FiniteOnlyFPMath())
973 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
975 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
977 // 8-bytes alignment stuff.
978 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
979 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
981 // FIXME: Should we signal R9 usage?
987 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
988 /// Don't print things like \\n or \\0.
989 static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) {
990 for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
996 void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
997 const TargetData *TD = TM.getTargetData();
999 if (!GVar->hasInitializer()) // External global require no code
1002 // Check to see if this is a special global used by LLVM, if so, emit it.
1004 if (EmitSpecialLLVMGlobal(GVar)) {
1005 if (Subtarget->isTargetDarwin() &&
1006 TM.getRelocationModel() == Reloc::Static) {
1007 if (GVar->getName() == "llvm.global_ctors")
1008 O << ".reference .constructors_used\n";
1009 else if (GVar->getName() == "llvm.global_dtors")
1010 O << ".reference .destructors_used\n";
1015 std::string name = Mang->getValueName(GVar);
1016 Constant *C = GVar->getInitializer();
1017 if (isa<MDNode>(C) || isa<MDString>(C))
1019 const Type *Type = C->getType();
1020 unsigned Size = TD->getTypeAllocSize(Type);
1021 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1022 bool isDarwin = Subtarget->isTargetDarwin();
1024 printVisibility(name, GVar->getVisibility());
1026 if (Subtarget->isTargetELF())
1027 O << "\t.type " << name << ",%object\n";
1029 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1031 TAI->SectionKindForGlobal(GVar) == SectionKind::RODataMergeStr)) {
1032 // FIXME: This seems to be pretty darwin-specific
1034 if (GVar->hasExternalLinkage()) {
1035 SwitchToSection(TAI->SectionForGlobal(GVar));
1036 if (const char *Directive = TAI->getZeroFillDirective()) {
1037 O << "\t.globl\t" << name << "\n";
1038 O << Directive << "__DATA, __common, " << name << ", "
1039 << Size << ", " << Align << "\n";
1044 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1045 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1048 if (GVar->hasLocalLinkage()) {
1049 O << TAI->getLCOMMDirective() << name << "," << Size
1051 } else if (GVar->hasCommonLinkage()) {
1052 O << TAI->getCOMMDirective() << name << "," << Size
1055 SwitchToSection(TAI->SectionForGlobal(GVar));
1056 O << "\t.globl " << name << '\n'
1057 << TAI->getWeakDefDirective() << name << '\n';
1058 EmitAlignment(Align, GVar);
1061 O << "\t\t\t\t" << TAI->getCommentString() << ' ';
1062 PrintUnmangledNameSafely(GVar, O);
1065 EmitGlobalConstant(C);
1068 } else if (TAI->getLCOMMDirective() != NULL) {
1069 if (GVar->hasLocalLinkage()) {
1070 O << TAI->getLCOMMDirective() << name << "," << Size;
1072 O << TAI->getCOMMDirective() << name << "," << Size;
1073 if (TAI->getCOMMDirectiveTakesAlignment())
1074 O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1077 SwitchToSection(TAI->SectionForGlobal(GVar));
1078 if (GVar->hasLocalLinkage())
1079 O << "\t.local\t" << name << "\n";
1080 O << TAI->getCOMMDirective() << name << "," << Size;
1081 if (TAI->getCOMMDirectiveTakesAlignment())
1082 O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1085 O << "\t\t" << TAI->getCommentString() << " ";
1086 PrintUnmangledNameSafely(GVar, O);
1093 SwitchToSection(TAI->SectionForGlobal(GVar));
1094 switch (GVar->getLinkage()) {
1095 case GlobalValue::CommonLinkage:
1096 case GlobalValue::LinkOnceAnyLinkage:
1097 case GlobalValue::LinkOnceODRLinkage:
1098 case GlobalValue::WeakAnyLinkage:
1099 case GlobalValue::WeakODRLinkage:
1101 O << "\t.globl " << name << "\n"
1102 << "\t.weak_definition " << name << "\n";
1104 O << "\t.weak " << name << "\n";
1107 case GlobalValue::AppendingLinkage:
1108 // FIXME: appending linkage variables should go into a section of
1109 // their name or something. For now, just emit them as external.
1110 case GlobalValue::ExternalLinkage:
1111 O << "\t.globl " << name << "\n";
1113 case GlobalValue::PrivateLinkage:
1114 case GlobalValue::InternalLinkage:
1117 LLVM_UNREACHABLE("Unknown linkage type!");
1120 EmitAlignment(Align, GVar);
1123 O << "\t\t\t\t" << TAI->getCommentString() << " ";
1124 PrintUnmangledNameSafely(GVar, O);
1127 if (TAI->hasDotTypeDotSizeDirective())
1128 O << "\t.size " << name << ", " << Size << "\n";
1130 EmitGlobalConstant(C);
1135 bool ARMAsmPrinter::doFinalization(Module &M) {
1136 for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
1138 printModuleLevelGV(I);
1140 if (Subtarget->isTargetDarwin()) {
1141 SwitchToDataSection("");
1143 // Output stubs for dynamically-linked functions
1144 for (StringSet<>::iterator i = FnStubs.begin(), e = FnStubs.end();
1146 if (TM.getRelocationModel() == Reloc::PIC_)
1147 SwitchToTextSection(".section __TEXT,__picsymbolstub4,symbol_stubs,"
1150 SwitchToTextSection(".section __TEXT,__symbol_stub4,symbol_stubs,"
1154 O << "\t.code\t32\n";
1156 const char *p = i->getKeyData();
1157 printSuffixedName(p, "$stub");
1159 O << "\t.indirect_symbol " << p << "\n";
1161 printSuffixedName(p, "$slp");
1163 if (TM.getRelocationModel() == Reloc::PIC_) {
1164 printSuffixedName(p, "$scv");
1166 O << "\tadd ip, pc, ip\n";
1168 O << "\tldr pc, [ip, #0]\n";
1169 printSuffixedName(p, "$slp");
1172 printSuffixedName(p, "$lazy_ptr");
1173 if (TM.getRelocationModel() == Reloc::PIC_) {
1175 printSuffixedName(p, "$scv");
1179 SwitchToDataSection(".lazy_symbol_pointer", 0);
1180 printSuffixedName(p, "$lazy_ptr");
1182 O << "\t.indirect_symbol " << p << "\n";
1183 O << "\t.long\tdyld_stub_binding_helper\n";
1187 // Output non-lazy-pointers for external and common global variables.
1188 if (!GVNonLazyPtrs.empty()) {
1189 SwitchToDataSection("\t.non_lazy_symbol_pointer", 0);
1190 for (StringSet<>::iterator i = GVNonLazyPtrs.begin(),
1191 e = GVNonLazyPtrs.end(); i != e; ++i) {
1192 const char *p = i->getKeyData();
1193 printSuffixedName(p, "$non_lazy_ptr");
1195 O << "\t.indirect_symbol " << p << "\n";
1196 O << "\t.long\t0\n";
1200 if (!HiddenGVNonLazyPtrs.empty()) {
1201 SwitchToSection(TAI->getDataSection());
1202 for (StringSet<>::iterator i = HiddenGVNonLazyPtrs.begin(),
1203 e = HiddenGVNonLazyPtrs.end(); i != e; ++i) {
1204 const char *p = i->getKeyData();
1206 printSuffixedName(p, "$non_lazy_ptr");
1208 O << "\t.long " << p << "\n";
1213 // Funny Darwin hack: This flag tells the linker that no global symbols
1214 // contain code that falls through to other global symbols (e.g. the obvious
1215 // implementation of multiple entry points). If this doesn't occur, the
1216 // linker can safely perform dead code stripping. Since LLVM never
1217 // generates code that does this, it is always safe to set.
1218 O << "\t.subsections_via_symbols\n";
1221 return AsmPrinter::doFinalization(M);
1224 /// createARMCodePrinterPass - Returns a pass that prints the ARM
1225 /// assembly code for a MachineFunction to the given output stream,
1226 /// using the given target machine description. This should work
1227 /// regardless of whether the function is in SSA form.
1229 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
1230 ARMBaseTargetMachine &tm,
1232 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), verbose);
1236 static struct Register {
1238 ARMBaseTargetMachine::registerAsmPrinter(createARMCodePrinterPass);
1243 // Force static initialization.
1244 extern "C" void LLVMInitializeARMAsmPrinter() { }