1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/raw_ostream.h"
56 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
57 cl::desc("enable experimental asmprinter gunk in the arm backend"));
60 class ARMAsmPrinter : public AsmPrinter {
62 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
63 /// make the right decision when printing asm code for different targets.
64 const ARMSubtarget *Subtarget;
66 /// AFI - Keep a pointer to ARMFunctionInfo for the current
70 /// MCP - Keep a pointer to constantpool entries of the current
72 const MachineConstantPool *MCP;
75 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
76 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
77 Subtarget = &TM.getSubtarget<ARMSubtarget>();
80 virtual const char *getPassName() const {
81 return "ARM Assembly Printer";
84 void printInstructionThroughMCStreamer(const MachineInstr *MI);
87 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
88 const char *Modifier = 0);
89 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
90 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
92 void printSORegOperand(const MachineInstr *MI, int OpNum,
94 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
96 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
98 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
100 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
102 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
103 const char *Modifier = 0);
104 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
105 const char *Modifier = 0);
106 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
108 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
112 const char *Modifier = 0);
113 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum,
116 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
118 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
119 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
121 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
124 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
126 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
128 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
130 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
133 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
134 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
136 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
138 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
140 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
142 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
144 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
147 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
149 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
151 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
153 void printPredicateOperand(const MachineInstr *MI, int OpNum,
155 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
157 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
159 void printPCLabel(const MachineInstr *MI, int OpNum,
161 void printRegisterList(const MachineInstr *MI, int OpNum,
163 void printCPInstOperand(const MachineInstr *MI, int OpNum,
165 const char *Modifier);
166 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
168 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
170 void printTBAddrMode(const MachineInstr *MI, int OpNum,
172 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
174 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
176 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
178 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
181 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
182 unsigned AsmVariant, const char *ExtraCode,
184 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
186 const char *ExtraCode, raw_ostream &O);
188 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
189 static const char *getRegisterName(unsigned RegNo);
191 virtual void EmitInstruction(const MachineInstr *MI);
192 bool runOnMachineFunction(MachineFunction &F);
194 virtual void EmitConstantPool() {} // we emit constant pools customly!
195 virtual void EmitFunctionEntryLabel();
196 void EmitStartOfAsmFile(Module &M);
197 void EmitEndOfAsmFile(Module &M);
199 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
200 const MachineBasicBlock *MBB) const;
201 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
203 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
205 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
206 SmallString<128> Str;
207 raw_svector_ostream OS(Str);
208 EmitMachineConstantPoolValue(MCPV, OS);
209 OutStreamer.EmitRawText(OS.str());
212 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
214 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
215 case 1: O << MAI->getData8bitsDirective(0); break;
216 case 2: O << MAI->getData16bitsDirective(0); break;
217 case 4: O << MAI->getData32bitsDirective(0); break;
218 default: assert(0 && "Unknown CPV size");
221 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
223 if (ACPV->isLSDA()) {
224 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
225 } else if (ACPV->isBlockAddress()) {
226 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
227 } else if (ACPV->isGlobalValue()) {
228 const GlobalValue *GV = ACPV->getGV();
229 bool isIndirect = Subtarget->isTargetDarwin() &&
230 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
232 O << *Mang->getSymbol(GV);
234 // FIXME: Remove this when Darwin transition to @GOT like syntax.
235 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
238 MachineModuleInfoMachO &MMIMachO =
239 MMI->getObjFileInfo<MachineModuleInfoMachO>();
240 MachineModuleInfoImpl::StubValueTy &StubSym =
241 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
242 MMIMachO.getGVStubEntry(Sym);
243 if (StubSym.getPointer() == 0)
244 StubSym = MachineModuleInfoImpl::
245 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
248 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
249 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
252 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
253 if (ACPV->getPCAdjustment() != 0) {
254 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
255 << getFunctionNumber() << "_" << ACPV->getLabelId()
256 << "+" << (unsigned)ACPV->getPCAdjustment();
257 if (ACPV->mustAddCurrentAddress())
263 } // end of anonymous namespace
265 #include "ARMGenAsmWriter.inc"
267 void ARMAsmPrinter::EmitFunctionEntryLabel() {
268 if (AFI->isThumbFunction()) {
269 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
270 if (!Subtarget->isTargetDarwin())
271 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
273 // This needs to emit to a temporary string to get properly quoted
274 // MCSymbols when they have spaces in them.
275 SmallString<128> Tmp;
276 raw_svector_ostream OS(Tmp);
277 OS << "\t.thumb_func\t" << *CurrentFnSym;
278 OutStreamer.EmitRawText(OS.str());
282 OutStreamer.EmitLabel(CurrentFnSym);
285 /// runOnMachineFunction - This uses the printInstruction()
286 /// method to print assembly for each instruction.
288 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
289 AFI = MF.getInfo<ARMFunctionInfo>();
290 MCP = MF.getConstantPool();
292 return AsmPrinter::runOnMachineFunction(MF);
295 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
296 raw_ostream &O, const char *Modifier) {
297 const MachineOperand &MO = MI->getOperand(OpNum);
298 unsigned TF = MO.getTargetFlags();
300 switch (MO.getType()) {
302 assert(0 && "<unknown operand type>");
303 case MachineOperand::MO_Register: {
304 unsigned Reg = MO.getReg();
305 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
306 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
307 unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
308 unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
310 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
312 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
313 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
315 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
316 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
317 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
319 assert(!MO.getSubReg() && "Subregs should be eliminated!");
320 O << getRegisterName(Reg);
324 case MachineOperand::MO_Immediate: {
325 int64_t Imm = MO.getImm();
327 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
328 (TF & ARMII::MO_LO16))
330 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
331 (TF & ARMII::MO_HI16))
336 case MachineOperand::MO_MachineBasicBlock:
337 O << *MO.getMBB()->getSymbol();
339 case MachineOperand::MO_GlobalAddress: {
340 bool isCallOp = Modifier && !strcmp(Modifier, "call");
341 const GlobalValue *GV = MO.getGlobal();
343 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
344 (TF & ARMII::MO_LO16))
346 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
347 (TF & ARMII::MO_HI16))
349 O << *Mang->getSymbol(GV);
351 printOffset(MO.getOffset(), O);
353 if (isCallOp && Subtarget->isTargetELF() &&
354 TM.getRelocationModel() == Reloc::PIC_)
358 case MachineOperand::MO_ExternalSymbol: {
359 bool isCallOp = Modifier && !strcmp(Modifier, "call");
360 O << *GetExternalSymbolSymbol(MO.getSymbolName());
362 if (isCallOp && Subtarget->isTargetELF() &&
363 TM.getRelocationModel() == Reloc::PIC_)
367 case MachineOperand::MO_ConstantPoolIndex:
368 O << *GetCPISymbol(MO.getIndex());
370 case MachineOperand::MO_JumpTableIndex:
371 O << *GetJTISymbol(MO.getIndex());
376 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
377 const MCAsmInfo *MAI) {
378 // Break it up into two parts that make up a shifter immediate.
379 V = ARM_AM::getSOImmVal(V);
380 assert(V != -1 && "Not a valid so_imm value!");
382 unsigned Imm = ARM_AM::getSOImmValImm(V);
383 unsigned Rot = ARM_AM::getSOImmValRot(V);
385 // Print low-level immediate formation info, per
386 // A5.1.3: "Data-processing operands - Immediate".
388 O << "#" << Imm << ", " << Rot;
389 // Pretty printed version.
391 O << "\t" << MAI->getCommentString() << ' ';
392 O << (int)ARM_AM::rotr32(Imm, Rot);
399 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
400 /// immediate in bits 0-7.
401 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
403 const MachineOperand &MO = MI->getOperand(OpNum);
404 assert(MO.isImm() && "Not a valid so_imm value!");
405 printSOImm(O, MO.getImm(), isVerbose(), MAI);
408 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
409 /// followed by an 'orr' to materialize.
410 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
412 const MachineOperand &MO = MI->getOperand(OpNum);
413 assert(MO.isImm() && "Not a valid so_imm value!");
414 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
415 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
416 printSOImm(O, V1, isVerbose(), MAI);
418 printPredicateOperand(MI, 2, O);
420 printOperand(MI, 0, O);
422 printOperand(MI, 0, O);
424 printSOImm(O, V2, isVerbose(), MAI);
427 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
428 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
430 // REG REG 0,SH_OPC - e.g. R5, ROR R3
431 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
432 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
434 const MachineOperand &MO1 = MI->getOperand(Op);
435 const MachineOperand &MO2 = MI->getOperand(Op+1);
436 const MachineOperand &MO3 = MI->getOperand(Op+2);
438 O << getRegisterName(MO1.getReg());
440 // Print the shift opc.
442 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
446 O << getRegisterName(MO2.getReg());
447 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
449 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
453 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
455 const MachineOperand &MO1 = MI->getOperand(Op);
456 const MachineOperand &MO2 = MI->getOperand(Op+1);
457 const MachineOperand &MO3 = MI->getOperand(Op+2);
459 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
460 printOperand(MI, Op, O);
464 O << "[" << getRegisterName(MO1.getReg());
467 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
469 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
470 << ARM_AM::getAM2Offset(MO3.getImm());
476 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
477 << getRegisterName(MO2.getReg());
479 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
481 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
486 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
488 const MachineOperand &MO1 = MI->getOperand(Op);
489 const MachineOperand &MO2 = MI->getOperand(Op+1);
492 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
494 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
499 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
500 << getRegisterName(MO1.getReg());
502 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
504 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
508 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
510 const MachineOperand &MO1 = MI->getOperand(Op);
511 const MachineOperand &MO2 = MI->getOperand(Op+1);
512 const MachineOperand &MO3 = MI->getOperand(Op+2);
514 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
515 O << "[" << getRegisterName(MO1.getReg());
519 << (char)ARM_AM::getAM3Op(MO3.getImm())
520 << getRegisterName(MO2.getReg())
525 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
527 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
532 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
534 const MachineOperand &MO1 = MI->getOperand(Op);
535 const MachineOperand &MO2 = MI->getOperand(Op+1);
538 O << (char)ARM_AM::getAM3Op(MO2.getImm())
539 << getRegisterName(MO1.getReg());
543 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
545 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
549 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
551 const char *Modifier) {
552 const MachineOperand &MO2 = MI->getOperand(Op+1);
553 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
554 if (Modifier && strcmp(Modifier, "submode") == 0) {
555 O << ARM_AM::getAMSubModeStr(Mode);
556 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
557 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
558 if (Mode == ARM_AM::ia)
561 printOperand(MI, Op, O);
565 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
567 const char *Modifier) {
568 const MachineOperand &MO1 = MI->getOperand(Op);
569 const MachineOperand &MO2 = MI->getOperand(Op+1);
571 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
572 printOperand(MI, Op, O);
576 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
578 if (Modifier && strcmp(Modifier, "submode") == 0) {
579 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
580 O << ARM_AM::getAMSubModeStr(Mode);
582 } else if (Modifier && strcmp(Modifier, "base") == 0) {
583 // Used for FSTM{D|S} and LSTM{D|S} operations.
584 O << getRegisterName(MO1.getReg());
588 O << "[" << getRegisterName(MO1.getReg());
590 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
592 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
598 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 O << "[" << getRegisterName(MO1.getReg());
605 // FIXME: Both darwin as and GNU as violate ARM docs here.
606 O << ", :" << MO2.getImm();
611 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
613 const MachineOperand &MO = MI->getOperand(Op);
614 if (MO.getReg() == 0)
617 O << ", " << getRegisterName(MO.getReg());
620 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
622 const char *Modifier) {
623 if (Modifier && strcmp(Modifier, "label") == 0) {
624 printPCLabel(MI, Op+1, O);
628 const MachineOperand &MO1 = MI->getOperand(Op);
629 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
630 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
634 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
636 const MachineOperand &MO = MI->getOperand(Op);
637 uint32_t v = ~MO.getImm();
638 int32_t lsb = CountTrailingZeros_32(v);
639 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
640 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
641 O << "#" << lsb << ", #" << width;
644 //===--------------------------------------------------------------------===//
646 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
648 O << "#" << MI->getOperand(Op).getImm() * 4;
652 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
654 // (3 - the number of trailing zeros) is the number of then / else.
655 unsigned Mask = MI->getOperand(Op).getImm();
656 unsigned CondBit0 = Mask >> 4 & 1;
657 unsigned NumTZ = CountTrailingZeros_32(Mask);
658 assert(NumTZ <= 3 && "Invalid IT mask!");
659 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
660 bool T = ((Mask >> Pos) & 1) == CondBit0;
669 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
671 const MachineOperand &MO1 = MI->getOperand(Op);
672 const MachineOperand &MO2 = MI->getOperand(Op+1);
673 O << "[" << getRegisterName(MO1.getReg());
674 O << ", " << getRegisterName(MO2.getReg()) << "]";
678 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
681 const MachineOperand &MO1 = MI->getOperand(Op);
682 const MachineOperand &MO2 = MI->getOperand(Op+1);
683 const MachineOperand &MO3 = MI->getOperand(Op+2);
685 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
686 printOperand(MI, Op, O);
690 O << "[" << getRegisterName(MO1.getReg());
692 O << ", " << getRegisterName(MO3.getReg());
693 else if (unsigned ImmOffs = MO2.getImm())
694 O << ", #" << ImmOffs * Scale;
699 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
701 printThumbAddrModeRI5Operand(MI, Op, O, 1);
704 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
706 printThumbAddrModeRI5Operand(MI, Op, O, 2);
709 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
711 printThumbAddrModeRI5Operand(MI, Op, O, 4);
714 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
716 const MachineOperand &MO1 = MI->getOperand(Op);
717 const MachineOperand &MO2 = MI->getOperand(Op+1);
718 O << "[" << getRegisterName(MO1.getReg());
719 if (unsigned ImmOffs = MO2.getImm())
720 O << ", #" << ImmOffs*4;
724 //===--------------------------------------------------------------------===//
726 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
727 // register with shift forms.
729 // REG IMM, SH_OPC - e.g. R5, LSL #3
730 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
732 const MachineOperand &MO1 = MI->getOperand(OpNum);
733 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
735 unsigned Reg = MO1.getReg();
736 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
737 O << getRegisterName(Reg);
739 // Print the shift opc.
741 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
744 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
745 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
748 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
751 const MachineOperand &MO1 = MI->getOperand(OpNum);
752 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
754 O << "[" << getRegisterName(MO1.getReg());
756 unsigned OffImm = MO2.getImm();
757 if (OffImm) // Don't print +0.
758 O << ", #" << OffImm;
762 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
765 const MachineOperand &MO1 = MI->getOperand(OpNum);
766 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
768 O << "[" << getRegisterName(MO1.getReg());
770 int32_t OffImm = (int32_t)MO2.getImm();
773 O << ", #-" << -OffImm;
775 O << ", #" << OffImm;
779 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
782 const MachineOperand &MO1 = MI->getOperand(OpNum);
783 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
785 O << "[" << getRegisterName(MO1.getReg());
787 int32_t OffImm = (int32_t)MO2.getImm() / 4;
790 O << ", #-" << -OffImm * 4;
792 O << ", #" << OffImm * 4;
796 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
799 const MachineOperand &MO1 = MI->getOperand(OpNum);
800 int32_t OffImm = (int32_t)MO1.getImm();
803 O << "#-" << -OffImm;
808 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
811 const MachineOperand &MO1 = MI->getOperand(OpNum);
812 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
813 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
815 O << "[" << getRegisterName(MO1.getReg());
817 assert(MO2.getReg() && "Invalid so_reg load / store address!");
818 O << ", " << getRegisterName(MO2.getReg());
820 unsigned ShAmt = MO3.getImm();
822 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
823 O << ", lsl #" << ShAmt;
829 //===--------------------------------------------------------------------===//
831 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
833 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
835 O << ARMCondCodeToString(CC);
838 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
841 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
842 O << ARMCondCodeToString(CC);
845 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
847 unsigned Reg = MI->getOperand(OpNum).getReg();
849 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
854 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
856 int Id = (int)MI->getOperand(OpNum).getImm();
857 O << MAI->getPrivateGlobalPrefix()
858 << "PC" << getFunctionNumber() << "_" << Id;
861 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
864 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
865 if (MI->getOperand(i).isImplicit())
867 if ((int)i != OpNum) O << ", ";
868 printOperand(MI, i, O);
873 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
874 raw_ostream &O, const char *Modifier) {
875 assert(Modifier && "This operand only works with a modifier!");
876 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
878 if (!strcmp(Modifier, "label")) {
879 unsigned ID = MI->getOperand(OpNum).getImm();
880 OutStreamer.EmitLabel(GetCPISymbol(ID));
882 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
883 unsigned CPI = MI->getOperand(OpNum).getIndex();
885 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
887 if (MCPE.isMachineConstantPoolEntry()) {
888 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
890 EmitGlobalConstant(MCPE.Val.ConstVal);
895 MCSymbol *ARMAsmPrinter::
896 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
897 const MachineBasicBlock *MBB) const {
898 SmallString<60> Name;
899 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
900 << getFunctionNumber() << '_' << uid << '_' << uid2
901 << "_set_" << MBB->getNumber();
902 return OutContext.GetOrCreateSymbol(Name.str());
905 MCSymbol *ARMAsmPrinter::
906 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
907 SmallString<60> Name;
908 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
909 << getFunctionNumber() << '_' << uid << '_' << uid2;
910 return OutContext.GetOrCreateSymbol(Name.str());
913 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
915 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
917 const MachineOperand &MO1 = MI->getOperand(OpNum);
918 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
920 unsigned JTI = MO1.getIndex();
921 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
922 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
924 O << *JTISymbol << ":\n";
926 const char *JTEntryDirective = MAI->getData32bitsDirective();
928 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
929 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
930 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
931 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
932 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
933 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
934 MachineBasicBlock *MBB = JTBBs[i];
935 bool isNew = JTSets.insert(MBB);
937 if (UseSet && isNew) {
939 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
940 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
943 O << JTEntryDirective << ' ';
945 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
946 else if (TM.getRelocationModel() == Reloc::PIC_)
947 O << *MBB->getSymbol() << '-' << *JTISymbol;
949 O << *MBB->getSymbol();
956 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
958 const MachineOperand &MO1 = MI->getOperand(OpNum);
959 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
960 unsigned JTI = MO1.getIndex();
962 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
964 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
966 O << *JTISymbol << ":\n";
968 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
969 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
970 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
971 bool ByteOffset = false, HalfWordOffset = false;
972 if (MI->getOpcode() == ARM::t2TBB)
974 else if (MI->getOpcode() == ARM::t2TBH)
975 HalfWordOffset = true;
977 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
978 MachineBasicBlock *MBB = JTBBs[i];
980 O << MAI->getData8bitsDirective();
981 else if (HalfWordOffset)
982 O << MAI->getData16bitsDirective();
984 if (ByteOffset || HalfWordOffset)
985 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
987 O << "\tb.w " << *MBB->getSymbol();
994 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
996 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
997 if (MI->getOpcode() == ARM::t2TBH)
1002 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1004 O << MI->getOperand(OpNum).getImm();
1007 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1009 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1010 O << '#' << FP->getValueAPF().convertToFloat();
1012 O << "\t\t" << MAI->getCommentString() << ' ';
1013 WriteAsOperand(O, FP, /*PrintType=*/false);
1017 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1019 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1020 O << '#' << FP->getValueAPF().convertToDouble();
1022 O << "\t\t" << MAI->getCommentString() << ' ';
1023 WriteAsOperand(O, FP, /*PrintType=*/false);
1027 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1029 unsigned Imm = MI->getOperand(OpNum).getImm();
1030 unsigned OpCmode = (Imm >> 8) & 0x1f;
1031 unsigned Imm8 = Imm & 0xff;
1034 if (OpCmode == 0xe) {
1035 // 8-bit vector elements
1037 } else if ((OpCmode & 0xc) == 0x8) {
1038 // 16-bit vector elements
1039 unsigned ByteNum = (OpCmode & 0x6) >> 1;
1040 Val = Imm8 << (8 * ByteNum);
1041 } else if ((OpCmode & 0x8) == 0) {
1042 // 32-bit vector elements, zero with one byte set
1043 unsigned ByteNum = (OpCmode & 0x6) >> 1;
1044 Val = Imm8 << (8 * ByteNum);
1045 } else if ((OpCmode & 0xe) == 0xc) {
1046 // 32-bit vector elements, one byte with low bits set
1047 unsigned ByteNum = (OpCmode & 0x1);
1048 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
1049 } else if (OpCmode == 0x1e) {
1050 // 64-bit vector elements
1051 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
1052 if ((Imm >> ByteNum) & 1)
1053 Val |= (uint64_t)0xff << (8 * ByteNum);
1056 assert(false && "Unsupported NEON immediate");
1058 O << "#0x" << utohexstr(Val);
1061 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1062 unsigned AsmVariant, const char *ExtraCode,
1064 // Does this asm operand have a single letter operand modifier?
1065 if (ExtraCode && ExtraCode[0]) {
1066 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1068 switch (ExtraCode[0]) {
1069 default: return true; // Unknown modifier.
1070 case 'a': // Print as a memory address.
1071 if (MI->getOperand(OpNum).isReg()) {
1072 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1076 case 'c': // Don't print "#" before an immediate operand.
1077 if (!MI->getOperand(OpNum).isImm())
1079 printNoHashImmediate(MI, OpNum, O);
1081 case 'P': // Print a VFP double precision register.
1082 case 'q': // Print a NEON quad precision register.
1083 printOperand(MI, OpNum, O);
1088 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1093 printOperand(MI, OpNum, O);
1097 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1098 unsigned OpNum, unsigned AsmVariant,
1099 const char *ExtraCode,
1101 if (ExtraCode && ExtraCode[0])
1102 return true; // Unknown modifier.
1104 const MachineOperand &MO = MI->getOperand(OpNum);
1105 assert(MO.isReg() && "unexpected inline asm memory operand");
1106 O << "[" << getRegisterName(MO.getReg()) << "]";
1110 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1112 printInstructionThroughMCStreamer(MI);
1116 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1119 SmallString<128> Str;
1120 raw_svector_ostream OS(Str);
1121 if (MI->getOpcode() == ARM::DBG_VALUE) {
1122 unsigned NOps = MI->getNumOperands();
1124 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1125 // cast away const; DIetc do not take const operands for some reason.
1126 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1129 // Frame address. Currently handles register +- offset only.
1130 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1131 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1134 printOperand(MI, NOps-2, OS);
1135 OutStreamer.EmitRawText(OS.str());
1139 printInstruction(MI, OS);
1140 OutStreamer.EmitRawText(OS.str());
1142 // Make sure the instruction that follows TBB is 2-byte aligned.
1143 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1144 if (MI->getOpcode() == ARM::t2TBB)
1148 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1149 if (Subtarget->isTargetDarwin()) {
1150 Reloc::Model RelocM = TM.getRelocationModel();
1151 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1152 // Declare all the text sections up front (before the DWARF sections
1153 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1154 // them together at the beginning of the object file. This helps
1155 // avoid out-of-range branches that are due a fundamental limitation of
1156 // the way symbol offsets are encoded with the current Darwin ARM
1158 const TargetLoweringObjectFileMachO &TLOFMacho =
1159 static_cast<const TargetLoweringObjectFileMachO &>(
1160 getObjFileLowering());
1161 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1162 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1163 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1164 if (RelocM == Reloc::DynamicNoPIC) {
1165 const MCSection *sect =
1166 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1167 MCSectionMachO::S_SYMBOL_STUBS,
1168 12, SectionKind::getText());
1169 OutStreamer.SwitchSection(sect);
1171 const MCSection *sect =
1172 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1173 MCSectionMachO::S_SYMBOL_STUBS,
1174 16, SectionKind::getText());
1175 OutStreamer.SwitchSection(sect);
1180 // Use unified assembler syntax.
1181 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1183 // Emit ARM Build Attributes
1184 if (Subtarget->isTargetELF()) {
1186 std::string CPUString = Subtarget->getCPUString();
1187 if (CPUString != "generic")
1188 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1190 // FIXME: Emit FPU type
1191 if (Subtarget->hasVFP2())
1192 OutStreamer.EmitRawText("\t.eabi_attribute " +
1193 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1195 // Signal various FP modes.
1196 if (!UnsafeFPMath) {
1197 OutStreamer.EmitRawText("\t.eabi_attribute " +
1198 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1199 OutStreamer.EmitRawText("\t.eabi_attribute " +
1200 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1203 if (FiniteOnlyFPMath())
1204 OutStreamer.EmitRawText("\t.eabi_attribute " +
1205 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1207 OutStreamer.EmitRawText("\t.eabi_attribute " +
1208 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1210 // 8-bytes alignment stuff.
1211 OutStreamer.EmitRawText("\t.eabi_attribute " +
1212 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1213 OutStreamer.EmitRawText("\t.eabi_attribute " +
1214 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1216 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1217 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1218 OutStreamer.EmitRawText("\t.eabi_attribute " +
1219 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1220 OutStreamer.EmitRawText("\t.eabi_attribute " +
1221 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1223 // FIXME: Should we signal R9 usage?
1228 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1229 if (Subtarget->isTargetDarwin()) {
1230 // All darwin targets use mach-o.
1231 const TargetLoweringObjectFileMachO &TLOFMacho =
1232 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1233 MachineModuleInfoMachO &MMIMacho =
1234 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1236 // Output non-lazy-pointers for external and common global variables.
1237 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1239 if (!Stubs.empty()) {
1240 // Switch with ".non_lazy_symbol_pointer" directive.
1241 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1243 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1245 OutStreamer.EmitLabel(Stubs[i].first);
1246 // .indirect_symbol _foo
1247 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1248 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1251 // External to current translation unit.
1252 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1254 // Internal to current translation unit.
1256 // When we place the LSDA into the TEXT section, the type info pointers
1257 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1258 // However, sometimes the types are local to the file. So we need to
1259 // fill in the value for the NLP in those cases.
1260 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1262 4/*size*/, 0/*addrspace*/);
1266 OutStreamer.AddBlankLine();
1269 Stubs = MMIMacho.GetHiddenGVStubList();
1270 if (!Stubs.empty()) {
1271 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1273 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1275 OutStreamer.EmitLabel(Stubs[i].first);
1277 OutStreamer.EmitValue(MCSymbolRefExpr::
1278 Create(Stubs[i].second.getPointer(),
1280 4/*size*/, 0/*addrspace*/);
1284 OutStreamer.AddBlankLine();
1287 // Funny Darwin hack: This flag tells the linker that no global symbols
1288 // contain code that falls through to other global symbols (e.g. the obvious
1289 // implementation of multiple entry points). If this doesn't occur, the
1290 // linker can safely perform dead code stripping. Since LLVM never
1291 // generates code that does this, it is always safe to set.
1292 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1296 //===----------------------------------------------------------------------===//
1298 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1299 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1300 switch (MI->getOpcode()) {
1301 case ARM::t2MOVi32imm:
1302 assert(0 && "Should be lowered by thumb2it pass");
1304 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1305 // This is a pseudo op for a label + instruction sequence, which looks like:
1308 // This adds the address of LPC0 to r0.
1311 // FIXME: MOVE TO SHARED PLACE.
1312 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1313 const char *Prefix = MAI->getPrivateGlobalPrefix();
1314 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1315 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1316 OutStreamer.EmitLabel(Label);
1319 // Form and emit tha dd.
1321 AddInst.setOpcode(ARM::ADDrr);
1322 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1323 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1324 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1325 OutStreamer.EmitInstruction(AddInst);
1328 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1329 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1330 /// in the function. The first operand is the ID# for this instruction, the
1331 /// second is the index into the MachineConstantPool that this is, the third
1332 /// is the size in bytes of this constant pool entry.
1333 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1334 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1337 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1339 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1340 if (MCPE.isMachineConstantPoolEntry())
1341 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1343 EmitGlobalConstant(MCPE.Val.ConstVal);
1347 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1348 // This is a hack that lowers as a two instruction sequence.
1349 unsigned DstReg = MI->getOperand(0).getReg();
1350 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1352 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1353 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1357 TmpInst.setOpcode(ARM::MOVi);
1358 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1359 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1362 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1363 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1365 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1366 OutStreamer.EmitInstruction(TmpInst);
1371 TmpInst.setOpcode(ARM::ORRri);
1372 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1373 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1374 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1376 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1377 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1379 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1380 OutStreamer.EmitInstruction(TmpInst);
1384 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1385 // This is a hack that lowers as a two instruction sequence.
1386 unsigned DstReg = MI->getOperand(0).getReg();
1387 const MachineOperand &MO = MI->getOperand(1);
1390 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1391 V1 = MCOperand::CreateImm(ImmVal & 65535);
1392 V2 = MCOperand::CreateImm(ImmVal >> 16);
1393 } else if (MO.isGlobal()) {
1394 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
1395 const MCSymbolRefExpr *SymRef1 =
1396 MCSymbolRefExpr::Create(Symbol,
1397 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1398 const MCSymbolRefExpr *SymRef2 =
1399 MCSymbolRefExpr::Create(Symbol,
1400 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1401 V1 = MCOperand::CreateExpr(SymRef1);
1402 V2 = MCOperand::CreateExpr(SymRef2);
1405 llvm_unreachable("cannot handle this operand");
1410 TmpInst.setOpcode(ARM::MOVi16);
1411 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1412 TmpInst.addOperand(V1); // lower16(imm)
1415 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1416 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1418 OutStreamer.EmitInstruction(TmpInst);
1423 TmpInst.setOpcode(ARM::MOVTi16);
1424 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1425 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1426 TmpInst.addOperand(V2); // upper16(imm)
1429 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1430 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1432 OutStreamer.EmitInstruction(TmpInst);
1440 MCInstLowering.Lower(MI, TmpInst);
1441 OutStreamer.EmitInstruction(TmpInst);
1444 //===----------------------------------------------------------------------===//
1445 // Target Registry Stuff
1446 //===----------------------------------------------------------------------===//
1448 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1449 unsigned SyntaxVariant,
1450 const MCAsmInfo &MAI) {
1451 if (SyntaxVariant == 0)
1452 return new ARMInstPrinter(MAI, false);
1456 // Force static initialization.
1457 extern "C" void LLVMInitializeARMAsmPrinter() {
1458 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1459 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1461 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1462 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);