1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void PrintGlobalVariable(const GlobalVariable* GVar);
163 void printInstruction(const MachineInstr *MI); // autogenerated.
164 static const char *getRegisterName(unsigned RegNo);
166 void printMachineInstruction(const MachineInstr *MI);
167 bool runOnMachineFunction(MachineFunction &F);
168 void EmitStartOfAsmFile(Module &M);
169 void EmitEndOfAsmFile(Module &M);
171 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
173 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
174 printDataDirective(MCPV->getType());
176 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
177 SmallString<128> TmpNameStr;
179 if (ACPV->isLSDA()) {
180 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
181 "_LSDA_" << getFunctionNumber();
182 O << TmpNameStr.str();
183 } else if (ACPV->isBlockAddress()) {
184 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
185 } else if (ACPV->isGlobalValue()) {
186 GlobalValue *GV = ACPV->getGV();
187 bool isIndirect = Subtarget->isTargetDarwin() &&
188 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
190 GetGlobalValueSymbol(GV)->print(O, MAI);
192 // FIXME: Remove this when Darwin transition to @GOT like syntax.
193 MCSymbol *Sym = GetPrivateGlobalValueSymbolStub(GV, "$non_lazy_ptr");
196 MachineModuleInfoMachO &MMIMachO =
197 MMI->getObjFileInfo<MachineModuleInfoMachO>();
198 const MCSymbol *&StubSym =
199 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
200 MMIMachO.getGVStubEntry(Sym);
202 StubSym = GetGlobalValueSymbol(GV);
205 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
206 GetExternalSymbolSymbol(ACPV->getSymbol())->print(O, MAI);
209 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
210 if (ACPV->getPCAdjustment() != 0) {
211 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
212 << getFunctionNumber() << "_" << ACPV->getLabelId()
213 << "+" << (unsigned)ACPV->getPCAdjustment();
214 if (ACPV->mustAddCurrentAddress())
221 void getAnalysisUsage(AnalysisUsage &AU) const {
222 AsmPrinter::getAnalysisUsage(AU);
223 AU.setPreservesAll();
224 AU.addRequired<MachineModuleInfo>();
225 AU.addRequired<DwarfWriter>();
228 } // end of anonymous namespace
230 #include "ARMGenAsmWriter.inc"
232 /// runOnMachineFunction - This uses the printInstruction()
233 /// method to print assembly for each instruction.
235 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
238 AFI = MF.getInfo<ARMFunctionInfo>();
239 MCP = MF.getConstantPool();
241 SetupMachineFunction(MF);
244 // NOTE: we don't print out constant pools here, they are handled as
249 // Print out labels for the function.
250 const Function *F = MF.getFunction();
251 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
253 switch (F->getLinkage()) {
254 default: llvm_unreachable("Unknown linkage type!");
255 case Function::PrivateLinkage:
256 case Function::InternalLinkage:
258 case Function::ExternalLinkage:
260 CurrentFnSym->print(O, MAI);
263 case Function::LinkerPrivateLinkage:
264 case Function::WeakAnyLinkage:
265 case Function::WeakODRLinkage:
266 case Function::LinkOnceAnyLinkage:
267 case Function::LinkOnceODRLinkage:
268 if (Subtarget->isTargetDarwin()) {
270 CurrentFnSym->print(O, MAI);
272 O << "\t.weak_definition\t";
273 CurrentFnSym->print(O, MAI);
276 O << MAI->getWeakRefDirective();
277 CurrentFnSym->print(O, MAI);
283 printVisibility(CurrentFnSym, F->getVisibility());
285 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
286 if (AFI->isThumbFunction()) {
287 EmitAlignment(FnAlign, F, AFI->getAlign());
288 O << "\t.code\t16\n";
289 O << "\t.thumb_func";
290 if (Subtarget->isTargetDarwin()) {
292 CurrentFnSym->print(O, MAI);
296 EmitAlignment(FnAlign, F);
299 CurrentFnSym->print(O, MAI);
301 // Emit pre-function debug information.
302 DW->BeginFunction(&MF);
304 if (Subtarget->isTargetDarwin()) {
305 // If the function is empty, then we need to emit *something*. Otherwise,
306 // the function's label might be associated with something that it wasn't
307 // meant to be associated with. We emit a noop in this situation.
308 MachineFunction::iterator I = MF.begin();
310 if (++I == MF.end() && MF.front().empty())
314 // Print out code for the function.
315 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
317 // Print a label for the basic block.
319 EmitBasicBlockStart(I);
321 // Print the assembly for the instruction.
322 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
324 printMachineInstruction(II);
327 if (MAI->hasDotTypeDotSizeDirective()) {
329 CurrentFnSym->print(O, MAI);
331 CurrentFnSym->print(O, MAI);
335 // Emit post-function debug information.
336 DW->EndFunction(&MF);
341 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
342 const char *Modifier) {
343 const MachineOperand &MO = MI->getOperand(OpNum);
344 unsigned TF = MO.getTargetFlags();
346 switch (MO.getType()) {
348 assert(0 && "<unknown operand type>");
349 case MachineOperand::MO_Register: {
350 unsigned Reg = MO.getReg();
351 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
352 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
353 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
354 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
356 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
358 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
359 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
360 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
361 &ARM::DPR_VFP2RegClass);
362 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
364 assert(!MO.getSubReg() && "Subregs should be eliminated!");
365 O << getRegisterName(Reg);
369 case MachineOperand::MO_Immediate: {
370 int64_t Imm = MO.getImm();
372 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
373 (TF & ARMII::MO_LO16))
375 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
376 (TF & ARMII::MO_HI16))
381 case MachineOperand::MO_MachineBasicBlock:
382 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
384 case MachineOperand::MO_GlobalAddress: {
385 bool isCallOp = Modifier && !strcmp(Modifier, "call");
386 GlobalValue *GV = MO.getGlobal();
388 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
389 (TF & ARMII::MO_LO16))
391 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
392 (TF & ARMII::MO_HI16))
394 GetGlobalValueSymbol(GV)->print(O, MAI);
396 printOffset(MO.getOffset());
398 if (isCallOp && Subtarget->isTargetELF() &&
399 TM.getRelocationModel() == Reloc::PIC_)
403 case MachineOperand::MO_ExternalSymbol: {
404 bool isCallOp = Modifier && !strcmp(Modifier, "call");
405 GetExternalSymbolSymbol(MO.getSymbolName())->print(O, MAI);
407 if (isCallOp && Subtarget->isTargetELF() &&
408 TM.getRelocationModel() == Reloc::PIC_)
412 case MachineOperand::MO_ConstantPoolIndex:
413 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
414 << '_' << MO.getIndex();
416 case MachineOperand::MO_JumpTableIndex:
417 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
418 << '_' << MO.getIndex();
423 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
424 const MCAsmInfo *MAI) {
425 // Break it up into two parts that make up a shifter immediate.
426 V = ARM_AM::getSOImmVal(V);
427 assert(V != -1 && "Not a valid so_imm value!");
429 unsigned Imm = ARM_AM::getSOImmValImm(V);
430 unsigned Rot = ARM_AM::getSOImmValRot(V);
432 // Print low-level immediate formation info, per
433 // A5.1.3: "Data-processing operands - Immediate".
435 O << "#" << Imm << ", " << Rot;
436 // Pretty printed version.
438 O.PadToColumn(MAI->getCommentColumn());
439 O << MAI->getCommentString() << ' ';
440 O << (int)ARM_AM::rotr32(Imm, Rot);
447 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
448 /// immediate in bits 0-7.
449 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
450 const MachineOperand &MO = MI->getOperand(OpNum);
451 assert(MO.isImm() && "Not a valid so_imm value!");
452 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
455 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
456 /// followed by an 'orr' to materialize.
457 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
458 const MachineOperand &MO = MI->getOperand(OpNum);
459 assert(MO.isImm() && "Not a valid so_imm value!");
460 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
461 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
462 printSOImm(O, V1, VerboseAsm, MAI);
464 printPredicateOperand(MI, 2);
470 printSOImm(O, V2, VerboseAsm, MAI);
473 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
474 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
476 // REG REG 0,SH_OPC - e.g. R5, ROR R3
477 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
478 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
479 const MachineOperand &MO1 = MI->getOperand(Op);
480 const MachineOperand &MO2 = MI->getOperand(Op+1);
481 const MachineOperand &MO3 = MI->getOperand(Op+2);
483 O << getRegisterName(MO1.getReg());
485 // Print the shift opc.
487 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
491 O << getRegisterName(MO2.getReg());
492 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
494 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
498 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
499 const MachineOperand &MO1 = MI->getOperand(Op);
500 const MachineOperand &MO2 = MI->getOperand(Op+1);
501 const MachineOperand &MO3 = MI->getOperand(Op+2);
503 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
504 printOperand(MI, Op);
508 O << "[" << getRegisterName(MO1.getReg());
511 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
513 << (char)ARM_AM::getAM2Op(MO3.getImm())
514 << ARM_AM::getAM2Offset(MO3.getImm());
520 << (char)ARM_AM::getAM2Op(MO3.getImm())
521 << getRegisterName(MO2.getReg());
523 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
525 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
530 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
531 const MachineOperand &MO1 = MI->getOperand(Op);
532 const MachineOperand &MO2 = MI->getOperand(Op+1);
535 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
536 assert(ImmOffs && "Malformed indexed load / store!");
538 << (char)ARM_AM::getAM2Op(MO2.getImm())
543 O << (char)ARM_AM::getAM2Op(MO2.getImm())
544 << getRegisterName(MO1.getReg());
546 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
548 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
552 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
553 const MachineOperand &MO1 = MI->getOperand(Op);
554 const MachineOperand &MO2 = MI->getOperand(Op+1);
555 const MachineOperand &MO3 = MI->getOperand(Op+2);
557 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
558 O << "[" << getRegisterName(MO1.getReg());
562 << (char)ARM_AM::getAM3Op(MO3.getImm())
563 << getRegisterName(MO2.getReg())
568 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
570 << (char)ARM_AM::getAM3Op(MO3.getImm())
575 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
576 const MachineOperand &MO1 = MI->getOperand(Op);
577 const MachineOperand &MO2 = MI->getOperand(Op+1);
580 O << (char)ARM_AM::getAM3Op(MO2.getImm())
581 << getRegisterName(MO1.getReg());
585 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
586 assert(ImmOffs && "Malformed indexed load / store!");
588 << (char)ARM_AM::getAM3Op(MO2.getImm())
592 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
593 const char *Modifier) {
594 const MachineOperand &MO1 = MI->getOperand(Op);
595 const MachineOperand &MO2 = MI->getOperand(Op+1);
596 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
597 if (Modifier && strcmp(Modifier, "submode") == 0) {
598 if (MO1.getReg() == ARM::SP) {
600 bool isLDM = (MI->getOpcode() == ARM::LDM ||
601 MI->getOpcode() == ARM::LDM_RET ||
602 MI->getOpcode() == ARM::t2LDM ||
603 MI->getOpcode() == ARM::t2LDM_RET);
604 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
606 O << ARM_AM::getAMSubModeStr(Mode);
607 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
608 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
609 if (Mode == ARM_AM::ia)
612 printOperand(MI, Op);
613 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
618 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
619 const char *Modifier) {
620 const MachineOperand &MO1 = MI->getOperand(Op);
621 const MachineOperand &MO2 = MI->getOperand(Op+1);
623 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
624 printOperand(MI, Op);
628 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
630 if (Modifier && strcmp(Modifier, "submode") == 0) {
631 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
632 O << ARM_AM::getAMSubModeStr(Mode);
634 } else if (Modifier && strcmp(Modifier, "base") == 0) {
635 // Used for FSTM{D|S} and LSTM{D|S} operations.
636 O << getRegisterName(MO1.getReg());
637 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
642 O << "[" << getRegisterName(MO1.getReg());
644 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
646 << (char)ARM_AM::getAM5Op(MO2.getImm())
652 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
653 const MachineOperand &MO1 = MI->getOperand(Op);
654 const MachineOperand &MO2 = MI->getOperand(Op+1);
655 const MachineOperand &MO3 = MI->getOperand(Op+2);
656 const MachineOperand &MO4 = MI->getOperand(Op+3);
658 O << "[" << getRegisterName(MO1.getReg());
660 // FIXME: Both darwin as and GNU as violate ARM docs here.
661 O << ", :" << MO4.getImm();
665 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
666 if (MO2.getReg() == 0)
669 O << ", " << getRegisterName(MO2.getReg());
673 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
674 const char *Modifier) {
675 if (Modifier && strcmp(Modifier, "label") == 0) {
676 printPCLabel(MI, Op+1);
680 const MachineOperand &MO1 = MI->getOperand(Op);
681 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
682 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
686 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
687 const MachineOperand &MO = MI->getOperand(Op);
688 uint32_t v = ~MO.getImm();
689 int32_t lsb = CountTrailingZeros_32(v);
690 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
691 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
692 O << "#" << lsb << ", #" << width;
695 //===--------------------------------------------------------------------===//
697 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
698 O << "#" << MI->getOperand(Op).getImm() * 4;
702 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
703 // (3 - the number of trailing zeros) is the number of then / else.
704 unsigned Mask = MI->getOperand(Op).getImm();
705 unsigned NumTZ = CountTrailingZeros_32(Mask);
706 assert(NumTZ <= 3 && "Invalid IT mask!");
707 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
708 bool T = (Mask & (1 << Pos)) == 0;
717 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
718 const MachineOperand &MO1 = MI->getOperand(Op);
719 const MachineOperand &MO2 = MI->getOperand(Op+1);
720 O << "[" << getRegisterName(MO1.getReg());
721 O << ", " << getRegisterName(MO2.getReg()) << "]";
725 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
727 const MachineOperand &MO1 = MI->getOperand(Op);
728 const MachineOperand &MO2 = MI->getOperand(Op+1);
729 const MachineOperand &MO3 = MI->getOperand(Op+2);
731 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
732 printOperand(MI, Op);
736 O << "[" << getRegisterName(MO1.getReg());
738 O << ", " << getRegisterName(MO3.getReg());
739 else if (unsigned ImmOffs = MO2.getImm())
740 O << ", #+" << ImmOffs * Scale;
745 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
746 printThumbAddrModeRI5Operand(MI, Op, 1);
749 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
750 printThumbAddrModeRI5Operand(MI, Op, 2);
753 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
754 printThumbAddrModeRI5Operand(MI, Op, 4);
757 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
758 const MachineOperand &MO1 = MI->getOperand(Op);
759 const MachineOperand &MO2 = MI->getOperand(Op+1);
760 O << "[" << getRegisterName(MO1.getReg());
761 if (unsigned ImmOffs = MO2.getImm())
762 O << ", #+" << ImmOffs*4;
766 //===--------------------------------------------------------------------===//
768 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
769 // register with shift forms.
771 // REG IMM, SH_OPC - e.g. R5, LSL #3
772 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
773 const MachineOperand &MO1 = MI->getOperand(OpNum);
774 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
776 unsigned Reg = MO1.getReg();
777 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
778 O << getRegisterName(Reg);
780 // Print the shift opc.
782 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
785 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
786 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
789 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
791 const MachineOperand &MO1 = MI->getOperand(OpNum);
792 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
794 O << "[" << getRegisterName(MO1.getReg());
796 unsigned OffImm = MO2.getImm();
797 if (OffImm) // Don't print +0.
798 O << ", #+" << OffImm;
802 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
804 const MachineOperand &MO1 = MI->getOperand(OpNum);
805 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
807 O << "[" << getRegisterName(MO1.getReg());
809 int32_t OffImm = (int32_t)MO2.getImm();
812 O << ", #-" << -OffImm;
814 O << ", #+" << OffImm;
818 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
820 const MachineOperand &MO1 = MI->getOperand(OpNum);
821 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
823 O << "[" << getRegisterName(MO1.getReg());
825 int32_t OffImm = (int32_t)MO2.getImm() / 4;
828 O << ", #-" << -OffImm * 4;
830 O << ", #+" << OffImm * 4;
834 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
836 const MachineOperand &MO1 = MI->getOperand(OpNum);
837 int32_t OffImm = (int32_t)MO1.getImm();
840 O << "#-" << -OffImm;
845 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
847 const MachineOperand &MO1 = MI->getOperand(OpNum);
848 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
849 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
851 O << "[" << getRegisterName(MO1.getReg());
853 assert(MO2.getReg() && "Invalid so_reg load / store address!");
854 O << ", " << getRegisterName(MO2.getReg());
856 unsigned ShAmt = MO3.getImm();
858 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
859 O << ", lsl #" << ShAmt;
865 //===--------------------------------------------------------------------===//
867 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
868 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
870 O << ARMCondCodeToString(CC);
873 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
874 unsigned Reg = MI->getOperand(OpNum).getReg();
876 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
881 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
882 int Id = (int)MI->getOperand(OpNum).getImm();
883 O << MAI->getPrivateGlobalPrefix()
884 << "PC" << getFunctionNumber() << "_" << Id;
887 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
889 // Always skip the first operand, it's the optional (and implicit writeback).
890 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
891 if (MI->getOperand(i).isImplicit())
893 if ((int)i != OpNum+1) O << ", ";
899 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
900 const char *Modifier) {
901 assert(Modifier && "This operand only works with a modifier!");
902 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
904 if (!strcmp(Modifier, "label")) {
905 unsigned ID = MI->getOperand(OpNum).getImm();
906 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
907 << '_' << ID << ":\n";
909 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
910 unsigned CPI = MI->getOperand(OpNum).getIndex();
912 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
914 if (MCPE.isMachineConstantPoolEntry()) {
915 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
917 EmitGlobalConstant(MCPE.Val.ConstVal);
922 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
923 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
925 const MachineOperand &MO1 = MI->getOperand(OpNum);
926 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
927 unsigned JTI = MO1.getIndex();
928 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
929 << '_' << JTI << '_' << MO2.getImm() << ":\n";
931 const char *JTEntryDirective = MAI->getData32bitsDirective();
933 const MachineFunction *MF = MI->getParent()->getParent();
934 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
935 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
936 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
937 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
938 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
939 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
940 MachineBasicBlock *MBB = JTBBs[i];
941 bool isNew = JTSets.insert(MBB);
944 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
946 O << JTEntryDirective << ' ';
948 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
949 << '_' << JTI << '_' << MO2.getImm()
950 << "_set_" << MBB->getNumber();
951 else if (TM.getRelocationModel() == Reloc::PIC_) {
952 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
953 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
954 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
956 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
963 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
964 const MachineOperand &MO1 = MI->getOperand(OpNum);
965 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
966 unsigned JTI = MO1.getIndex();
967 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
968 << '_' << JTI << '_' << MO2.getImm() << ":\n";
970 const MachineFunction *MF = MI->getParent()->getParent();
971 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
972 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
973 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
974 bool ByteOffset = false, HalfWordOffset = false;
975 if (MI->getOpcode() == ARM::t2TBB)
977 else if (MI->getOpcode() == ARM::t2TBH)
978 HalfWordOffset = true;
980 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
981 MachineBasicBlock *MBB = JTBBs[i];
983 O << MAI->getData8bitsDirective();
984 else if (HalfWordOffset)
985 O << MAI->getData16bitsDirective();
986 if (ByteOffset || HalfWordOffset) {
988 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
989 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
990 << '_' << JTI << '_' << MO2.getImm() << ")/2";
993 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
999 // Make sure the instruction that follows TBB is 2-byte aligned.
1000 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1001 if (ByteOffset && (JTBBs.size() & 1)) {
1007 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
1008 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1009 if (MI->getOpcode() == ARM::t2TBH)
1014 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
1015 O << MI->getOperand(OpNum).getImm();
1018 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1019 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1020 O << '#' << FP->getValueAPF().convertToFloat();
1022 O.PadToColumn(MAI->getCommentColumn());
1023 O << MAI->getCommentString() << ' ';
1024 WriteAsOperand(O, FP, /*PrintType=*/false);
1028 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1029 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1030 O << '#' << FP->getValueAPF().convertToDouble();
1032 O.PadToColumn(MAI->getCommentColumn());
1033 O << MAI->getCommentString() << ' ';
1034 WriteAsOperand(O, FP, /*PrintType=*/false);
1038 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1039 unsigned AsmVariant, const char *ExtraCode){
1040 // Does this asm operand have a single letter operand modifier?
1041 if (ExtraCode && ExtraCode[0]) {
1042 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1044 switch (ExtraCode[0]) {
1045 default: return true; // Unknown modifier.
1046 case 'a': // Print as a memory address.
1047 if (MI->getOperand(OpNum).isReg()) {
1048 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1052 case 'c': // Don't print "#" before an immediate operand.
1053 if (!MI->getOperand(OpNum).isImm())
1055 printNoHashImmediate(MI, OpNum);
1057 case 'P': // Print a VFP double precision register.
1058 case 'q': // Print a NEON quad precision register.
1059 printOperand(MI, OpNum);
1062 if (TM.getTargetData()->isLittleEndian())
1066 if (TM.getTargetData()->isBigEndian())
1069 case 'H': // Write second word of DI / DF reference.
1070 // Verify that this operand has two consecutive registers.
1071 if (!MI->getOperand(OpNum).isReg() ||
1072 OpNum+1 == MI->getNumOperands() ||
1073 !MI->getOperand(OpNum+1).isReg())
1075 ++OpNum; // Return the high-part.
1079 printOperand(MI, OpNum);
1083 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1084 unsigned OpNum, unsigned AsmVariant,
1085 const char *ExtraCode) {
1086 if (ExtraCode && ExtraCode[0])
1087 return true; // Unknown modifier.
1089 const MachineOperand &MO = MI->getOperand(OpNum);
1090 assert(MO.isReg() && "unexpected inline asm memory operand");
1091 O << "[" << getRegisterName(MO.getReg()) << "]";
1095 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1098 // Call the autogenerated instruction printer routines.
1099 processDebugLoc(MI, true);
1102 printInstructionThroughMCStreamer(MI);
1104 int Opc = MI->getOpcode();
1105 if (Opc == ARM::CONSTPOOL_ENTRY)
1108 printInstruction(MI);
1114 processDebugLoc(MI, false);
1117 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1118 if (Subtarget->isTargetDarwin()) {
1119 Reloc::Model RelocM = TM.getRelocationModel();
1120 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1121 // Declare all the text sections up front (before the DWARF sections
1122 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1123 // them together at the beginning of the object file. This helps
1124 // avoid out-of-range branches that are due a fundamental limitation of
1125 // the way symbol offsets are encoded with the current Darwin ARM
1127 TargetLoweringObjectFileMachO &TLOFMacho =
1128 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1129 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1130 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1131 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1132 if (RelocM == Reloc::DynamicNoPIC) {
1133 const MCSection *sect =
1134 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1135 MCSectionMachO::S_SYMBOL_STUBS,
1136 12, SectionKind::getText());
1137 OutStreamer.SwitchSection(sect);
1139 const MCSection *sect =
1140 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1141 MCSectionMachO::S_SYMBOL_STUBS,
1142 16, SectionKind::getText());
1143 OutStreamer.SwitchSection(sect);
1148 // Use unified assembler syntax.
1149 O << "\t.syntax unified\n";
1151 // Emit ARM Build Attributes
1152 if (Subtarget->isTargetELF()) {
1154 std::string CPUString = Subtarget->getCPUString();
1155 if (CPUString != "generic")
1156 O << "\t.cpu " << CPUString << '\n';
1158 // FIXME: Emit FPU type
1159 if (Subtarget->hasVFP2())
1160 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1162 // Signal various FP modes.
1164 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1165 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1167 if (FiniteOnlyFPMath())
1168 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1170 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1172 // 8-bytes alignment stuff.
1173 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1174 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1176 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1177 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1178 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1179 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1181 // FIXME: Should we signal R9 usage?
1185 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1186 const TargetData *TD = TM.getTargetData();
1188 if (!GVar->hasInitializer()) // External global require no code
1191 // Check to see if this is a special global used by LLVM, if so, emit it.
1193 if (EmitSpecialLLVMGlobal(GVar)) {
1194 if (Subtarget->isTargetDarwin() &&
1195 TM.getRelocationModel() == Reloc::Static) {
1196 if (GVar->getName() == "llvm.global_ctors")
1197 O << ".reference .constructors_used\n";
1198 else if (GVar->getName() == "llvm.global_dtors")
1199 O << ".reference .destructors_used\n";
1204 MCSymbol *GVarSym = GetGlobalValueSymbol(GVar);
1206 Constant *C = GVar->getInitializer();
1207 const Type *Type = C->getType();
1208 unsigned Size = TD->getTypeAllocSize(Type);
1209 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1210 bool isDarwin = Subtarget->isTargetDarwin();
1212 printVisibility(GVarSym, GVar->getVisibility());
1214 if (Subtarget->isTargetELF()) {
1216 GVarSym->print(O, MAI);
1220 const MCSection *TheSection =
1221 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1222 OutStreamer.SwitchSection(TheSection);
1224 // FIXME: get this stuff from section kind flags.
1225 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1226 // Don't put things that should go in the cstring section into "comm".
1227 !TheSection->getKind().isMergeableCString()) {
1228 if (GVar->hasExternalLinkage()) {
1229 if (const char *Directive = MAI->getZeroFillDirective()) {
1231 GVarSym->print(O, MAI);
1233 O << Directive << "__DATA, __common, ";
1234 GVarSym->print(O, MAI);
1235 O << ", " << Size << ", " << Align << "\n";
1240 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1241 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1244 if (GVar->hasLocalLinkage()) {
1245 O << MAI->getLCOMMDirective();
1246 GVarSym->print(O, MAI);
1247 O << ',' << Size << ',' << Align;
1248 } else if (GVar->hasCommonLinkage()) {
1249 O << MAI->getCOMMDirective();
1250 GVarSym->print(O, MAI);
1251 O << ',' << Size << ',' << Align;
1253 OutStreamer.SwitchSection(TheSection);
1255 GVarSym->print(O, MAI);
1256 O << '\n' << MAI->getWeakDefDirective();
1257 GVarSym->print(O, MAI);
1259 EmitAlignment(Align, GVar);
1260 GVarSym->print(O, MAI);
1263 O.PadToColumn(MAI->getCommentColumn());
1264 O << MAI->getCommentString() << ' ';
1265 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1268 EmitGlobalConstant(C);
1271 } else if (MAI->getLCOMMDirective() != NULL) {
1272 if (GVar->hasLocalLinkage()) {
1273 O << MAI->getLCOMMDirective();
1274 GVarSym->print(O, MAI);
1277 O << MAI->getCOMMDirective();
1278 GVarSym->print(O, MAI);
1280 if (MAI->getCOMMDirectiveTakesAlignment())
1281 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1284 if (GVar->hasLocalLinkage()) {
1286 GVarSym->print(O, MAI);
1289 O << MAI->getCOMMDirective();
1290 GVarSym->print(O, MAI);
1292 if (MAI->getCOMMDirectiveTakesAlignment())
1293 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1296 O.PadToColumn(MAI->getCommentColumn());
1297 O << MAI->getCommentString() << ' ';
1298 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1305 switch (GVar->getLinkage()) {
1306 case GlobalValue::CommonLinkage:
1307 case GlobalValue::LinkOnceAnyLinkage:
1308 case GlobalValue::LinkOnceODRLinkage:
1309 case GlobalValue::WeakAnyLinkage:
1310 case GlobalValue::WeakODRLinkage:
1311 case GlobalValue::LinkerPrivateLinkage:
1314 GVarSym->print(O, MAI);
1315 O << "\n\t.weak_definition ";
1316 GVarSym->print(O, MAI);
1320 GVarSym->print(O, MAI);
1324 case GlobalValue::AppendingLinkage:
1325 // FIXME: appending linkage variables should go into a section of
1326 // their name or something. For now, just emit them as external.
1327 case GlobalValue::ExternalLinkage:
1329 GVarSym->print(O, MAI);
1332 case GlobalValue::PrivateLinkage:
1333 case GlobalValue::InternalLinkage:
1336 llvm_unreachable("Unknown linkage type!");
1339 EmitAlignment(Align, GVar);
1340 GVarSym->print(O, MAI);
1343 O.PadToColumn(MAI->getCommentColumn());
1344 O << MAI->getCommentString() << ' ';
1345 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1348 if (MAI->hasDotTypeDotSizeDirective()) {
1350 GVarSym->print(O, MAI);
1351 O << ", " << Size << "\n";
1354 EmitGlobalConstant(C);
1359 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1360 if (Subtarget->isTargetDarwin()) {
1361 // All darwin targets use mach-o.
1362 TargetLoweringObjectFileMachO &TLOFMacho =
1363 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1364 MachineModuleInfoMachO &MMIMacho =
1365 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1369 // Output non-lazy-pointers for external and common global variables.
1370 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1372 if (!Stubs.empty()) {
1373 // Switch with ".non_lazy_symbol_pointer" directive.
1374 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1376 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1377 Stubs[i].first->print(O, MAI);
1378 O << ":\n\t.indirect_symbol ";
1379 Stubs[i].second->print(O, MAI);
1380 O << "\n\t.long\t0\n";
1384 Stubs = MMIMacho.GetHiddenGVStubList();
1385 if (!Stubs.empty()) {
1386 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1388 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1389 Stubs[i].first->print(O, MAI);
1391 Stubs[i].second->print(O, MAI);
1396 // Funny Darwin hack: This flag tells the linker that no global symbols
1397 // contain code that falls through to other global symbols (e.g. the obvious
1398 // implementation of multiple entry points). If this doesn't occur, the
1399 // linker can safely perform dead code stripping. Since LLVM never
1400 // generates code that does this, it is always safe to set.
1401 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1405 //===----------------------------------------------------------------------===//
1407 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1408 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1409 switch (MI->getOpcode()) {
1410 case ARM::t2MOVi32imm:
1411 assert(0 && "Should be lowered by thumb2it pass");
1413 case TargetInstrInfo::DBG_LABEL:
1414 case TargetInstrInfo::EH_LABEL:
1415 case TargetInstrInfo::GC_LABEL:
1418 case TargetInstrInfo::KILL:
1421 case TargetInstrInfo::INLINEASM:
1424 case TargetInstrInfo::IMPLICIT_DEF:
1425 printImplicitDef(MI);
1427 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1428 // This is a pseudo op for a label + instruction sequence, which looks like:
1431 // This adds the address of LPC0 to r0.
1434 // FIXME: MOVE TO SHARED PLACE.
1435 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1436 const char *Prefix = MAI->getPrivateGlobalPrefix();
1437 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1438 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1439 OutStreamer.EmitLabel(Label);
1442 // Form and emit tha dd.
1444 AddInst.setOpcode(ARM::ADDrr);
1445 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1446 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1447 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1448 printMCInst(&AddInst);
1451 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1452 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1453 /// in the function. The first operand is the ID# for this instruction, the
1454 /// second is the index into the MachineConstantPool that this is, the third
1455 /// is the size in bytes of this constant pool entry.
1456 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1457 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1461 const char *Prefix = MAI->getPrivateGlobalPrefix();
1462 MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
1463 Twine(getFunctionNumber())+
1464 "_"+ Twine(LabelId));
1465 OutStreamer.EmitLabel(Label);
1467 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1468 if (MCPE.isMachineConstantPoolEntry())
1469 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1471 EmitGlobalConstant(MCPE.Val.ConstVal);
1475 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1476 // This is a hack that lowers as a two instruction sequence.
1477 unsigned DstReg = MI->getOperand(0).getReg();
1478 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1480 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1481 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1485 TmpInst.setOpcode(ARM::MOVi);
1486 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1487 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1490 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1491 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1493 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1494 printMCInst(&TmpInst);
1500 TmpInst.setOpcode(ARM::ORRri);
1501 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1502 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1503 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1505 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1506 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1508 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1509 printMCInst(&TmpInst);
1513 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1514 // This is a hack that lowers as a two instruction sequence.
1515 unsigned DstReg = MI->getOperand(0).getReg();
1516 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1520 TmpInst.setOpcode(ARM::MOVi16);
1521 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1522 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1525 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1526 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1528 printMCInst(&TmpInst);
1534 TmpInst.setOpcode(ARM::MOVTi16);
1535 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1536 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1537 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1540 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1541 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1543 printMCInst(&TmpInst);
1551 MCInstLowering.Lower(MI, TmpInst);
1553 printMCInst(&TmpInst);
1556 //===----------------------------------------------------------------------===//
1557 // Target Registry Stuff
1558 //===----------------------------------------------------------------------===//
1560 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1561 unsigned SyntaxVariant,
1562 const MCAsmInfo &MAI,
1564 if (SyntaxVariant == 0)
1565 return new ARMInstPrinter(O, MAI, false);
1569 // Force static initialization.
1570 extern "C" void LLVMInitializeARMAsmPrinter() {
1571 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1572 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1574 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1575 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);