1 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Module.h"
24 #include "llvm/MDNode.h"
25 #include "llvm/CodeGen/AsmPrinter.h"
26 #include "llvm/CodeGen/DwarfWriter.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringExtras.h"
36 #include "llvm/ADT/StringSet.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Mangler.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
44 STATISTIC(EmittedInsts, "Number of machine instrs printed");
47 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
50 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
51 /// make the right decision when printing asm code for different targets.
52 const ARMSubtarget *Subtarget;
54 /// AFI - Keep a pointer to ARMFunctionInfo for the current
58 /// MCP - Keep a pointer to constantpool entries of the current
60 const MachineConstantPool *MCP;
62 /// We name each basic block in a Function with a unique number, so
63 /// that we can consistently refer to them later. This is cleared
64 /// at the beginning of each call to runOnMachineFunction().
66 typedef std::map<const Value *, unsigned> ValueMapTy;
67 ValueMapTy NumberForBB;
69 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
70 /// non-lazy-pointers for indirect access.
71 StringSet<> GVNonLazyPtrs;
73 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
74 /// visibility that require non-lazy-pointers for indirect access.
75 StringSet<> HiddenGVNonLazyPtrs;
77 /// FnStubs - Keeps the set of external function GlobalAddresses that the
78 /// asm printer should generate stubs for.
81 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
84 explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
85 const TargetAsmInfo *T, CodeGenOpt::Level OL,
87 : AsmPrinter(O, TM, T, OL, V), DW(0), AFI(NULL), MCP(NULL),
89 Subtarget = &TM.getSubtarget<ARMSubtarget>();
92 virtual const char *getPassName() const {
93 return "ARM Assembly Printer";
96 void printOperand(const MachineInstr *MI, int OpNum,
97 const char *Modifier = 0);
98 void printSOImmOperand(const MachineInstr *MI, int OpNum);
99 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
100 void printSORegOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
104 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
105 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
108 const char *Modifier = 0);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
116 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
117 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
121 void printT2SOImmOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
127 void printPredicateOperand(const MachineInstr *MI, int OpNum);
128 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
129 void printPCLabel(const MachineInstr *MI, int OpNum);
130 void printRegisterList(const MachineInstr *MI, int OpNum);
131 void printCPInstOperand(const MachineInstr *MI, int OpNum,
132 const char *Modifier);
133 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
135 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
136 unsigned AsmVariant, const char *ExtraCode);
137 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
139 const char *ExtraCode);
141 void printModuleLevelGV(const GlobalVariable* GVar);
142 bool printInstruction(const MachineInstr *MI); // autogenerated.
143 void printMachineInstruction(const MachineInstr *MI);
144 bool runOnMachineFunction(MachineFunction &F);
145 bool doInitialization(Module &M);
146 bool doFinalization(Module &M);
148 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
150 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
151 printDataDirective(MCPV->getType());
153 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
154 GlobalValue *GV = ACPV->getGV();
155 std::string Name = GV ? Mang->getValueName(GV) : TAI->getGlobalPrefix();
157 Name += ACPV->getSymbol();
158 if (ACPV->isNonLazyPointer()) {
159 if (GV->hasHiddenVisibility())
160 HiddenGVNonLazyPtrs.insert(Name);
162 GVNonLazyPtrs.insert(Name);
163 printSuffixedName(Name, "$non_lazy_ptr");
164 } else if (ACPV->isStub()) {
165 FnStubs.insert(Name);
166 printSuffixedName(Name, "$stub");
169 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
170 if (ACPV->getPCAdjustment() != 0) {
171 O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
172 << utostr(ACPV->getLabelId())
173 << "+" << (unsigned)ACPV->getPCAdjustment();
174 if (ACPV->mustAddCurrentAddress())
181 void getAnalysisUsage(AnalysisUsage &AU) const {
182 AsmPrinter::getAnalysisUsage(AU);
183 AU.setPreservesAll();
184 AU.addRequired<MachineModuleInfo>();
185 AU.addRequired<DwarfWriter>();
188 } // end of anonymous namespace
190 #include "ARMGenAsmWriter.inc"
192 /// runOnMachineFunction - This uses the printInstruction()
193 /// method to print assembly for each instruction.
195 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
198 AFI = MF.getInfo<ARMFunctionInfo>();
199 MCP = MF.getConstantPool();
201 SetupMachineFunction(MF);
204 // NOTE: we don't print out constant pools here, they are handled as
208 // Print out labels for the function.
209 const Function *F = MF.getFunction();
210 switch (F->getLinkage()) {
211 default: assert(0 && "Unknown linkage type!");
212 case Function::PrivateLinkage:
213 case Function::InternalLinkage:
214 SwitchToTextSection("\t.text", F);
216 case Function::ExternalLinkage:
217 SwitchToTextSection("\t.text", F);
218 O << "\t.globl\t" << CurrentFnName << "\n";
220 case Function::WeakAnyLinkage:
221 case Function::WeakODRLinkage:
222 case Function::LinkOnceAnyLinkage:
223 case Function::LinkOnceODRLinkage:
224 if (Subtarget->isTargetDarwin()) {
226 ".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
227 O << "\t.globl\t" << CurrentFnName << "\n";
228 O << "\t.weak_definition\t" << CurrentFnName << "\n";
230 O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
235 printVisibility(CurrentFnName, F->getVisibility());
237 if (AFI->isThumbFunction()) {
238 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
239 O << "\t.code\t16\n";
240 O << "\t.thumb_func";
241 if (Subtarget->isTargetDarwin())
242 O << "\t" << CurrentFnName;
246 EmitAlignment(MF.getAlignment(), F);
249 O << CurrentFnName << ":\n";
250 // Emit pre-function debug information.
251 DW->BeginFunction(&MF);
253 if (Subtarget->isTargetDarwin()) {
254 // If the function is empty, then we need to emit *something*. Otherwise,
255 // the function's label might be associated with something that it wasn't
256 // meant to be associated with. We emit a noop in this situation.
257 MachineFunction::iterator I = MF.begin();
259 if (++I == MF.end() && MF.front().empty())
263 // Print out code for the function.
264 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
266 // Print a label for the basic block.
267 if (I != MF.begin()) {
268 printBasicBlockLabel(I, true, true, VerboseAsm);
271 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
273 // Print the assembly for the instruction.
274 printMachineInstruction(II);
278 if (TAI->hasDotTypeDotSizeDirective())
279 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
281 // Emit post-function debug information.
282 DW->EndFunction(&MF);
289 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
290 const char *Modifier) {
291 const MachineOperand &MO = MI->getOperand(OpNum);
292 switch (MO.getType()) {
293 case MachineOperand::MO_Register: {
294 unsigned Reg = MO.getReg();
295 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
296 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
297 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
298 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
300 << TRI->getAsmName(DRegLo) << "-" << TRI->getAsmName(DRegHi)
303 O << TRI->getAsmName(Reg);
306 assert(0 && "not implemented");
309 case MachineOperand::MO_Immediate: {
310 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
316 case MachineOperand::MO_MachineBasicBlock:
317 printBasicBlockLabel(MO.getMBB());
319 case MachineOperand::MO_GlobalAddress: {
320 bool isCallOp = Modifier && !strcmp(Modifier, "call");
321 GlobalValue *GV = MO.getGlobal();
322 std::string Name = Mang->getValueName(GV);
323 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
324 GV->hasLinkOnceLinkage());
325 if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
326 TM.getRelocationModel() != Reloc::Static) {
327 printSuffixedName(Name, "$stub");
328 FnStubs.insert(Name);
332 printOffset(MO.getOffset());
334 if (isCallOp && Subtarget->isTargetELF() &&
335 TM.getRelocationModel() == Reloc::PIC_)
339 case MachineOperand::MO_ExternalSymbol: {
340 bool isCallOp = Modifier && !strcmp(Modifier, "call");
341 std::string Name(TAI->getGlobalPrefix());
342 Name += MO.getSymbolName();
343 if (isCallOp && Subtarget->isTargetDarwin() &&
344 TM.getRelocationModel() != Reloc::Static) {
345 printSuffixedName(Name, "$stub");
346 FnStubs.insert(Name);
349 if (isCallOp && Subtarget->isTargetELF() &&
350 TM.getRelocationModel() == Reloc::PIC_)
354 case MachineOperand::MO_ConstantPoolIndex:
355 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
356 << '_' << MO.getIndex();
358 case MachineOperand::MO_JumpTableIndex:
359 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
360 << '_' << MO.getIndex();
363 O << "<unknown operand type>"; abort (); break;
367 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
368 const TargetAsmInfo *TAI) {
369 assert(V < (1 << 12) && "Not a valid so_imm value!");
370 unsigned Imm = ARM_AM::getSOImmValImm(V);
371 unsigned Rot = ARM_AM::getSOImmValRot(V);
373 // Print low-level immediate formation info, per
374 // A5.1.3: "Data-processing operands - Immediate".
376 O << "#" << Imm << ", " << Rot;
377 // Pretty printed version.
379 O << ' ' << TAI->getCommentString()
380 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
386 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
387 /// immediate in bits 0-7.
388 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
389 const MachineOperand &MO = MI->getOperand(OpNum);
390 assert(MO.isImm() && "Not a valid so_imm value!");
391 printSOImm(O, MO.getImm(), VerboseAsm, TAI);
394 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
395 /// followed by an 'orr' to materialize.
396 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
397 const MachineOperand &MO = MI->getOperand(OpNum);
398 assert(MO.isImm() && "Not a valid so_imm value!");
399 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
400 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
401 printSOImm(O, ARM_AM::getSOImmVal(V1), VerboseAsm, TAI);
403 printPredicateOperand(MI, 2);
409 printSOImm(O, ARM_AM::getSOImmVal(V2), VerboseAsm, TAI);
412 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
413 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
415 // REG REG 0,SH_OPC - e.g. R5, ROR R3
416 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
417 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
418 const MachineOperand &MO1 = MI->getOperand(Op);
419 const MachineOperand &MO2 = MI->getOperand(Op+1);
420 const MachineOperand &MO3 = MI->getOperand(Op+2);
422 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
423 O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
425 // Print the shift opc.
427 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
431 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
432 O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
433 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
435 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
439 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
440 const MachineOperand &MO1 = MI->getOperand(Op);
441 const MachineOperand &MO2 = MI->getOperand(Op+1);
442 const MachineOperand &MO3 = MI->getOperand(Op+2);
444 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
445 printOperand(MI, Op);
449 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
452 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
454 << (char)ARM_AM::getAM2Op(MO3.getImm())
455 << ARM_AM::getAM2Offset(MO3.getImm());
461 << (char)ARM_AM::getAM2Op(MO3.getImm())
462 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
464 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
466 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
471 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
472 const MachineOperand &MO1 = MI->getOperand(Op);
473 const MachineOperand &MO2 = MI->getOperand(Op+1);
476 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
477 assert(ImmOffs && "Malformed indexed load / store!");
479 << (char)ARM_AM::getAM2Op(MO2.getImm())
484 O << (char)ARM_AM::getAM2Op(MO2.getImm())
485 << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
487 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
489 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
493 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
494 const MachineOperand &MO1 = MI->getOperand(Op);
495 const MachineOperand &MO2 = MI->getOperand(Op+1);
496 const MachineOperand &MO3 = MI->getOperand(Op+2);
498 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
499 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
503 << (char)ARM_AM::getAM3Op(MO3.getImm())
504 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
509 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
511 << (char)ARM_AM::getAM3Op(MO3.getImm())
516 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
517 const MachineOperand &MO1 = MI->getOperand(Op);
518 const MachineOperand &MO2 = MI->getOperand(Op+1);
521 O << (char)ARM_AM::getAM3Op(MO2.getImm())
522 << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
526 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
527 assert(ImmOffs && "Malformed indexed load / store!");
529 << (char)ARM_AM::getAM3Op(MO2.getImm())
533 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
534 const char *Modifier) {
535 const MachineOperand &MO1 = MI->getOperand(Op);
536 const MachineOperand &MO2 = MI->getOperand(Op+1);
537 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
538 if (Modifier && strcmp(Modifier, "submode") == 0) {
539 if (MO1.getReg() == ARM::SP) {
540 bool isLDM = (MI->getOpcode() == ARM::LDM ||
541 MI->getOpcode() == ARM::LDM_RET);
542 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
544 O << ARM_AM::getAMSubModeStr(Mode);
546 printOperand(MI, Op);
547 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
552 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
553 const char *Modifier) {
554 const MachineOperand &MO1 = MI->getOperand(Op);
555 const MachineOperand &MO2 = MI->getOperand(Op+1);
557 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
558 printOperand(MI, Op);
562 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
564 if (Modifier && strcmp(Modifier, "submode") == 0) {
565 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
566 if (MO1.getReg() == ARM::SP) {
567 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
568 MI->getOpcode() == ARM::FLDMS);
569 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
571 O << ARM_AM::getAMSubModeStr(Mode);
573 } else if (Modifier && strcmp(Modifier, "base") == 0) {
574 // Used for FSTM{D|S} and LSTM{D|S} operations.
575 O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
576 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
581 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
583 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
585 << (char)ARM_AM::getAM5Op(MO2.getImm())
591 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
592 const char *Modifier) {
593 if (Modifier && strcmp(Modifier, "label") == 0) {
594 printPCLabel(MI, Op+1);
598 const MachineOperand &MO1 = MI->getOperand(Op);
599 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
600 O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
604 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
605 const MachineOperand &MO = MI->getOperand(Op);
606 uint32_t v = ~MO.getImm();
607 int32_t lsb = CountTrailingZeros_32(v);
608 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
609 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
610 O << "#" << lsb << ", #" << width;
613 //===--------------------------------------------------------------------===//
616 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
617 const MachineOperand &MO1 = MI->getOperand(Op);
618 const MachineOperand &MO2 = MI->getOperand(Op+1);
619 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
620 O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
624 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
626 const MachineOperand &MO1 = MI->getOperand(Op);
627 const MachineOperand &MO2 = MI->getOperand(Op+1);
628 const MachineOperand &MO3 = MI->getOperand(Op+2);
630 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
631 printOperand(MI, Op);
635 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
637 O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
638 else if (unsigned ImmOffs = MO2.getImm()) {
639 O << ", #" << ImmOffs;
647 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
648 printThumbAddrModeRI5Operand(MI, Op, 1);
651 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
652 printThumbAddrModeRI5Operand(MI, Op, 2);
655 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
656 printThumbAddrModeRI5Operand(MI, Op, 4);
659 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
660 const MachineOperand &MO1 = MI->getOperand(Op);
661 const MachineOperand &MO2 = MI->getOperand(Op+1);
662 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
663 if (unsigned ImmOffs = MO2.getImm())
664 O << ", #" << ImmOffs << " * 4";
668 //===--------------------------------------------------------------------===//
670 /// printT2SOImmOperand - T2SOImm is:
671 /// 1. a 4-bit splat control value and 8 bit immediate value
672 /// 2. a 5-bit rotate amount and a non-zero 8-bit immediate value
673 /// represented by a normalizedin 7-bit value (msb is always 1)
674 void ARMAsmPrinter::printT2SOImmOperand(const MachineInstr *MI, int OpNum) {
675 const MachineOperand &MO = MI->getOperand(OpNum);
676 assert(MO.isImm() && "Not a valid so_imm value!");
678 unsigned Imm = ARM_AM::getT2SOImmValDecode(MO.getImm());
679 // Always print the immediate directly, as the "rotate" form
680 // is deprecated in some contexts.
684 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
685 // register with shift forms.
687 // REG IMM, SH_OPC - e.g. R5, LSL #3
688 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
689 const MachineOperand &MO1 = MI->getOperand(OpNum);
690 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
692 unsigned Reg = MO1.getReg();
693 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
694 O << TM.getRegisterInfo()->getAsmName(Reg);
696 // Print the shift opc.
698 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
701 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
702 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
705 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
707 const MachineOperand &MO1 = MI->getOperand(OpNum);
708 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
710 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
712 unsigned OffImm = MO2.getImm();
713 if (OffImm) // Don't print +0.
714 O << ", #+" << OffImm;
718 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
720 const MachineOperand &MO1 = MI->getOperand(OpNum);
721 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
723 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
725 int32_t OffImm = (int32_t)MO2.getImm();
728 O << ", #-" << -OffImm;
730 O << ", #+" << OffImm;
734 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
736 const MachineOperand &MO1 = MI->getOperand(OpNum);
737 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
738 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
740 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
744 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
746 unsigned ShAmt = MO3.getImm();
748 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
749 O << ", lsl #" << ShAmt;
756 //===--------------------------------------------------------------------===//
758 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
759 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
761 O << ARMCondCodeToString(CC);
764 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
765 unsigned Reg = MI->getOperand(OpNum).getReg();
767 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
772 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
773 int Id = (int)MI->getOperand(OpNum).getImm();
774 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
777 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
779 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
781 if (i != e-1) O << ", ";
786 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
787 const char *Modifier) {
788 assert(Modifier && "This operand only works with a modifier!");
789 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
791 if (!strcmp(Modifier, "label")) {
792 unsigned ID = MI->getOperand(OpNum).getImm();
793 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
794 << '_' << ID << ":\n";
796 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
797 unsigned CPI = MI->getOperand(OpNum).getIndex();
799 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
801 if (MCPE.isMachineConstantPoolEntry()) {
802 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
804 EmitGlobalConstant(MCPE.Val.ConstVal);
809 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
810 const MachineOperand &MO1 = MI->getOperand(OpNum);
811 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
812 unsigned JTI = MO1.getIndex();
813 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
814 << '_' << JTI << '_' << MO2.getImm() << ":\n";
816 const char *JTEntryDirective = TAI->getJumpTableDirective();
817 if (!JTEntryDirective)
818 JTEntryDirective = TAI->getData32bitsDirective();
820 const MachineFunction *MF = MI->getParent()->getParent();
821 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
822 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
823 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
824 bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
825 std::set<MachineBasicBlock*> JTSets;
826 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
827 MachineBasicBlock *MBB = JTBBs[i];
828 if (UseSet && JTSets.insert(MBB).second)
829 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
831 O << JTEntryDirective << ' ';
833 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
834 << '_' << JTI << '_' << MO2.getImm()
835 << "_set_" << MBB->getNumber();
836 else if (TM.getRelocationModel() == Reloc::PIC_) {
837 printBasicBlockLabel(MBB, false, false, false);
838 // If the arch uses custom Jump Table directives, don't calc relative to JT
839 if (!TAI->getJumpTableDirective())
840 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
841 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
843 printBasicBlockLabel(MBB, false, false, false);
850 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
851 unsigned AsmVariant, const char *ExtraCode){
852 // Does this asm operand have a single letter operand modifier?
853 if (ExtraCode && ExtraCode[0]) {
854 if (ExtraCode[1] != 0) return true; // Unknown modifier.
856 switch (ExtraCode[0]) {
857 default: return true; // Unknown modifier.
858 case 'a': // Don't print "#" before a global var name or constant.
859 case 'c': // Don't print "$" before a global var name or constant.
860 printOperand(MI, OpNum, "no_hash");
862 case 'P': // Print a VFP double precision register.
863 printOperand(MI, OpNum);
866 if (TM.getTargetData()->isLittleEndian())
870 if (TM.getTargetData()->isBigEndian())
873 case 'H': // Write second word of DI / DF reference.
874 // Verify that this operand has two consecutive registers.
875 if (!MI->getOperand(OpNum).isReg() ||
876 OpNum+1 == MI->getNumOperands() ||
877 !MI->getOperand(OpNum+1).isReg())
879 ++OpNum; // Return the high-part.
883 printOperand(MI, OpNum);
887 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
888 unsigned OpNum, unsigned AsmVariant,
889 const char *ExtraCode) {
890 if (ExtraCode && ExtraCode[0])
891 return true; // Unknown modifier.
892 printAddrMode2Operand(MI, OpNum);
896 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
899 int Opc = MI->getOpcode();
901 case ARM::CONSTPOOL_ENTRY:
902 if (!InCPMode && AFI->isThumbFunction()) {
908 if (InCPMode && AFI->isThumbFunction())
912 // Call the autogenerated instruction printer routines.
913 printInstruction(MI);
916 bool ARMAsmPrinter::doInitialization(Module &M) {
918 bool Result = AsmPrinter::doInitialization(M);
919 DW = getAnalysisIfAvailable<DwarfWriter>();
921 // Thumb-2 instructions are supported only in unified assembler syntax mode.
922 if (Subtarget->hasThumb2())
923 O << "\t.syntax unified\n";
925 // Emit ARM Build Attributes
926 if (Subtarget->isTargetELF()) {
928 std::string CPUString = Subtarget->getCPUString();
929 if (CPUString != "generic")
930 O << "\t.cpu " << CPUString << '\n';
932 // FIXME: Emit FPU type
933 if (Subtarget->hasVFP2())
934 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
936 // Signal various FP modes.
938 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
939 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
941 if (FiniteOnlyFPMath())
942 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
944 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
946 // 8-bytes alignment stuff.
947 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
948 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
950 // FIXME: Should we signal R9 usage?
956 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
957 /// Don't print things like \\n or \\0.
958 static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) {
959 for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
965 void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
966 const TargetData *TD = TM.getTargetData();
968 if (!GVar->hasInitializer()) // External global require no code
971 // Check to see if this is a special global used by LLVM, if so, emit it.
973 if (EmitSpecialLLVMGlobal(GVar)) {
974 if (Subtarget->isTargetDarwin() &&
975 TM.getRelocationModel() == Reloc::Static) {
976 if (GVar->getName() == "llvm.global_ctors")
977 O << ".reference .constructors_used\n";
978 else if (GVar->getName() == "llvm.global_dtors")
979 O << ".reference .destructors_used\n";
984 std::string name = Mang->getValueName(GVar);
985 Constant *C = GVar->getInitializer();
986 if (isa<MDNode>(C) || isa<MDString>(C))
988 const Type *Type = C->getType();
989 unsigned Size = TD->getTypeAllocSize(Type);
990 unsigned Align = TD->getPreferredAlignmentLog(GVar);
991 bool isDarwin = Subtarget->isTargetDarwin();
993 printVisibility(name, GVar->getVisibility());
995 if (Subtarget->isTargetELF())
996 O << "\t.type " << name << ",%object\n";
998 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1000 TAI->SectionKindForGlobal(GVar) == SectionKind::RODataMergeStr)) {
1001 // FIXME: This seems to be pretty darwin-specific
1003 if (GVar->hasExternalLinkage()) {
1004 SwitchToSection(TAI->SectionForGlobal(GVar));
1005 if (const char *Directive = TAI->getZeroFillDirective()) {
1006 O << "\t.globl\t" << name << "\n";
1007 O << Directive << "__DATA, __common, " << name << ", "
1008 << Size << ", " << Align << "\n";
1013 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1014 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1017 if (GVar->hasLocalLinkage()) {
1018 O << TAI->getLCOMMDirective() << name << "," << Size
1020 } else if (GVar->hasCommonLinkage()) {
1021 O << TAI->getCOMMDirective() << name << "," << Size
1024 SwitchToSection(TAI->SectionForGlobal(GVar));
1025 O << "\t.globl " << name << '\n'
1026 << TAI->getWeakDefDirective() << name << '\n';
1027 EmitAlignment(Align, GVar);
1030 O << "\t\t\t\t" << TAI->getCommentString() << ' ';
1031 PrintUnmangledNameSafely(GVar, O);
1034 EmitGlobalConstant(C);
1037 } else if (TAI->getLCOMMDirective() != NULL) {
1038 if (GVar->hasLocalLinkage()) {
1039 O << TAI->getLCOMMDirective() << name << "," << Size;
1041 O << TAI->getCOMMDirective() << name << "," << Size;
1042 if (TAI->getCOMMDirectiveTakesAlignment())
1043 O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1046 SwitchToSection(TAI->SectionForGlobal(GVar));
1047 if (GVar->hasLocalLinkage())
1048 O << "\t.local\t" << name << "\n";
1049 O << TAI->getCOMMDirective() << name << "," << Size;
1050 if (TAI->getCOMMDirectiveTakesAlignment())
1051 O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1054 O << "\t\t" << TAI->getCommentString() << " ";
1055 PrintUnmangledNameSafely(GVar, O);
1062 SwitchToSection(TAI->SectionForGlobal(GVar));
1063 switch (GVar->getLinkage()) {
1064 case GlobalValue::CommonLinkage:
1065 case GlobalValue::LinkOnceAnyLinkage:
1066 case GlobalValue::LinkOnceODRLinkage:
1067 case GlobalValue::WeakAnyLinkage:
1068 case GlobalValue::WeakODRLinkage:
1070 O << "\t.globl " << name << "\n"
1071 << "\t.weak_definition " << name << "\n";
1073 O << "\t.weak " << name << "\n";
1076 case GlobalValue::AppendingLinkage:
1077 // FIXME: appending linkage variables should go into a section of
1078 // their name or something. For now, just emit them as external.
1079 case GlobalValue::ExternalLinkage:
1080 O << "\t.globl " << name << "\n";
1082 case GlobalValue::PrivateLinkage:
1083 case GlobalValue::InternalLinkage:
1086 assert(0 && "Unknown linkage type!");
1090 EmitAlignment(Align, GVar);
1093 O << "\t\t\t\t" << TAI->getCommentString() << " ";
1094 PrintUnmangledNameSafely(GVar, O);
1097 if (TAI->hasDotTypeDotSizeDirective())
1098 O << "\t.size " << name << ", " << Size << "\n";
1100 EmitGlobalConstant(C);
1105 bool ARMAsmPrinter::doFinalization(Module &M) {
1106 for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
1108 printModuleLevelGV(I);
1110 if (Subtarget->isTargetDarwin()) {
1111 SwitchToDataSection("");
1113 // Output stubs for dynamically-linked functions
1114 for (StringSet<>::iterator i = FnStubs.begin(), e = FnStubs.end();
1116 if (TM.getRelocationModel() == Reloc::PIC_)
1117 SwitchToTextSection(".section __TEXT,__picsymbolstub4,symbol_stubs,"
1120 SwitchToTextSection(".section __TEXT,__symbol_stub4,symbol_stubs,"
1124 O << "\t.code\t32\n";
1126 const char *p = i->getKeyData();
1127 printSuffixedName(p, "$stub");
1129 O << "\t.indirect_symbol " << p << "\n";
1131 printSuffixedName(p, "$slp");
1133 if (TM.getRelocationModel() == Reloc::PIC_) {
1134 printSuffixedName(p, "$scv");
1136 O << "\tadd ip, pc, ip\n";
1138 O << "\tldr pc, [ip, #0]\n";
1139 printSuffixedName(p, "$slp");
1142 printSuffixedName(p, "$lazy_ptr");
1143 if (TM.getRelocationModel() == Reloc::PIC_) {
1145 printSuffixedName(p, "$scv");
1149 SwitchToDataSection(".lazy_symbol_pointer", 0);
1150 printSuffixedName(p, "$lazy_ptr");
1152 O << "\t.indirect_symbol " << p << "\n";
1153 O << "\t.long\tdyld_stub_binding_helper\n";
1157 // Output non-lazy-pointers for external and common global variables.
1158 if (!GVNonLazyPtrs.empty()) {
1159 SwitchToDataSection("\t.non_lazy_symbol_pointer", 0);
1160 for (StringSet<>::iterator i = GVNonLazyPtrs.begin(),
1161 e = GVNonLazyPtrs.end(); i != e; ++i) {
1162 const char *p = i->getKeyData();
1163 printSuffixedName(p, "$non_lazy_ptr");
1165 O << "\t.indirect_symbol " << p << "\n";
1166 O << "\t.long\t0\n";
1170 if (!HiddenGVNonLazyPtrs.empty()) {
1171 SwitchToSection(TAI->getDataSection());
1172 for (StringSet<>::iterator i = HiddenGVNonLazyPtrs.begin(),
1173 e = HiddenGVNonLazyPtrs.end(); i != e; ++i) {
1174 const char *p = i->getKeyData();
1176 printSuffixedName(p, "$non_lazy_ptr");
1178 O << "\t.long " << p << "\n";
1183 // Funny Darwin hack: This flag tells the linker that no global symbols
1184 // contain code that falls through to other global symbols (e.g. the obvious
1185 // implementation of multiple entry points). If this doesn't occur, the
1186 // linker can safely perform dead code stripping. Since LLVM never
1187 // generates code that does this, it is always safe to set.
1188 O << "\t.subsections_via_symbols\n";
1191 return AsmPrinter::doFinalization(M);
1194 /// createARMCodePrinterPass - Returns a pass that prints the ARM
1195 /// assembly code for a MachineFunction to the given output stream,
1196 /// using the given target machine description. This should work
1197 /// regardless of whether the function is in SSA form.
1199 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
1200 ARMBaseTargetMachine &tm,
1201 CodeGenOpt::Level OptLevel,
1203 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
1207 static struct Register {
1209 ARMBaseTargetMachine::registerAsmPrinter(createARMCodePrinterPass);
1214 // Force static initialization.
1215 extern "C" void LLVMInitializeARMAsmPrinter() { }