1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
171 const MachineBasicBlock *MBB) const;
172 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
174 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
176 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
177 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
178 case 1: O << MAI->getData8bitsDirective(0); break;
179 case 2: O << MAI->getData16bitsDirective(0); break;
180 case 4: O << MAI->getData32bitsDirective(0); break;
181 default: assert(0 && "Unknown CPV size");
184 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
185 SmallString<128> TmpNameStr;
187 if (ACPV->isLSDA()) {
188 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
189 "_LSDA_" << getFunctionNumber();
190 O << TmpNameStr.str();
191 } else if (ACPV->isBlockAddress()) {
192 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
193 } else if (ACPV->isGlobalValue()) {
194 GlobalValue *GV = ACPV->getGV();
195 bool isIndirect = Subtarget->isTargetDarwin() &&
196 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
198 O << *GetGlobalValueSymbol(GV);
200 // FIXME: Remove this when Darwin transition to @GOT like syntax.
201 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
204 MachineModuleInfoMachO &MMIMachO =
205 MMI->getObjFileInfo<MachineModuleInfoMachO>();
206 const MCSymbol *&StubSym =
207 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
208 MMIMachO.getGVStubEntry(Sym);
210 StubSym = GetGlobalValueSymbol(GV);
213 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
214 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
217 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
218 if (ACPV->getPCAdjustment() != 0) {
219 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
220 << getFunctionNumber() << "_" << ACPV->getLabelId()
221 << "+" << (unsigned)ACPV->getPCAdjustment();
222 if (ACPV->mustAddCurrentAddress())
229 void getAnalysisUsage(AnalysisUsage &AU) const {
230 AsmPrinter::getAnalysisUsage(AU);
231 AU.setPreservesAll();
232 AU.addRequired<MachineModuleInfo>();
233 AU.addRequired<DwarfWriter>();
236 } // end of anonymous namespace
238 #include "ARMGenAsmWriter.inc"
240 /// runOnMachineFunction - This uses the printInstruction()
241 /// method to print assembly for each instruction.
243 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
244 AFI = MF.getInfo<ARMFunctionInfo>();
245 MCP = MF.getConstantPool();
247 SetupMachineFunction(MF);
250 // NOTE: we don't print out constant pools here, they are handled as
255 // Print out labels for the function.
256 const Function *F = MF.getFunction();
257 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
259 switch (F->getLinkage()) {
260 default: llvm_unreachable("Unknown linkage type!");
261 case Function::PrivateLinkage:
262 case Function::InternalLinkage:
264 case Function::ExternalLinkage:
265 O << "\t.globl\t" << *CurrentFnSym << "\n";
267 case Function::LinkerPrivateLinkage:
268 case Function::WeakAnyLinkage:
269 case Function::WeakODRLinkage:
270 case Function::LinkOnceAnyLinkage:
271 case Function::LinkOnceODRLinkage:
272 if (Subtarget->isTargetDarwin()) {
273 O << "\t.globl\t" << *CurrentFnSym << "\n";
274 O << "\t.weak_definition\t" << *CurrentFnSym << "\n";
276 O << MAI->getWeakRefDirective() << *CurrentFnSym << "\n";
281 printVisibility(CurrentFnSym, F->getVisibility());
283 EmitAlignment(1 << MF.getAlignment(), F);
284 if (AFI->isThumbFunction()) {
285 O << "\t.code\t16\n";
286 O << "\t.thumb_func";
287 if (Subtarget->isTargetDarwin())
288 O << "\t" << *CurrentFnSym;
292 O << *CurrentFnSym << ":\n";
293 // Emit pre-function debug information.
294 DW->BeginFunction(&MF);
296 if (Subtarget->isTargetDarwin()) {
297 // If the function is empty, then we need to emit *something*. Otherwise,
298 // the function's label might be associated with something that it wasn't
299 // meant to be associated with. We emit a noop in this situation.
300 MachineFunction::iterator I = MF.begin();
302 if (++I == MF.end() && MF.front().empty())
306 // Print out code for the function.
307 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
309 // Print a label for the basic block.
311 EmitBasicBlockStart(I);
313 // Print the assembly for the instruction.
314 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
316 printMachineInstruction(II);
319 if (MAI->hasDotTypeDotSizeDirective())
320 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
322 // Emit post-function debug information.
323 DW->EndFunction(&MF);
328 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
329 const char *Modifier) {
330 const MachineOperand &MO = MI->getOperand(OpNum);
331 unsigned TF = MO.getTargetFlags();
333 switch (MO.getType()) {
335 assert(0 && "<unknown operand type>");
336 case MachineOperand::MO_Register: {
337 unsigned Reg = MO.getReg();
338 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
339 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
340 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
341 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
343 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
345 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
346 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
347 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
348 &ARM::DPR_VFP2RegClass);
349 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
351 assert(!MO.getSubReg() && "Subregs should be eliminated!");
352 O << getRegisterName(Reg);
356 case MachineOperand::MO_Immediate: {
357 int64_t Imm = MO.getImm();
359 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
360 (TF & ARMII::MO_LO16))
362 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
363 (TF & ARMII::MO_HI16))
368 case MachineOperand::MO_MachineBasicBlock:
369 O << *MO.getMBB()->getSymbol(OutContext);
371 case MachineOperand::MO_GlobalAddress: {
372 bool isCallOp = Modifier && !strcmp(Modifier, "call");
373 GlobalValue *GV = MO.getGlobal();
375 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
376 (TF & ARMII::MO_LO16))
378 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
379 (TF & ARMII::MO_HI16))
381 O << *GetGlobalValueSymbol(GV);
383 printOffset(MO.getOffset());
385 if (isCallOp && Subtarget->isTargetELF() &&
386 TM.getRelocationModel() == Reloc::PIC_)
390 case MachineOperand::MO_ExternalSymbol: {
391 bool isCallOp = Modifier && !strcmp(Modifier, "call");
392 O << *GetExternalSymbolSymbol(MO.getSymbolName());
394 if (isCallOp && Subtarget->isTargetELF() &&
395 TM.getRelocationModel() == Reloc::PIC_)
399 case MachineOperand::MO_ConstantPoolIndex:
400 O << *GetCPISymbol(MO.getIndex());
402 case MachineOperand::MO_JumpTableIndex:
403 O << *GetJTISymbol(MO.getIndex());
408 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
409 const MCAsmInfo *MAI) {
410 // Break it up into two parts that make up a shifter immediate.
411 V = ARM_AM::getSOImmVal(V);
412 assert(V != -1 && "Not a valid so_imm value!");
414 unsigned Imm = ARM_AM::getSOImmValImm(V);
415 unsigned Rot = ARM_AM::getSOImmValRot(V);
417 // Print low-level immediate formation info, per
418 // A5.1.3: "Data-processing operands - Immediate".
420 O << "#" << Imm << ", " << Rot;
421 // Pretty printed version.
423 O.PadToColumn(MAI->getCommentColumn());
424 O << MAI->getCommentString() << ' ';
425 O << (int)ARM_AM::rotr32(Imm, Rot);
432 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
433 /// immediate in bits 0-7.
434 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
435 const MachineOperand &MO = MI->getOperand(OpNum);
436 assert(MO.isImm() && "Not a valid so_imm value!");
437 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
440 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
441 /// followed by an 'orr' to materialize.
442 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
443 const MachineOperand &MO = MI->getOperand(OpNum);
444 assert(MO.isImm() && "Not a valid so_imm value!");
445 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
446 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
447 printSOImm(O, V1, VerboseAsm, MAI);
449 printPredicateOperand(MI, 2);
455 printSOImm(O, V2, VerboseAsm, MAI);
458 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
459 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
461 // REG REG 0,SH_OPC - e.g. R5, ROR R3
462 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
463 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
464 const MachineOperand &MO1 = MI->getOperand(Op);
465 const MachineOperand &MO2 = MI->getOperand(Op+1);
466 const MachineOperand &MO3 = MI->getOperand(Op+2);
468 O << getRegisterName(MO1.getReg());
470 // Print the shift opc.
472 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
476 O << getRegisterName(MO2.getReg());
477 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
479 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
483 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
484 const MachineOperand &MO1 = MI->getOperand(Op);
485 const MachineOperand &MO2 = MI->getOperand(Op+1);
486 const MachineOperand &MO3 = MI->getOperand(Op+2);
488 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
489 printOperand(MI, Op);
493 O << "[" << getRegisterName(MO1.getReg());
496 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
498 << (char)ARM_AM::getAM2Op(MO3.getImm())
499 << ARM_AM::getAM2Offset(MO3.getImm());
505 << (char)ARM_AM::getAM2Op(MO3.getImm())
506 << getRegisterName(MO2.getReg());
508 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
510 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
515 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
516 const MachineOperand &MO1 = MI->getOperand(Op);
517 const MachineOperand &MO2 = MI->getOperand(Op+1);
520 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
521 assert(ImmOffs && "Malformed indexed load / store!");
523 << (char)ARM_AM::getAM2Op(MO2.getImm())
528 O << (char)ARM_AM::getAM2Op(MO2.getImm())
529 << getRegisterName(MO1.getReg());
531 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
533 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
537 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
538 const MachineOperand &MO1 = MI->getOperand(Op);
539 const MachineOperand &MO2 = MI->getOperand(Op+1);
540 const MachineOperand &MO3 = MI->getOperand(Op+2);
542 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
543 O << "[" << getRegisterName(MO1.getReg());
547 << (char)ARM_AM::getAM3Op(MO3.getImm())
548 << getRegisterName(MO2.getReg())
553 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
555 << (char)ARM_AM::getAM3Op(MO3.getImm())
560 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
561 const MachineOperand &MO1 = MI->getOperand(Op);
562 const MachineOperand &MO2 = MI->getOperand(Op+1);
565 O << (char)ARM_AM::getAM3Op(MO2.getImm())
566 << getRegisterName(MO1.getReg());
570 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
571 assert(ImmOffs && "Malformed indexed load / store!");
573 << (char)ARM_AM::getAM3Op(MO2.getImm())
577 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
578 const char *Modifier) {
579 const MachineOperand &MO1 = MI->getOperand(Op);
580 const MachineOperand &MO2 = MI->getOperand(Op+1);
581 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
582 if (Modifier && strcmp(Modifier, "submode") == 0) {
583 if (MO1.getReg() == ARM::SP) {
585 bool isLDM = (MI->getOpcode() == ARM::LDM ||
586 MI->getOpcode() == ARM::LDM_RET ||
587 MI->getOpcode() == ARM::t2LDM ||
588 MI->getOpcode() == ARM::t2LDM_RET);
589 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
591 O << ARM_AM::getAMSubModeStr(Mode);
592 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
593 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
594 if (Mode == ARM_AM::ia)
597 printOperand(MI, Op);
598 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
603 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
604 const char *Modifier) {
605 const MachineOperand &MO1 = MI->getOperand(Op);
606 const MachineOperand &MO2 = MI->getOperand(Op+1);
608 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
609 printOperand(MI, Op);
613 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
615 if (Modifier && strcmp(Modifier, "submode") == 0) {
616 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
617 O << ARM_AM::getAMSubModeStr(Mode);
619 } else if (Modifier && strcmp(Modifier, "base") == 0) {
620 // Used for FSTM{D|S} and LSTM{D|S} operations.
621 O << getRegisterName(MO1.getReg());
622 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
627 O << "[" << getRegisterName(MO1.getReg());
629 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
631 << (char)ARM_AM::getAM5Op(MO2.getImm())
637 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
638 const MachineOperand &MO1 = MI->getOperand(Op);
639 const MachineOperand &MO2 = MI->getOperand(Op+1);
640 const MachineOperand &MO3 = MI->getOperand(Op+2);
641 const MachineOperand &MO4 = MI->getOperand(Op+3);
643 O << "[" << getRegisterName(MO1.getReg());
645 // FIXME: Both darwin as and GNU as violate ARM docs here.
646 O << ", :" << MO4.getImm();
650 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
651 if (MO2.getReg() == 0)
654 O << ", " << getRegisterName(MO2.getReg());
658 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
659 const char *Modifier) {
660 if (Modifier && strcmp(Modifier, "label") == 0) {
661 printPCLabel(MI, Op+1);
665 const MachineOperand &MO1 = MI->getOperand(Op);
666 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
667 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
671 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
672 const MachineOperand &MO = MI->getOperand(Op);
673 uint32_t v = ~MO.getImm();
674 int32_t lsb = CountTrailingZeros_32(v);
675 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
676 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
677 O << "#" << lsb << ", #" << width;
680 //===--------------------------------------------------------------------===//
682 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
683 O << "#" << MI->getOperand(Op).getImm() * 4;
687 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
688 // (3 - the number of trailing zeros) is the number of then / else.
689 unsigned Mask = MI->getOperand(Op).getImm();
690 unsigned NumTZ = CountTrailingZeros_32(Mask);
691 assert(NumTZ <= 3 && "Invalid IT mask!");
692 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
693 bool T = (Mask & (1 << Pos)) == 0;
702 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
703 const MachineOperand &MO1 = MI->getOperand(Op);
704 const MachineOperand &MO2 = MI->getOperand(Op+1);
705 O << "[" << getRegisterName(MO1.getReg());
706 O << ", " << getRegisterName(MO2.getReg()) << "]";
710 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
712 const MachineOperand &MO1 = MI->getOperand(Op);
713 const MachineOperand &MO2 = MI->getOperand(Op+1);
714 const MachineOperand &MO3 = MI->getOperand(Op+2);
716 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
717 printOperand(MI, Op);
721 O << "[" << getRegisterName(MO1.getReg());
723 O << ", " << getRegisterName(MO3.getReg());
724 else if (unsigned ImmOffs = MO2.getImm())
725 O << ", #+" << ImmOffs * Scale;
730 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
731 printThumbAddrModeRI5Operand(MI, Op, 1);
734 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
735 printThumbAddrModeRI5Operand(MI, Op, 2);
738 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
739 printThumbAddrModeRI5Operand(MI, Op, 4);
742 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
743 const MachineOperand &MO1 = MI->getOperand(Op);
744 const MachineOperand &MO2 = MI->getOperand(Op+1);
745 O << "[" << getRegisterName(MO1.getReg());
746 if (unsigned ImmOffs = MO2.getImm())
747 O << ", #+" << ImmOffs*4;
751 //===--------------------------------------------------------------------===//
753 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
754 // register with shift forms.
756 // REG IMM, SH_OPC - e.g. R5, LSL #3
757 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
758 const MachineOperand &MO1 = MI->getOperand(OpNum);
759 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
761 unsigned Reg = MO1.getReg();
762 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
763 O << getRegisterName(Reg);
765 // Print the shift opc.
767 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
770 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
771 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
774 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
776 const MachineOperand &MO1 = MI->getOperand(OpNum);
777 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
779 O << "[" << getRegisterName(MO1.getReg());
781 unsigned OffImm = MO2.getImm();
782 if (OffImm) // Don't print +0.
783 O << ", #+" << OffImm;
787 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
789 const MachineOperand &MO1 = MI->getOperand(OpNum);
790 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
792 O << "[" << getRegisterName(MO1.getReg());
794 int32_t OffImm = (int32_t)MO2.getImm();
797 O << ", #-" << -OffImm;
799 O << ", #+" << OffImm;
803 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
805 const MachineOperand &MO1 = MI->getOperand(OpNum);
806 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
808 O << "[" << getRegisterName(MO1.getReg());
810 int32_t OffImm = (int32_t)MO2.getImm() / 4;
813 O << ", #-" << -OffImm * 4;
815 O << ", #+" << OffImm * 4;
819 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
821 const MachineOperand &MO1 = MI->getOperand(OpNum);
822 int32_t OffImm = (int32_t)MO1.getImm();
825 O << "#-" << -OffImm;
830 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
832 const MachineOperand &MO1 = MI->getOperand(OpNum);
833 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
834 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
836 O << "[" << getRegisterName(MO1.getReg());
838 assert(MO2.getReg() && "Invalid so_reg load / store address!");
839 O << ", " << getRegisterName(MO2.getReg());
841 unsigned ShAmt = MO3.getImm();
843 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
844 O << ", lsl #" << ShAmt;
850 //===--------------------------------------------------------------------===//
852 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
853 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
855 O << ARMCondCodeToString(CC);
858 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
859 unsigned Reg = MI->getOperand(OpNum).getReg();
861 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
866 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
867 int Id = (int)MI->getOperand(OpNum).getImm();
868 O << MAI->getPrivateGlobalPrefix()
869 << "PC" << getFunctionNumber() << "_" << Id;
872 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
874 // Always skip the first operand, it's the optional (and implicit writeback).
875 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
876 if (MI->getOperand(i).isImplicit())
878 if ((int)i != OpNum+1) O << ", ";
884 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
885 const char *Modifier) {
886 assert(Modifier && "This operand only works with a modifier!");
887 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
889 if (!strcmp(Modifier, "label")) {
890 unsigned ID = MI->getOperand(OpNum).getImm();
891 O << *GetCPISymbol(ID) << ":\n";
893 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
894 unsigned CPI = MI->getOperand(OpNum).getIndex();
896 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
898 if (MCPE.isMachineConstantPoolEntry()) {
899 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
901 EmitGlobalConstant(MCPE.Val.ConstVal);
906 MCSymbol *ARMAsmPrinter::
907 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
908 const MachineBasicBlock *MBB) const {
909 SmallString<60> Name;
910 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
911 << getFunctionNumber() << '_' << uid << '_' << uid2
912 << "_set_" << MBB->getNumber();
913 return OutContext.GetOrCreateSymbol(Name.str());
916 MCSymbol *ARMAsmPrinter::
917 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
918 SmallString<60> Name;
919 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
920 << getFunctionNumber() << '_' << uid << '_' << uid2;
921 return OutContext.GetOrCreateSymbol(Name.str());
924 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
925 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
927 const MachineOperand &MO1 = MI->getOperand(OpNum);
928 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
930 unsigned JTI = MO1.getIndex();
931 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
932 OutStreamer.EmitLabel(JTISymbol);
934 const char *JTEntryDirective = MAI->getData32bitsDirective();
936 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
937 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
938 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
939 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
940 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
941 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
942 MachineBasicBlock *MBB = JTBBs[i];
943 bool isNew = JTSets.insert(MBB);
945 if (UseSet && isNew) {
947 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
948 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
951 O << JTEntryDirective << ' ';
953 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
954 else if (TM.getRelocationModel() == Reloc::PIC_)
955 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
957 O << *MBB->getSymbol(OutContext);
964 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
965 const MachineOperand &MO1 = MI->getOperand(OpNum);
966 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
967 unsigned JTI = MO1.getIndex();
969 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
970 OutStreamer.EmitLabel(JTISymbol);
972 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
973 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
974 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
975 bool ByteOffset = false, HalfWordOffset = false;
976 if (MI->getOpcode() == ARM::t2TBB)
978 else if (MI->getOpcode() == ARM::t2TBH)
979 HalfWordOffset = true;
981 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
982 MachineBasicBlock *MBB = JTBBs[i];
984 O << MAI->getData8bitsDirective();
985 else if (HalfWordOffset)
986 O << MAI->getData16bitsDirective();
988 if (ByteOffset || HalfWordOffset)
989 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
991 O << "\tb.w " << *MBB->getSymbol(OutContext);
997 // Make sure the instruction that follows TBB is 2-byte aligned.
998 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
999 if (ByteOffset && (JTBBs.size() & 1)) {
1005 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
1006 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1007 if (MI->getOpcode() == ARM::t2TBH)
1012 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
1013 O << MI->getOperand(OpNum).getImm();
1016 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1017 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1018 O << '#' << FP->getValueAPF().convertToFloat();
1020 O.PadToColumn(MAI->getCommentColumn());
1021 O << MAI->getCommentString() << ' ';
1022 WriteAsOperand(O, FP, /*PrintType=*/false);
1026 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1027 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1028 O << '#' << FP->getValueAPF().convertToDouble();
1030 O.PadToColumn(MAI->getCommentColumn());
1031 O << MAI->getCommentString() << ' ';
1032 WriteAsOperand(O, FP, /*PrintType=*/false);
1036 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1037 unsigned AsmVariant, const char *ExtraCode){
1038 // Does this asm operand have a single letter operand modifier?
1039 if (ExtraCode && ExtraCode[0]) {
1040 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1042 switch (ExtraCode[0]) {
1043 default: return true; // Unknown modifier.
1044 case 'a': // Print as a memory address.
1045 if (MI->getOperand(OpNum).isReg()) {
1046 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1050 case 'c': // Don't print "#" before an immediate operand.
1051 if (!MI->getOperand(OpNum).isImm())
1053 printNoHashImmediate(MI, OpNum);
1055 case 'P': // Print a VFP double precision register.
1056 case 'q': // Print a NEON quad precision register.
1057 printOperand(MI, OpNum);
1060 if (TM.getTargetData()->isLittleEndian())
1064 if (TM.getTargetData()->isBigEndian())
1067 case 'H': // Write second word of DI / DF reference.
1068 // Verify that this operand has two consecutive registers.
1069 if (!MI->getOperand(OpNum).isReg() ||
1070 OpNum+1 == MI->getNumOperands() ||
1071 !MI->getOperand(OpNum+1).isReg())
1073 ++OpNum; // Return the high-part.
1077 printOperand(MI, OpNum);
1081 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1082 unsigned OpNum, unsigned AsmVariant,
1083 const char *ExtraCode) {
1084 if (ExtraCode && ExtraCode[0])
1085 return true; // Unknown modifier.
1087 const MachineOperand &MO = MI->getOperand(OpNum);
1088 assert(MO.isReg() && "unexpected inline asm memory operand");
1089 O << "[" << getRegisterName(MO.getReg()) << "]";
1093 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1096 // Call the autogenerated instruction printer routines.
1097 processDebugLoc(MI, true);
1100 printInstructionThroughMCStreamer(MI);
1102 int Opc = MI->getOpcode();
1103 if (Opc == ARM::CONSTPOOL_ENTRY)
1106 printInstruction(MI);
1112 processDebugLoc(MI, false);
1115 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1116 if (Subtarget->isTargetDarwin()) {
1117 Reloc::Model RelocM = TM.getRelocationModel();
1118 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1119 // Declare all the text sections up front (before the DWARF sections
1120 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1121 // them together at the beginning of the object file. This helps
1122 // avoid out-of-range branches that are due a fundamental limitation of
1123 // the way symbol offsets are encoded with the current Darwin ARM
1125 TargetLoweringObjectFileMachO &TLOFMacho =
1126 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1127 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1128 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1129 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1130 if (RelocM == Reloc::DynamicNoPIC) {
1131 const MCSection *sect =
1132 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1133 MCSectionMachO::S_SYMBOL_STUBS,
1134 12, SectionKind::getText());
1135 OutStreamer.SwitchSection(sect);
1137 const MCSection *sect =
1138 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1139 MCSectionMachO::S_SYMBOL_STUBS,
1140 16, SectionKind::getText());
1141 OutStreamer.SwitchSection(sect);
1146 // Use unified assembler syntax.
1147 O << "\t.syntax unified\n";
1149 // Emit ARM Build Attributes
1150 if (Subtarget->isTargetELF()) {
1152 std::string CPUString = Subtarget->getCPUString();
1153 if (CPUString != "generic")
1154 O << "\t.cpu " << CPUString << '\n';
1156 // FIXME: Emit FPU type
1157 if (Subtarget->hasVFP2())
1158 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1160 // Signal various FP modes.
1162 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1163 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1165 if (FiniteOnlyFPMath())
1166 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1168 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1170 // 8-bytes alignment stuff.
1171 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1172 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1174 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1175 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1176 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1177 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1179 // FIXME: Should we signal R9 usage?
1184 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1185 if (Subtarget->isTargetDarwin()) {
1186 // All darwin targets use mach-o.
1187 TargetLoweringObjectFileMachO &TLOFMacho =
1188 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1189 MachineModuleInfoMachO &MMIMacho =
1190 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1194 // Output non-lazy-pointers for external and common global variables.
1195 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1197 if (!Stubs.empty()) {
1198 // Switch with ".non_lazy_symbol_pointer" directive.
1199 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1201 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1202 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1203 O << *Stubs[i].second << "\n\t.long\t0\n";
1207 Stubs = MMIMacho.GetHiddenGVStubList();
1208 if (!Stubs.empty()) {
1209 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1211 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1212 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1215 // Funny Darwin hack: This flag tells the linker that no global symbols
1216 // contain code that falls through to other global symbols (e.g. the obvious
1217 // implementation of multiple entry points). If this doesn't occur, the
1218 // linker can safely perform dead code stripping. Since LLVM never
1219 // generates code that does this, it is always safe to set.
1220 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1224 //===----------------------------------------------------------------------===//
1226 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1227 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1228 switch (MI->getOpcode()) {
1229 case ARM::t2MOVi32imm:
1230 assert(0 && "Should be lowered by thumb2it pass");
1232 case TargetInstrInfo::DBG_LABEL:
1233 case TargetInstrInfo::EH_LABEL:
1234 case TargetInstrInfo::GC_LABEL:
1237 case TargetInstrInfo::KILL:
1240 case TargetInstrInfo::INLINEASM:
1243 case TargetInstrInfo::IMPLICIT_DEF:
1244 printImplicitDef(MI);
1246 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1247 // This is a pseudo op for a label + instruction sequence, which looks like:
1250 // This adds the address of LPC0 to r0.
1253 // FIXME: MOVE TO SHARED PLACE.
1254 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1255 const char *Prefix = MAI->getPrivateGlobalPrefix();
1256 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1257 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1258 OutStreamer.EmitLabel(Label);
1261 // Form and emit tha dd.
1263 AddInst.setOpcode(ARM::ADDrr);
1264 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1265 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1266 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1267 printMCInst(&AddInst);
1270 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1271 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1272 /// in the function. The first operand is the ID# for this instruction, the
1273 /// second is the index into the MachineConstantPool that this is, the third
1274 /// is the size in bytes of this constant pool entry.
1275 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1276 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1279 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1281 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1282 if (MCPE.isMachineConstantPoolEntry())
1283 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1285 EmitGlobalConstant(MCPE.Val.ConstVal);
1289 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1290 // This is a hack that lowers as a two instruction sequence.
1291 unsigned DstReg = MI->getOperand(0).getReg();
1292 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1294 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1295 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1299 TmpInst.setOpcode(ARM::MOVi);
1300 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1301 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1304 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1305 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1307 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1308 printMCInst(&TmpInst);
1314 TmpInst.setOpcode(ARM::ORRri);
1315 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1316 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1317 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1319 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1320 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1322 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1323 printMCInst(&TmpInst);
1327 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1328 // This is a hack that lowers as a two instruction sequence.
1329 unsigned DstReg = MI->getOperand(0).getReg();
1330 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1334 TmpInst.setOpcode(ARM::MOVi16);
1335 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1336 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1339 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1340 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1342 printMCInst(&TmpInst);
1348 TmpInst.setOpcode(ARM::MOVTi16);
1349 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1350 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1351 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1354 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1355 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1357 printMCInst(&TmpInst);
1365 MCInstLowering.Lower(MI, TmpInst);
1367 printMCInst(&TmpInst);
1370 //===----------------------------------------------------------------------===//
1371 // Target Registry Stuff
1372 //===----------------------------------------------------------------------===//
1374 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1375 unsigned SyntaxVariant,
1376 const MCAsmInfo &MAI,
1378 if (SyntaxVariant == 0)
1379 return new ARMInstPrinter(O, MAI, false);
1383 // Force static initialization.
1384 extern "C" void LLVMInitializeARMAsmPrinter() {
1385 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1386 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1388 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1389 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);