1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
172 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
173 printDataDirective(MCPV->getType());
175 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
176 SmallString<128> TmpNameStr;
178 if (ACPV->isLSDA()) {
179 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
180 "_LSDA_" << getFunctionNumber();
181 O << TmpNameStr.str();
182 } else if (ACPV->isBlockAddress()) {
183 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
184 } else if (ACPV->isGlobalValue()) {
185 GlobalValue *GV = ACPV->getGV();
186 bool isIndirect = Subtarget->isTargetDarwin() &&
187 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
189 O << *GetGlobalValueSymbol(GV);
191 // FIXME: Remove this when Darwin transition to @GOT like syntax.
192 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
195 MachineModuleInfoMachO &MMIMachO =
196 MMI->getObjFileInfo<MachineModuleInfoMachO>();
197 const MCSymbol *&StubSym =
198 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
199 MMIMachO.getGVStubEntry(Sym);
201 StubSym = GetGlobalValueSymbol(GV);
204 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
205 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
208 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
209 if (ACPV->getPCAdjustment() != 0) {
210 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
211 << getFunctionNumber() << "_" << ACPV->getLabelId()
212 << "+" << (unsigned)ACPV->getPCAdjustment();
213 if (ACPV->mustAddCurrentAddress())
220 void getAnalysisUsage(AnalysisUsage &AU) const {
221 AsmPrinter::getAnalysisUsage(AU);
222 AU.setPreservesAll();
223 AU.addRequired<MachineModuleInfo>();
224 AU.addRequired<DwarfWriter>();
227 } // end of anonymous namespace
229 #include "ARMGenAsmWriter.inc"
231 /// runOnMachineFunction - This uses the printInstruction()
232 /// method to print assembly for each instruction.
234 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
237 AFI = MF.getInfo<ARMFunctionInfo>();
238 MCP = MF.getConstantPool();
240 SetupMachineFunction(MF);
243 // NOTE: we don't print out constant pools here, they are handled as
248 // Print out labels for the function.
249 const Function *F = MF.getFunction();
250 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
252 switch (F->getLinkage()) {
253 default: llvm_unreachable("Unknown linkage type!");
254 case Function::PrivateLinkage:
255 case Function::InternalLinkage:
257 case Function::ExternalLinkage:
258 O << "\t.globl\t" << *CurrentFnSym << "\n";
260 case Function::LinkerPrivateLinkage:
261 case Function::WeakAnyLinkage:
262 case Function::WeakODRLinkage:
263 case Function::LinkOnceAnyLinkage:
264 case Function::LinkOnceODRLinkage:
265 if (Subtarget->isTargetDarwin()) {
266 O << "\t.globl\t" << *CurrentFnSym << "\n";
267 O << "\t.weak_definition\t" << *CurrentFnSym << "\n";
269 O << MAI->getWeakRefDirective() << *CurrentFnSym << "\n";
274 printVisibility(CurrentFnSym, F->getVisibility());
276 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
277 if (AFI->isThumbFunction()) {
278 EmitAlignment(FnAlign, F, AFI->getAlign());
279 O << "\t.code\t16\n";
280 O << "\t.thumb_func";
281 if (Subtarget->isTargetDarwin())
282 O << "\t" << *CurrentFnSym;
285 EmitAlignment(FnAlign, F);
288 O << *CurrentFnSym << ":\n";
289 // Emit pre-function debug information.
290 DW->BeginFunction(&MF);
292 if (Subtarget->isTargetDarwin()) {
293 // If the function is empty, then we need to emit *something*. Otherwise,
294 // the function's label might be associated with something that it wasn't
295 // meant to be associated with. We emit a noop in this situation.
296 MachineFunction::iterator I = MF.begin();
298 if (++I == MF.end() && MF.front().empty())
302 // Print out code for the function.
303 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
305 // Print a label for the basic block.
307 EmitBasicBlockStart(I);
309 // Print the assembly for the instruction.
310 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
312 printMachineInstruction(II);
315 if (MAI->hasDotTypeDotSizeDirective())
316 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
318 // Emit post-function debug information.
319 DW->EndFunction(&MF);
324 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
325 const char *Modifier) {
326 const MachineOperand &MO = MI->getOperand(OpNum);
327 unsigned TF = MO.getTargetFlags();
329 switch (MO.getType()) {
331 assert(0 && "<unknown operand type>");
332 case MachineOperand::MO_Register: {
333 unsigned Reg = MO.getReg();
334 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
335 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
336 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
337 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
339 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
341 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
342 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
343 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
344 &ARM::DPR_VFP2RegClass);
345 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
347 assert(!MO.getSubReg() && "Subregs should be eliminated!");
348 O << getRegisterName(Reg);
352 case MachineOperand::MO_Immediate: {
353 int64_t Imm = MO.getImm();
355 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
356 (TF & ARMII::MO_LO16))
358 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
359 (TF & ARMII::MO_HI16))
364 case MachineOperand::MO_MachineBasicBlock:
365 O << *GetMBBSymbol(MO.getMBB()->getNumber());
367 case MachineOperand::MO_GlobalAddress: {
368 bool isCallOp = Modifier && !strcmp(Modifier, "call");
369 GlobalValue *GV = MO.getGlobal();
371 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
372 (TF & ARMII::MO_LO16))
374 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
375 (TF & ARMII::MO_HI16))
377 O << *GetGlobalValueSymbol(GV);
379 printOffset(MO.getOffset());
381 if (isCallOp && Subtarget->isTargetELF() &&
382 TM.getRelocationModel() == Reloc::PIC_)
386 case MachineOperand::MO_ExternalSymbol: {
387 bool isCallOp = Modifier && !strcmp(Modifier, "call");
388 O << *GetExternalSymbolSymbol(MO.getSymbolName());
390 if (isCallOp && Subtarget->isTargetELF() &&
391 TM.getRelocationModel() == Reloc::PIC_)
395 case MachineOperand::MO_ConstantPoolIndex:
396 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
397 << '_' << MO.getIndex();
399 case MachineOperand::MO_JumpTableIndex:
400 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
401 << '_' << MO.getIndex();
406 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
407 const MCAsmInfo *MAI) {
408 // Break it up into two parts that make up a shifter immediate.
409 V = ARM_AM::getSOImmVal(V);
410 assert(V != -1 && "Not a valid so_imm value!");
412 unsigned Imm = ARM_AM::getSOImmValImm(V);
413 unsigned Rot = ARM_AM::getSOImmValRot(V);
415 // Print low-level immediate formation info, per
416 // A5.1.3: "Data-processing operands - Immediate".
418 O << "#" << Imm << ", " << Rot;
419 // Pretty printed version.
421 O.PadToColumn(MAI->getCommentColumn());
422 O << MAI->getCommentString() << ' ';
423 O << (int)ARM_AM::rotr32(Imm, Rot);
430 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
431 /// immediate in bits 0-7.
432 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
433 const MachineOperand &MO = MI->getOperand(OpNum);
434 assert(MO.isImm() && "Not a valid so_imm value!");
435 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
438 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
439 /// followed by an 'orr' to materialize.
440 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
441 const MachineOperand &MO = MI->getOperand(OpNum);
442 assert(MO.isImm() && "Not a valid so_imm value!");
443 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
444 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
445 printSOImm(O, V1, VerboseAsm, MAI);
447 printPredicateOperand(MI, 2);
453 printSOImm(O, V2, VerboseAsm, MAI);
456 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
457 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
459 // REG REG 0,SH_OPC - e.g. R5, ROR R3
460 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
461 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
462 const MachineOperand &MO1 = MI->getOperand(Op);
463 const MachineOperand &MO2 = MI->getOperand(Op+1);
464 const MachineOperand &MO3 = MI->getOperand(Op+2);
466 O << getRegisterName(MO1.getReg());
468 // Print the shift opc.
470 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
474 O << getRegisterName(MO2.getReg());
475 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
477 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
481 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
482 const MachineOperand &MO1 = MI->getOperand(Op);
483 const MachineOperand &MO2 = MI->getOperand(Op+1);
484 const MachineOperand &MO3 = MI->getOperand(Op+2);
486 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
487 printOperand(MI, Op);
491 O << "[" << getRegisterName(MO1.getReg());
494 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
496 << (char)ARM_AM::getAM2Op(MO3.getImm())
497 << ARM_AM::getAM2Offset(MO3.getImm());
503 << (char)ARM_AM::getAM2Op(MO3.getImm())
504 << getRegisterName(MO2.getReg());
506 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
508 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
513 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
514 const MachineOperand &MO1 = MI->getOperand(Op);
515 const MachineOperand &MO2 = MI->getOperand(Op+1);
518 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
519 assert(ImmOffs && "Malformed indexed load / store!");
521 << (char)ARM_AM::getAM2Op(MO2.getImm())
526 O << (char)ARM_AM::getAM2Op(MO2.getImm())
527 << getRegisterName(MO1.getReg());
529 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
531 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
535 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
536 const MachineOperand &MO1 = MI->getOperand(Op);
537 const MachineOperand &MO2 = MI->getOperand(Op+1);
538 const MachineOperand &MO3 = MI->getOperand(Op+2);
540 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
541 O << "[" << getRegisterName(MO1.getReg());
545 << (char)ARM_AM::getAM3Op(MO3.getImm())
546 << getRegisterName(MO2.getReg())
551 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
553 << (char)ARM_AM::getAM3Op(MO3.getImm())
558 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
559 const MachineOperand &MO1 = MI->getOperand(Op);
560 const MachineOperand &MO2 = MI->getOperand(Op+1);
563 O << (char)ARM_AM::getAM3Op(MO2.getImm())
564 << getRegisterName(MO1.getReg());
568 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
569 assert(ImmOffs && "Malformed indexed load / store!");
571 << (char)ARM_AM::getAM3Op(MO2.getImm())
575 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
576 const char *Modifier) {
577 const MachineOperand &MO1 = MI->getOperand(Op);
578 const MachineOperand &MO2 = MI->getOperand(Op+1);
579 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
580 if (Modifier && strcmp(Modifier, "submode") == 0) {
581 if (MO1.getReg() == ARM::SP) {
583 bool isLDM = (MI->getOpcode() == ARM::LDM ||
584 MI->getOpcode() == ARM::LDM_RET ||
585 MI->getOpcode() == ARM::t2LDM ||
586 MI->getOpcode() == ARM::t2LDM_RET);
587 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
589 O << ARM_AM::getAMSubModeStr(Mode);
590 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
591 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
592 if (Mode == ARM_AM::ia)
595 printOperand(MI, Op);
596 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
601 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
602 const char *Modifier) {
603 const MachineOperand &MO1 = MI->getOperand(Op);
604 const MachineOperand &MO2 = MI->getOperand(Op+1);
606 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
607 printOperand(MI, Op);
611 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
613 if (Modifier && strcmp(Modifier, "submode") == 0) {
614 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
615 O << ARM_AM::getAMSubModeStr(Mode);
617 } else if (Modifier && strcmp(Modifier, "base") == 0) {
618 // Used for FSTM{D|S} and LSTM{D|S} operations.
619 O << getRegisterName(MO1.getReg());
620 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
625 O << "[" << getRegisterName(MO1.getReg());
627 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
629 << (char)ARM_AM::getAM5Op(MO2.getImm())
635 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
636 const MachineOperand &MO1 = MI->getOperand(Op);
637 const MachineOperand &MO2 = MI->getOperand(Op+1);
638 const MachineOperand &MO3 = MI->getOperand(Op+2);
639 const MachineOperand &MO4 = MI->getOperand(Op+3);
641 O << "[" << getRegisterName(MO1.getReg());
643 // FIXME: Both darwin as and GNU as violate ARM docs here.
644 O << ", :" << MO4.getImm();
648 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
649 if (MO2.getReg() == 0)
652 O << ", " << getRegisterName(MO2.getReg());
656 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
657 const char *Modifier) {
658 if (Modifier && strcmp(Modifier, "label") == 0) {
659 printPCLabel(MI, Op+1);
663 const MachineOperand &MO1 = MI->getOperand(Op);
664 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
665 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
669 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
670 const MachineOperand &MO = MI->getOperand(Op);
671 uint32_t v = ~MO.getImm();
672 int32_t lsb = CountTrailingZeros_32(v);
673 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
674 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
675 O << "#" << lsb << ", #" << width;
678 //===--------------------------------------------------------------------===//
680 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
681 O << "#" << MI->getOperand(Op).getImm() * 4;
685 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
686 // (3 - the number of trailing zeros) is the number of then / else.
687 unsigned Mask = MI->getOperand(Op).getImm();
688 unsigned NumTZ = CountTrailingZeros_32(Mask);
689 assert(NumTZ <= 3 && "Invalid IT mask!");
690 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
691 bool T = (Mask & (1 << Pos)) == 0;
700 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
701 const MachineOperand &MO1 = MI->getOperand(Op);
702 const MachineOperand &MO2 = MI->getOperand(Op+1);
703 O << "[" << getRegisterName(MO1.getReg());
704 O << ", " << getRegisterName(MO2.getReg()) << "]";
708 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
710 const MachineOperand &MO1 = MI->getOperand(Op);
711 const MachineOperand &MO2 = MI->getOperand(Op+1);
712 const MachineOperand &MO3 = MI->getOperand(Op+2);
714 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
715 printOperand(MI, Op);
719 O << "[" << getRegisterName(MO1.getReg());
721 O << ", " << getRegisterName(MO3.getReg());
722 else if (unsigned ImmOffs = MO2.getImm())
723 O << ", #+" << ImmOffs * Scale;
728 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
729 printThumbAddrModeRI5Operand(MI, Op, 1);
732 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
733 printThumbAddrModeRI5Operand(MI, Op, 2);
736 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
737 printThumbAddrModeRI5Operand(MI, Op, 4);
740 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
741 const MachineOperand &MO1 = MI->getOperand(Op);
742 const MachineOperand &MO2 = MI->getOperand(Op+1);
743 O << "[" << getRegisterName(MO1.getReg());
744 if (unsigned ImmOffs = MO2.getImm())
745 O << ", #+" << ImmOffs*4;
749 //===--------------------------------------------------------------------===//
751 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
752 // register with shift forms.
754 // REG IMM, SH_OPC - e.g. R5, LSL #3
755 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
756 const MachineOperand &MO1 = MI->getOperand(OpNum);
757 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
759 unsigned Reg = MO1.getReg();
760 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
761 O << getRegisterName(Reg);
763 // Print the shift opc.
765 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
768 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
769 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
772 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
774 const MachineOperand &MO1 = MI->getOperand(OpNum);
775 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
777 O << "[" << getRegisterName(MO1.getReg());
779 unsigned OffImm = MO2.getImm();
780 if (OffImm) // Don't print +0.
781 O << ", #+" << OffImm;
785 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
787 const MachineOperand &MO1 = MI->getOperand(OpNum);
788 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
790 O << "[" << getRegisterName(MO1.getReg());
792 int32_t OffImm = (int32_t)MO2.getImm();
795 O << ", #-" << -OffImm;
797 O << ", #+" << OffImm;
801 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
803 const MachineOperand &MO1 = MI->getOperand(OpNum);
804 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
806 O << "[" << getRegisterName(MO1.getReg());
808 int32_t OffImm = (int32_t)MO2.getImm() / 4;
811 O << ", #-" << -OffImm * 4;
813 O << ", #+" << OffImm * 4;
817 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
819 const MachineOperand &MO1 = MI->getOperand(OpNum);
820 int32_t OffImm = (int32_t)MO1.getImm();
823 O << "#-" << -OffImm;
828 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
830 const MachineOperand &MO1 = MI->getOperand(OpNum);
831 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
832 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
834 O << "[" << getRegisterName(MO1.getReg());
836 assert(MO2.getReg() && "Invalid so_reg load / store address!");
837 O << ", " << getRegisterName(MO2.getReg());
839 unsigned ShAmt = MO3.getImm();
841 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
842 O << ", lsl #" << ShAmt;
848 //===--------------------------------------------------------------------===//
850 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
851 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
853 O << ARMCondCodeToString(CC);
856 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
857 unsigned Reg = MI->getOperand(OpNum).getReg();
859 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
864 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
865 int Id = (int)MI->getOperand(OpNum).getImm();
866 O << MAI->getPrivateGlobalPrefix()
867 << "PC" << getFunctionNumber() << "_" << Id;
870 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
872 // Always skip the first operand, it's the optional (and implicit writeback).
873 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
874 if (MI->getOperand(i).isImplicit())
876 if ((int)i != OpNum+1) O << ", ";
882 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
883 const char *Modifier) {
884 assert(Modifier && "This operand only works with a modifier!");
885 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
887 if (!strcmp(Modifier, "label")) {
888 unsigned ID = MI->getOperand(OpNum).getImm();
889 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
890 << '_' << ID << ":\n";
892 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
893 unsigned CPI = MI->getOperand(OpNum).getIndex();
895 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
897 if (MCPE.isMachineConstantPoolEntry()) {
898 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
900 EmitGlobalConstant(MCPE.Val.ConstVal);
905 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
906 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
908 const MachineOperand &MO1 = MI->getOperand(OpNum);
909 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
910 unsigned JTI = MO1.getIndex();
911 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
912 << '_' << JTI << '_' << MO2.getImm() << ":\n";
914 const char *JTEntryDirective = MAI->getData32bitsDirective();
916 const MachineFunction *MF = MI->getParent()->getParent();
917 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
918 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
919 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
920 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
921 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
922 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
923 MachineBasicBlock *MBB = JTBBs[i];
924 bool isNew = JTSets.insert(MBB);
927 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
929 O << JTEntryDirective << ' ';
931 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
932 << '_' << JTI << '_' << MO2.getImm()
933 << "_set_" << MBB->getNumber();
934 else if (TM.getRelocationModel() == Reloc::PIC_) {
935 O << *GetMBBSymbol(MBB->getNumber())
936 << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
937 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
939 O << *GetMBBSymbol(MBB->getNumber());
946 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
947 const MachineOperand &MO1 = MI->getOperand(OpNum);
948 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
949 unsigned JTI = MO1.getIndex();
950 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
951 << '_' << JTI << '_' << MO2.getImm() << ":\n";
953 const MachineFunction *MF = MI->getParent()->getParent();
954 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
955 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
956 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
957 bool ByteOffset = false, HalfWordOffset = false;
958 if (MI->getOpcode() == ARM::t2TBB)
960 else if (MI->getOpcode() == ARM::t2TBH)
961 HalfWordOffset = true;
963 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
964 MachineBasicBlock *MBB = JTBBs[i];
966 O << MAI->getData8bitsDirective();
967 else if (HalfWordOffset)
968 O << MAI->getData16bitsDirective();
969 if (ByteOffset || HalfWordOffset) {
970 O << '(' << *GetMBBSymbol(MBB->getNumber());
971 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
972 << '_' << JTI << '_' << MO2.getImm() << ")/2";
974 O << "\tb.w " << *GetMBBSymbol(MBB->getNumber());
980 // Make sure the instruction that follows TBB is 2-byte aligned.
981 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
982 if (ByteOffset && (JTBBs.size() & 1)) {
988 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
989 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
990 if (MI->getOpcode() == ARM::t2TBH)
995 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
996 O << MI->getOperand(OpNum).getImm();
999 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1000 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1001 O << '#' << FP->getValueAPF().convertToFloat();
1003 O.PadToColumn(MAI->getCommentColumn());
1004 O << MAI->getCommentString() << ' ';
1005 WriteAsOperand(O, FP, /*PrintType=*/false);
1009 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1010 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1011 O << '#' << FP->getValueAPF().convertToDouble();
1013 O.PadToColumn(MAI->getCommentColumn());
1014 O << MAI->getCommentString() << ' ';
1015 WriteAsOperand(O, FP, /*PrintType=*/false);
1019 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1020 unsigned AsmVariant, const char *ExtraCode){
1021 // Does this asm operand have a single letter operand modifier?
1022 if (ExtraCode && ExtraCode[0]) {
1023 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1025 switch (ExtraCode[0]) {
1026 default: return true; // Unknown modifier.
1027 case 'a': // Print as a memory address.
1028 if (MI->getOperand(OpNum).isReg()) {
1029 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1033 case 'c': // Don't print "#" before an immediate operand.
1034 if (!MI->getOperand(OpNum).isImm())
1036 printNoHashImmediate(MI, OpNum);
1038 case 'P': // Print a VFP double precision register.
1039 case 'q': // Print a NEON quad precision register.
1040 printOperand(MI, OpNum);
1043 if (TM.getTargetData()->isLittleEndian())
1047 if (TM.getTargetData()->isBigEndian())
1050 case 'H': // Write second word of DI / DF reference.
1051 // Verify that this operand has two consecutive registers.
1052 if (!MI->getOperand(OpNum).isReg() ||
1053 OpNum+1 == MI->getNumOperands() ||
1054 !MI->getOperand(OpNum+1).isReg())
1056 ++OpNum; // Return the high-part.
1060 printOperand(MI, OpNum);
1064 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1065 unsigned OpNum, unsigned AsmVariant,
1066 const char *ExtraCode) {
1067 if (ExtraCode && ExtraCode[0])
1068 return true; // Unknown modifier.
1070 const MachineOperand &MO = MI->getOperand(OpNum);
1071 assert(MO.isReg() && "unexpected inline asm memory operand");
1072 O << "[" << getRegisterName(MO.getReg()) << "]";
1076 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1079 // Call the autogenerated instruction printer routines.
1080 processDebugLoc(MI, true);
1083 printInstructionThroughMCStreamer(MI);
1085 int Opc = MI->getOpcode();
1086 if (Opc == ARM::CONSTPOOL_ENTRY)
1089 printInstruction(MI);
1095 processDebugLoc(MI, false);
1098 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1099 if (Subtarget->isTargetDarwin()) {
1100 Reloc::Model RelocM = TM.getRelocationModel();
1101 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1102 // Declare all the text sections up front (before the DWARF sections
1103 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1104 // them together at the beginning of the object file. This helps
1105 // avoid out-of-range branches that are due a fundamental limitation of
1106 // the way symbol offsets are encoded with the current Darwin ARM
1108 TargetLoweringObjectFileMachO &TLOFMacho =
1109 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1110 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1111 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1112 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1113 if (RelocM == Reloc::DynamicNoPIC) {
1114 const MCSection *sect =
1115 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1116 MCSectionMachO::S_SYMBOL_STUBS,
1117 12, SectionKind::getText());
1118 OutStreamer.SwitchSection(sect);
1120 const MCSection *sect =
1121 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1122 MCSectionMachO::S_SYMBOL_STUBS,
1123 16, SectionKind::getText());
1124 OutStreamer.SwitchSection(sect);
1129 // Use unified assembler syntax.
1130 O << "\t.syntax unified\n";
1132 // Emit ARM Build Attributes
1133 if (Subtarget->isTargetELF()) {
1135 std::string CPUString = Subtarget->getCPUString();
1136 if (CPUString != "generic")
1137 O << "\t.cpu " << CPUString << '\n';
1139 // FIXME: Emit FPU type
1140 if (Subtarget->hasVFP2())
1141 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1143 // Signal various FP modes.
1145 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1146 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1148 if (FiniteOnlyFPMath())
1149 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1151 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1153 // 8-bytes alignment stuff.
1154 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1155 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1157 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1158 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1159 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1160 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1162 // FIXME: Should we signal R9 usage?
1167 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1168 if (Subtarget->isTargetDarwin()) {
1169 // All darwin targets use mach-o.
1170 TargetLoweringObjectFileMachO &TLOFMacho =
1171 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1172 MachineModuleInfoMachO &MMIMacho =
1173 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1177 // Output non-lazy-pointers for external and common global variables.
1178 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1180 if (!Stubs.empty()) {
1181 // Switch with ".non_lazy_symbol_pointer" directive.
1182 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1184 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1185 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1186 O << *Stubs[i].second << "\n\t.long\t0\n";
1190 Stubs = MMIMacho.GetHiddenGVStubList();
1191 if (!Stubs.empty()) {
1192 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1194 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1195 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1198 // Funny Darwin hack: This flag tells the linker that no global symbols
1199 // contain code that falls through to other global symbols (e.g. the obvious
1200 // implementation of multiple entry points). If this doesn't occur, the
1201 // linker can safely perform dead code stripping. Since LLVM never
1202 // generates code that does this, it is always safe to set.
1203 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1207 //===----------------------------------------------------------------------===//
1209 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1210 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1211 switch (MI->getOpcode()) {
1212 case ARM::t2MOVi32imm:
1213 assert(0 && "Should be lowered by thumb2it pass");
1215 case TargetInstrInfo::DBG_LABEL:
1216 case TargetInstrInfo::EH_LABEL:
1217 case TargetInstrInfo::GC_LABEL:
1220 case TargetInstrInfo::KILL:
1223 case TargetInstrInfo::INLINEASM:
1226 case TargetInstrInfo::IMPLICIT_DEF:
1227 printImplicitDef(MI);
1229 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1230 // This is a pseudo op for a label + instruction sequence, which looks like:
1233 // This adds the address of LPC0 to r0.
1236 // FIXME: MOVE TO SHARED PLACE.
1237 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1238 const char *Prefix = MAI->getPrivateGlobalPrefix();
1239 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1240 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1241 OutStreamer.EmitLabel(Label);
1244 // Form and emit tha dd.
1246 AddInst.setOpcode(ARM::ADDrr);
1247 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1248 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1249 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1250 printMCInst(&AddInst);
1253 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1254 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1255 /// in the function. The first operand is the ID# for this instruction, the
1256 /// second is the index into the MachineConstantPool that this is, the third
1257 /// is the size in bytes of this constant pool entry.
1258 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1259 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1263 const char *Prefix = MAI->getPrivateGlobalPrefix();
1264 MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
1265 Twine(getFunctionNumber())+
1266 "_"+ Twine(LabelId));
1267 OutStreamer.EmitLabel(Label);
1269 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1270 if (MCPE.isMachineConstantPoolEntry())
1271 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1273 EmitGlobalConstant(MCPE.Val.ConstVal);
1277 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1278 // This is a hack that lowers as a two instruction sequence.
1279 unsigned DstReg = MI->getOperand(0).getReg();
1280 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1282 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1283 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1287 TmpInst.setOpcode(ARM::MOVi);
1288 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1289 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1292 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1293 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1295 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1296 printMCInst(&TmpInst);
1302 TmpInst.setOpcode(ARM::ORRri);
1303 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1304 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1305 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1307 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1308 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1310 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1311 printMCInst(&TmpInst);
1315 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1316 // This is a hack that lowers as a two instruction sequence.
1317 unsigned DstReg = MI->getOperand(0).getReg();
1318 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1322 TmpInst.setOpcode(ARM::MOVi16);
1323 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1324 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1327 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1328 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1330 printMCInst(&TmpInst);
1336 TmpInst.setOpcode(ARM::MOVTi16);
1337 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1338 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1339 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1342 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1343 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1345 printMCInst(&TmpInst);
1353 MCInstLowering.Lower(MI, TmpInst);
1355 printMCInst(&TmpInst);
1358 //===----------------------------------------------------------------------===//
1359 // Target Registry Stuff
1360 //===----------------------------------------------------------------------===//
1362 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1363 unsigned SyntaxVariant,
1364 const MCAsmInfo &MAI,
1366 if (SyntaxVariant == 0)
1367 return new ARMInstPrinter(O, MAI, false);
1371 // Force static initialization.
1372 extern "C" void LLVMInitializeARMAsmPrinter() {
1373 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1374 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1376 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1377 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);