1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void PrintGlobalVariable(const GlobalVariable* GVar);
163 void printInstruction(const MachineInstr *MI); // autogenerated.
164 static const char *getRegisterName(unsigned RegNo);
166 void printMachineInstruction(const MachineInstr *MI);
167 bool runOnMachineFunction(MachineFunction &F);
168 void EmitStartOfAsmFile(Module &M);
169 void EmitEndOfAsmFile(Module &M);
171 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
173 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
174 printDataDirective(MCPV->getType());
176 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
177 SmallString<128> TmpNameStr;
179 if (ACPV->isLSDA()) {
180 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
181 "_LSDA_" << getFunctionNumber();
182 O << TmpNameStr.str();
183 } else if (ACPV->isBlockAddress()) {
184 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
185 } else if (ACPV->isGlobalValue()) {
186 GlobalValue *GV = ACPV->getGV();
187 bool isIndirect = Subtarget->isTargetDarwin() &&
188 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
190 O << *GetGlobalValueSymbol(GV);
192 // FIXME: Remove this when Darwin transition to @GOT like syntax.
193 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
196 MachineModuleInfoMachO &MMIMachO =
197 MMI->getObjFileInfo<MachineModuleInfoMachO>();
198 const MCSymbol *&StubSym =
199 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
200 MMIMachO.getGVStubEntry(Sym);
202 StubSym = GetGlobalValueSymbol(GV);
205 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
206 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
209 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
210 if (ACPV->getPCAdjustment() != 0) {
211 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
212 << getFunctionNumber() << "_" << ACPV->getLabelId()
213 << "+" << (unsigned)ACPV->getPCAdjustment();
214 if (ACPV->mustAddCurrentAddress())
221 void getAnalysisUsage(AnalysisUsage &AU) const {
222 AsmPrinter::getAnalysisUsage(AU);
223 AU.setPreservesAll();
224 AU.addRequired<MachineModuleInfo>();
225 AU.addRequired<DwarfWriter>();
228 } // end of anonymous namespace
230 #include "ARMGenAsmWriter.inc"
232 /// runOnMachineFunction - This uses the printInstruction()
233 /// method to print assembly for each instruction.
235 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
238 AFI = MF.getInfo<ARMFunctionInfo>();
239 MCP = MF.getConstantPool();
241 SetupMachineFunction(MF);
244 // NOTE: we don't print out constant pools here, they are handled as
249 // Print out labels for the function.
250 const Function *F = MF.getFunction();
251 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
253 switch (F->getLinkage()) {
254 default: llvm_unreachable("Unknown linkage type!");
255 case Function::PrivateLinkage:
256 case Function::InternalLinkage:
258 case Function::ExternalLinkage:
259 O << "\t.globl\t" << *CurrentFnSym << "\n";
261 case Function::LinkerPrivateLinkage:
262 case Function::WeakAnyLinkage:
263 case Function::WeakODRLinkage:
264 case Function::LinkOnceAnyLinkage:
265 case Function::LinkOnceODRLinkage:
266 if (Subtarget->isTargetDarwin()) {
267 O << "\t.globl\t" << *CurrentFnSym << "\n";
268 O << "\t.weak_definition\t" << *CurrentFnSym << "\n";
270 O << MAI->getWeakRefDirective() << *CurrentFnSym << "\n";
275 printVisibility(CurrentFnSym, F->getVisibility());
277 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
278 if (AFI->isThumbFunction()) {
279 EmitAlignment(FnAlign, F, AFI->getAlign());
280 O << "\t.code\t16\n";
281 O << "\t.thumb_func";
282 if (Subtarget->isTargetDarwin())
283 O << "\t" << *CurrentFnSym;
286 EmitAlignment(FnAlign, F);
289 O << *CurrentFnSym << ":\n";
290 // Emit pre-function debug information.
291 DW->BeginFunction(&MF);
293 if (Subtarget->isTargetDarwin()) {
294 // If the function is empty, then we need to emit *something*. Otherwise,
295 // the function's label might be associated with something that it wasn't
296 // meant to be associated with. We emit a noop in this situation.
297 MachineFunction::iterator I = MF.begin();
299 if (++I == MF.end() && MF.front().empty())
303 // Print out code for the function.
304 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
306 // Print a label for the basic block.
308 EmitBasicBlockStart(I);
310 // Print the assembly for the instruction.
311 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
313 printMachineInstruction(II);
316 if (MAI->hasDotTypeDotSizeDirective())
317 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
319 // Emit post-function debug information.
320 DW->EndFunction(&MF);
325 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
326 const char *Modifier) {
327 const MachineOperand &MO = MI->getOperand(OpNum);
328 unsigned TF = MO.getTargetFlags();
330 switch (MO.getType()) {
332 assert(0 && "<unknown operand type>");
333 case MachineOperand::MO_Register: {
334 unsigned Reg = MO.getReg();
335 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
336 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
337 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
338 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
340 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
342 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
343 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
344 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
345 &ARM::DPR_VFP2RegClass);
346 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
348 assert(!MO.getSubReg() && "Subregs should be eliminated!");
349 O << getRegisterName(Reg);
353 case MachineOperand::MO_Immediate: {
354 int64_t Imm = MO.getImm();
356 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
357 (TF & ARMII::MO_LO16))
359 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
360 (TF & ARMII::MO_HI16))
365 case MachineOperand::MO_MachineBasicBlock:
366 O << *GetMBBSymbol(MO.getMBB()->getNumber());
368 case MachineOperand::MO_GlobalAddress: {
369 bool isCallOp = Modifier && !strcmp(Modifier, "call");
370 GlobalValue *GV = MO.getGlobal();
372 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
373 (TF & ARMII::MO_LO16))
375 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
376 (TF & ARMII::MO_HI16))
378 O << *GetGlobalValueSymbol(GV);
380 printOffset(MO.getOffset());
382 if (isCallOp && Subtarget->isTargetELF() &&
383 TM.getRelocationModel() == Reloc::PIC_)
387 case MachineOperand::MO_ExternalSymbol: {
388 bool isCallOp = Modifier && !strcmp(Modifier, "call");
389 O << *GetExternalSymbolSymbol(MO.getSymbolName());
391 if (isCallOp && Subtarget->isTargetELF() &&
392 TM.getRelocationModel() == Reloc::PIC_)
396 case MachineOperand::MO_ConstantPoolIndex:
397 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
398 << '_' << MO.getIndex();
400 case MachineOperand::MO_JumpTableIndex:
401 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
402 << '_' << MO.getIndex();
407 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
408 const MCAsmInfo *MAI) {
409 // Break it up into two parts that make up a shifter immediate.
410 V = ARM_AM::getSOImmVal(V);
411 assert(V != -1 && "Not a valid so_imm value!");
413 unsigned Imm = ARM_AM::getSOImmValImm(V);
414 unsigned Rot = ARM_AM::getSOImmValRot(V);
416 // Print low-level immediate formation info, per
417 // A5.1.3: "Data-processing operands - Immediate".
419 O << "#" << Imm << ", " << Rot;
420 // Pretty printed version.
422 O.PadToColumn(MAI->getCommentColumn());
423 O << MAI->getCommentString() << ' ';
424 O << (int)ARM_AM::rotr32(Imm, Rot);
431 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
432 /// immediate in bits 0-7.
433 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
434 const MachineOperand &MO = MI->getOperand(OpNum);
435 assert(MO.isImm() && "Not a valid so_imm value!");
436 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
439 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
440 /// followed by an 'orr' to materialize.
441 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
442 const MachineOperand &MO = MI->getOperand(OpNum);
443 assert(MO.isImm() && "Not a valid so_imm value!");
444 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
445 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
446 printSOImm(O, V1, VerboseAsm, MAI);
448 printPredicateOperand(MI, 2);
454 printSOImm(O, V2, VerboseAsm, MAI);
457 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
458 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
460 // REG REG 0,SH_OPC - e.g. R5, ROR R3
461 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
462 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
463 const MachineOperand &MO1 = MI->getOperand(Op);
464 const MachineOperand &MO2 = MI->getOperand(Op+1);
465 const MachineOperand &MO3 = MI->getOperand(Op+2);
467 O << getRegisterName(MO1.getReg());
469 // Print the shift opc.
471 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
475 O << getRegisterName(MO2.getReg());
476 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
478 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
482 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
483 const MachineOperand &MO1 = MI->getOperand(Op);
484 const MachineOperand &MO2 = MI->getOperand(Op+1);
485 const MachineOperand &MO3 = MI->getOperand(Op+2);
487 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
488 printOperand(MI, Op);
492 O << "[" << getRegisterName(MO1.getReg());
495 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
497 << (char)ARM_AM::getAM2Op(MO3.getImm())
498 << ARM_AM::getAM2Offset(MO3.getImm());
504 << (char)ARM_AM::getAM2Op(MO3.getImm())
505 << getRegisterName(MO2.getReg());
507 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
509 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
514 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
515 const MachineOperand &MO1 = MI->getOperand(Op);
516 const MachineOperand &MO2 = MI->getOperand(Op+1);
519 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
520 assert(ImmOffs && "Malformed indexed load / store!");
522 << (char)ARM_AM::getAM2Op(MO2.getImm())
527 O << (char)ARM_AM::getAM2Op(MO2.getImm())
528 << getRegisterName(MO1.getReg());
530 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
532 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
536 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
537 const MachineOperand &MO1 = MI->getOperand(Op);
538 const MachineOperand &MO2 = MI->getOperand(Op+1);
539 const MachineOperand &MO3 = MI->getOperand(Op+2);
541 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
542 O << "[" << getRegisterName(MO1.getReg());
546 << (char)ARM_AM::getAM3Op(MO3.getImm())
547 << getRegisterName(MO2.getReg())
552 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
554 << (char)ARM_AM::getAM3Op(MO3.getImm())
559 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
560 const MachineOperand &MO1 = MI->getOperand(Op);
561 const MachineOperand &MO2 = MI->getOperand(Op+1);
564 O << (char)ARM_AM::getAM3Op(MO2.getImm())
565 << getRegisterName(MO1.getReg());
569 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
570 assert(ImmOffs && "Malformed indexed load / store!");
572 << (char)ARM_AM::getAM3Op(MO2.getImm())
576 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
577 const char *Modifier) {
578 const MachineOperand &MO1 = MI->getOperand(Op);
579 const MachineOperand &MO2 = MI->getOperand(Op+1);
580 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
581 if (Modifier && strcmp(Modifier, "submode") == 0) {
582 if (MO1.getReg() == ARM::SP) {
584 bool isLDM = (MI->getOpcode() == ARM::LDM ||
585 MI->getOpcode() == ARM::LDM_RET ||
586 MI->getOpcode() == ARM::t2LDM ||
587 MI->getOpcode() == ARM::t2LDM_RET);
588 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
590 O << ARM_AM::getAMSubModeStr(Mode);
591 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
592 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
593 if (Mode == ARM_AM::ia)
596 printOperand(MI, Op);
597 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
602 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
603 const char *Modifier) {
604 const MachineOperand &MO1 = MI->getOperand(Op);
605 const MachineOperand &MO2 = MI->getOperand(Op+1);
607 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
608 printOperand(MI, Op);
612 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
614 if (Modifier && strcmp(Modifier, "submode") == 0) {
615 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
616 O << ARM_AM::getAMSubModeStr(Mode);
618 } else if (Modifier && strcmp(Modifier, "base") == 0) {
619 // Used for FSTM{D|S} and LSTM{D|S} operations.
620 O << getRegisterName(MO1.getReg());
621 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
626 O << "[" << getRegisterName(MO1.getReg());
628 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
630 << (char)ARM_AM::getAM5Op(MO2.getImm())
636 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
637 const MachineOperand &MO1 = MI->getOperand(Op);
638 const MachineOperand &MO2 = MI->getOperand(Op+1);
639 const MachineOperand &MO3 = MI->getOperand(Op+2);
640 const MachineOperand &MO4 = MI->getOperand(Op+3);
642 O << "[" << getRegisterName(MO1.getReg());
644 // FIXME: Both darwin as and GNU as violate ARM docs here.
645 O << ", :" << MO4.getImm();
649 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
650 if (MO2.getReg() == 0)
653 O << ", " << getRegisterName(MO2.getReg());
657 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
658 const char *Modifier) {
659 if (Modifier && strcmp(Modifier, "label") == 0) {
660 printPCLabel(MI, Op+1);
664 const MachineOperand &MO1 = MI->getOperand(Op);
665 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
666 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
670 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
671 const MachineOperand &MO = MI->getOperand(Op);
672 uint32_t v = ~MO.getImm();
673 int32_t lsb = CountTrailingZeros_32(v);
674 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
675 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
676 O << "#" << lsb << ", #" << width;
679 //===--------------------------------------------------------------------===//
681 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
682 O << "#" << MI->getOperand(Op).getImm() * 4;
686 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
687 // (3 - the number of trailing zeros) is the number of then / else.
688 unsigned Mask = MI->getOperand(Op).getImm();
689 unsigned NumTZ = CountTrailingZeros_32(Mask);
690 assert(NumTZ <= 3 && "Invalid IT mask!");
691 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
692 bool T = (Mask & (1 << Pos)) == 0;
701 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
702 const MachineOperand &MO1 = MI->getOperand(Op);
703 const MachineOperand &MO2 = MI->getOperand(Op+1);
704 O << "[" << getRegisterName(MO1.getReg());
705 O << ", " << getRegisterName(MO2.getReg()) << "]";
709 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
711 const MachineOperand &MO1 = MI->getOperand(Op);
712 const MachineOperand &MO2 = MI->getOperand(Op+1);
713 const MachineOperand &MO3 = MI->getOperand(Op+2);
715 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
716 printOperand(MI, Op);
720 O << "[" << getRegisterName(MO1.getReg());
722 O << ", " << getRegisterName(MO3.getReg());
723 else if (unsigned ImmOffs = MO2.getImm())
724 O << ", #+" << ImmOffs * Scale;
729 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
730 printThumbAddrModeRI5Operand(MI, Op, 1);
733 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
734 printThumbAddrModeRI5Operand(MI, Op, 2);
737 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
738 printThumbAddrModeRI5Operand(MI, Op, 4);
741 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
742 const MachineOperand &MO1 = MI->getOperand(Op);
743 const MachineOperand &MO2 = MI->getOperand(Op+1);
744 O << "[" << getRegisterName(MO1.getReg());
745 if (unsigned ImmOffs = MO2.getImm())
746 O << ", #+" << ImmOffs*4;
750 //===--------------------------------------------------------------------===//
752 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
753 // register with shift forms.
755 // REG IMM, SH_OPC - e.g. R5, LSL #3
756 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
757 const MachineOperand &MO1 = MI->getOperand(OpNum);
758 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
760 unsigned Reg = MO1.getReg();
761 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
762 O << getRegisterName(Reg);
764 // Print the shift opc.
766 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
769 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
770 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
773 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
775 const MachineOperand &MO1 = MI->getOperand(OpNum);
776 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
778 O << "[" << getRegisterName(MO1.getReg());
780 unsigned OffImm = MO2.getImm();
781 if (OffImm) // Don't print +0.
782 O << ", #+" << OffImm;
786 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
788 const MachineOperand &MO1 = MI->getOperand(OpNum);
789 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
791 O << "[" << getRegisterName(MO1.getReg());
793 int32_t OffImm = (int32_t)MO2.getImm();
796 O << ", #-" << -OffImm;
798 O << ", #+" << OffImm;
802 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
804 const MachineOperand &MO1 = MI->getOperand(OpNum);
805 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
807 O << "[" << getRegisterName(MO1.getReg());
809 int32_t OffImm = (int32_t)MO2.getImm() / 4;
812 O << ", #-" << -OffImm * 4;
814 O << ", #+" << OffImm * 4;
818 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
820 const MachineOperand &MO1 = MI->getOperand(OpNum);
821 int32_t OffImm = (int32_t)MO1.getImm();
824 O << "#-" << -OffImm;
829 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
831 const MachineOperand &MO1 = MI->getOperand(OpNum);
832 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
833 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
835 O << "[" << getRegisterName(MO1.getReg());
837 assert(MO2.getReg() && "Invalid so_reg load / store address!");
838 O << ", " << getRegisterName(MO2.getReg());
840 unsigned ShAmt = MO3.getImm();
842 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
843 O << ", lsl #" << ShAmt;
849 //===--------------------------------------------------------------------===//
851 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
852 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
854 O << ARMCondCodeToString(CC);
857 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
858 unsigned Reg = MI->getOperand(OpNum).getReg();
860 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
865 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
866 int Id = (int)MI->getOperand(OpNum).getImm();
867 O << MAI->getPrivateGlobalPrefix()
868 << "PC" << getFunctionNumber() << "_" << Id;
871 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
873 // Always skip the first operand, it's the optional (and implicit writeback).
874 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
875 if (MI->getOperand(i).isImplicit())
877 if ((int)i != OpNum+1) O << ", ";
883 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
884 const char *Modifier) {
885 assert(Modifier && "This operand only works with a modifier!");
886 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
888 if (!strcmp(Modifier, "label")) {
889 unsigned ID = MI->getOperand(OpNum).getImm();
890 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
891 << '_' << ID << ":\n";
893 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
894 unsigned CPI = MI->getOperand(OpNum).getIndex();
896 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
898 if (MCPE.isMachineConstantPoolEntry()) {
899 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
901 EmitGlobalConstant(MCPE.Val.ConstVal);
906 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
907 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
909 const MachineOperand &MO1 = MI->getOperand(OpNum);
910 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
911 unsigned JTI = MO1.getIndex();
912 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
913 << '_' << JTI << '_' << MO2.getImm() << ":\n";
915 const char *JTEntryDirective = MAI->getData32bitsDirective();
917 const MachineFunction *MF = MI->getParent()->getParent();
918 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
919 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
920 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
921 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
922 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
923 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
924 MachineBasicBlock *MBB = JTBBs[i];
925 bool isNew = JTSets.insert(MBB);
928 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
930 O << JTEntryDirective << ' ';
932 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
933 << '_' << JTI << '_' << MO2.getImm()
934 << "_set_" << MBB->getNumber();
935 else if (TM.getRelocationModel() == Reloc::PIC_) {
936 O << *GetMBBSymbol(MBB->getNumber())
937 << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
938 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
940 O << *GetMBBSymbol(MBB->getNumber());
947 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
948 const MachineOperand &MO1 = MI->getOperand(OpNum);
949 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
950 unsigned JTI = MO1.getIndex();
951 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
952 << '_' << JTI << '_' << MO2.getImm() << ":\n";
954 const MachineFunction *MF = MI->getParent()->getParent();
955 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
956 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
957 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
958 bool ByteOffset = false, HalfWordOffset = false;
959 if (MI->getOpcode() == ARM::t2TBB)
961 else if (MI->getOpcode() == ARM::t2TBH)
962 HalfWordOffset = true;
964 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
965 MachineBasicBlock *MBB = JTBBs[i];
967 O << MAI->getData8bitsDirective();
968 else if (HalfWordOffset)
969 O << MAI->getData16bitsDirective();
970 if (ByteOffset || HalfWordOffset) {
971 O << '(' << *GetMBBSymbol(MBB->getNumber());
972 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
973 << '_' << JTI << '_' << MO2.getImm() << ")/2";
975 O << "\tb.w " << *GetMBBSymbol(MBB->getNumber());
981 // Make sure the instruction that follows TBB is 2-byte aligned.
982 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
983 if (ByteOffset && (JTBBs.size() & 1)) {
989 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
990 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
991 if (MI->getOpcode() == ARM::t2TBH)
996 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
997 O << MI->getOperand(OpNum).getImm();
1000 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1001 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1002 O << '#' << FP->getValueAPF().convertToFloat();
1004 O.PadToColumn(MAI->getCommentColumn());
1005 O << MAI->getCommentString() << ' ';
1006 WriteAsOperand(O, FP, /*PrintType=*/false);
1010 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1011 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1012 O << '#' << FP->getValueAPF().convertToDouble();
1014 O.PadToColumn(MAI->getCommentColumn());
1015 O << MAI->getCommentString() << ' ';
1016 WriteAsOperand(O, FP, /*PrintType=*/false);
1020 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1021 unsigned AsmVariant, const char *ExtraCode){
1022 // Does this asm operand have a single letter operand modifier?
1023 if (ExtraCode && ExtraCode[0]) {
1024 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1026 switch (ExtraCode[0]) {
1027 default: return true; // Unknown modifier.
1028 case 'a': // Print as a memory address.
1029 if (MI->getOperand(OpNum).isReg()) {
1030 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1034 case 'c': // Don't print "#" before an immediate operand.
1035 if (!MI->getOperand(OpNum).isImm())
1037 printNoHashImmediate(MI, OpNum);
1039 case 'P': // Print a VFP double precision register.
1040 case 'q': // Print a NEON quad precision register.
1041 printOperand(MI, OpNum);
1044 if (TM.getTargetData()->isLittleEndian())
1048 if (TM.getTargetData()->isBigEndian())
1051 case 'H': // Write second word of DI / DF reference.
1052 // Verify that this operand has two consecutive registers.
1053 if (!MI->getOperand(OpNum).isReg() ||
1054 OpNum+1 == MI->getNumOperands() ||
1055 !MI->getOperand(OpNum+1).isReg())
1057 ++OpNum; // Return the high-part.
1061 printOperand(MI, OpNum);
1065 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1066 unsigned OpNum, unsigned AsmVariant,
1067 const char *ExtraCode) {
1068 if (ExtraCode && ExtraCode[0])
1069 return true; // Unknown modifier.
1071 const MachineOperand &MO = MI->getOperand(OpNum);
1072 assert(MO.isReg() && "unexpected inline asm memory operand");
1073 O << "[" << getRegisterName(MO.getReg()) << "]";
1077 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1080 // Call the autogenerated instruction printer routines.
1081 processDebugLoc(MI, true);
1084 printInstructionThroughMCStreamer(MI);
1086 int Opc = MI->getOpcode();
1087 if (Opc == ARM::CONSTPOOL_ENTRY)
1090 printInstruction(MI);
1096 processDebugLoc(MI, false);
1099 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1100 if (Subtarget->isTargetDarwin()) {
1101 Reloc::Model RelocM = TM.getRelocationModel();
1102 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1103 // Declare all the text sections up front (before the DWARF sections
1104 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1105 // them together at the beginning of the object file. This helps
1106 // avoid out-of-range branches that are due a fundamental limitation of
1107 // the way symbol offsets are encoded with the current Darwin ARM
1109 TargetLoweringObjectFileMachO &TLOFMacho =
1110 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1111 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1112 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1113 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1114 if (RelocM == Reloc::DynamicNoPIC) {
1115 const MCSection *sect =
1116 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1117 MCSectionMachO::S_SYMBOL_STUBS,
1118 12, SectionKind::getText());
1119 OutStreamer.SwitchSection(sect);
1121 const MCSection *sect =
1122 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1123 MCSectionMachO::S_SYMBOL_STUBS,
1124 16, SectionKind::getText());
1125 OutStreamer.SwitchSection(sect);
1130 // Use unified assembler syntax.
1131 O << "\t.syntax unified\n";
1133 // Emit ARM Build Attributes
1134 if (Subtarget->isTargetELF()) {
1136 std::string CPUString = Subtarget->getCPUString();
1137 if (CPUString != "generic")
1138 O << "\t.cpu " << CPUString << '\n';
1140 // FIXME: Emit FPU type
1141 if (Subtarget->hasVFP2())
1142 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1144 // Signal various FP modes.
1146 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1147 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1149 if (FiniteOnlyFPMath())
1150 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1152 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1154 // 8-bytes alignment stuff.
1155 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1156 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1158 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1159 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1160 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1161 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1163 // FIXME: Should we signal R9 usage?
1167 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1168 const TargetData *TD = TM.getTargetData();
1170 if (!GVar->hasInitializer()) // External global require no code
1173 // Check to see if this is a special global used by LLVM, if so, emit it.
1175 if (EmitSpecialLLVMGlobal(GVar)) {
1176 if (Subtarget->isTargetDarwin() &&
1177 TM.getRelocationModel() == Reloc::Static) {
1178 if (GVar->getName() == "llvm.global_ctors")
1179 O << ".reference .constructors_used\n";
1180 else if (GVar->getName() == "llvm.global_dtors")
1181 O << ".reference .destructors_used\n";
1186 MCSymbol *GVarSym = GetGlobalValueSymbol(GVar);
1188 Constant *C = GVar->getInitializer();
1189 const Type *Type = C->getType();
1190 unsigned Size = TD->getTypeAllocSize(Type);
1191 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1192 bool isDarwin = Subtarget->isTargetDarwin();
1194 printVisibility(GVarSym, GVar->getVisibility());
1196 if (Subtarget->isTargetELF())
1197 O << "\t.type " << *GVarSym << ",%object\n";
1199 SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GVar, TM);
1201 // Handle normal common symbols.
1202 if (GVKind.isCommon()) {
1203 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1205 O << ".comm " << *GVarSym << ',' << Size;
1206 if (MAI->getCOMMDirectiveTakesAlignment())
1207 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1210 O << "\t\t" << MAI->getCommentString() << " '";
1211 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1218 const MCSection *TheSection =
1219 getObjFileLowering().SectionForGlobal(GVar, GVKind, Mang, TM);
1221 // Handle the zerofill directive on darwin, which is a special form of BSS
1223 if (GVKind.isBSS() && MAI->hasMachoZeroFillDirective()) {
1224 TargetLoweringObjectFileMachO &TLOFMacho =
1225 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1226 if (TLOFMacho.isDataCommonSection(TheSection)) {
1228 OutStreamer.EmitSymbolAttribute(GVarSym, MCStreamer::Global);
1229 // .zerofill __DATA, __common, _foo, 400, 5
1230 OutStreamer.EmitZerofill(TheSection, GVarSym, Size, 1 << Align);
1235 OutStreamer.SwitchSection(TheSection);
1237 // FIXME: get this stuff from section kind flags.
1238 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1239 // Don't put things that should go in the cstring section into "comm".
1240 !TheSection->getKind().isMergeableCString() &&
1241 (GVar->hasLocalLinkage() || GVar->isWeakForLinker())) {
1242 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1245 if (GVar->hasLocalLinkage()) {
1246 O << MAI->getLCOMMDirective() << *GVarSym << ',' << Size
1248 } else if (GVar->hasCommonLinkage()) {
1249 O << MAI->getCOMMDirective() << *GVarSym << ',' << Size
1252 OutStreamer.SwitchSection(TheSection);
1253 O << "\t.globl " << *GVarSym << '\n' << MAI->getWeakDefDirective();
1254 O << *GVarSym << '\n';
1255 EmitAlignment(Align, GVar);
1256 O << *GVarSym << ":";
1258 O.PadToColumn(MAI->getCommentColumn());
1259 O << MAI->getCommentString() << ' ';
1260 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1263 EmitGlobalConstant(C);
1266 } else if (MAI->getLCOMMDirective() != NULL) {
1267 if (GVar->hasLocalLinkage()) {
1268 O << MAI->getLCOMMDirective() << *GVarSym << "," << Size;
1270 O << MAI->getCOMMDirective() << *GVarSym << "," << Size;
1271 if (MAI->getCOMMDirectiveTakesAlignment())
1272 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1275 if (GVar->hasLocalLinkage())
1276 O << "\t.local\t" << *GVarSym << '\n';
1277 O << MAI->getCOMMDirective() << *GVarSym << "," << Size;
1278 if (MAI->getCOMMDirectiveTakesAlignment())
1279 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1282 O.PadToColumn(MAI->getCommentColumn());
1283 O << MAI->getCommentString() << ' ';
1284 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1290 switch (GVar->getLinkage()) {
1291 case GlobalValue::CommonLinkage:
1292 case GlobalValue::LinkOnceAnyLinkage:
1293 case GlobalValue::LinkOnceODRLinkage:
1294 case GlobalValue::WeakAnyLinkage:
1295 case GlobalValue::WeakODRLinkage:
1296 case GlobalValue::LinkerPrivateLinkage:
1298 O << "\t.globl " << *GVarSym
1299 << "\n\t.weak_definition " << *GVarSym << "\n";
1301 O << "\t.weak " << *GVarSym << "\n";
1304 case GlobalValue::AppendingLinkage:
1305 // FIXME: appending linkage variables should go into a section of
1306 // their name or something. For now, just emit them as external.
1307 case GlobalValue::ExternalLinkage:
1308 O << "\t.globl " << *GVarSym << "\n";
1310 case GlobalValue::PrivateLinkage:
1311 case GlobalValue::InternalLinkage:
1314 llvm_unreachable("Unknown linkage type!");
1317 EmitAlignment(Align, GVar);
1318 O << *GVarSym << ":";
1320 O.PadToColumn(MAI->getCommentColumn());
1321 O << MAI->getCommentString() << ' ';
1322 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1325 if (MAI->hasDotTypeDotSizeDirective())
1326 O << "\t.size " << *GVarSym << ", " << Size << "\n";
1328 EmitGlobalConstant(C);
1333 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1334 if (Subtarget->isTargetDarwin()) {
1335 // All darwin targets use mach-o.
1336 TargetLoweringObjectFileMachO &TLOFMacho =
1337 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1338 MachineModuleInfoMachO &MMIMacho =
1339 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1343 // Output non-lazy-pointers for external and common global variables.
1344 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1346 if (!Stubs.empty()) {
1347 // Switch with ".non_lazy_symbol_pointer" directive.
1348 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1350 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1351 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1352 O << *Stubs[i].second << "\n\t.long\t0\n";
1356 Stubs = MMIMacho.GetHiddenGVStubList();
1357 if (!Stubs.empty()) {
1358 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1360 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1361 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1364 // Funny Darwin hack: This flag tells the linker that no global symbols
1365 // contain code that falls through to other global symbols (e.g. the obvious
1366 // implementation of multiple entry points). If this doesn't occur, the
1367 // linker can safely perform dead code stripping. Since LLVM never
1368 // generates code that does this, it is always safe to set.
1369 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1373 //===----------------------------------------------------------------------===//
1375 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1376 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1377 switch (MI->getOpcode()) {
1378 case ARM::t2MOVi32imm:
1379 assert(0 && "Should be lowered by thumb2it pass");
1381 case TargetInstrInfo::DBG_LABEL:
1382 case TargetInstrInfo::EH_LABEL:
1383 case TargetInstrInfo::GC_LABEL:
1386 case TargetInstrInfo::KILL:
1389 case TargetInstrInfo::INLINEASM:
1392 case TargetInstrInfo::IMPLICIT_DEF:
1393 printImplicitDef(MI);
1395 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1396 // This is a pseudo op for a label + instruction sequence, which looks like:
1399 // This adds the address of LPC0 to r0.
1402 // FIXME: MOVE TO SHARED PLACE.
1403 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1404 const char *Prefix = MAI->getPrivateGlobalPrefix();
1405 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1406 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1407 OutStreamer.EmitLabel(Label);
1410 // Form and emit tha dd.
1412 AddInst.setOpcode(ARM::ADDrr);
1413 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1414 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1415 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1416 printMCInst(&AddInst);
1419 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1420 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1421 /// in the function. The first operand is the ID# for this instruction, the
1422 /// second is the index into the MachineConstantPool that this is, the third
1423 /// is the size in bytes of this constant pool entry.
1424 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1425 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1429 const char *Prefix = MAI->getPrivateGlobalPrefix();
1430 MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
1431 Twine(getFunctionNumber())+
1432 "_"+ Twine(LabelId));
1433 OutStreamer.EmitLabel(Label);
1435 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1436 if (MCPE.isMachineConstantPoolEntry())
1437 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1439 EmitGlobalConstant(MCPE.Val.ConstVal);
1443 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1444 // This is a hack that lowers as a two instruction sequence.
1445 unsigned DstReg = MI->getOperand(0).getReg();
1446 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1448 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1449 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1453 TmpInst.setOpcode(ARM::MOVi);
1454 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1455 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1458 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1459 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1461 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1462 printMCInst(&TmpInst);
1468 TmpInst.setOpcode(ARM::ORRri);
1469 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1470 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1471 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1473 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1474 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1476 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1477 printMCInst(&TmpInst);
1481 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1482 // This is a hack that lowers as a two instruction sequence.
1483 unsigned DstReg = MI->getOperand(0).getReg();
1484 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1488 TmpInst.setOpcode(ARM::MOVi16);
1489 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1490 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1493 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1494 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1496 printMCInst(&TmpInst);
1502 TmpInst.setOpcode(ARM::MOVTi16);
1503 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1504 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1505 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1508 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1509 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1511 printMCInst(&TmpInst);
1519 MCInstLowering.Lower(MI, TmpInst);
1521 printMCInst(&TmpInst);
1524 //===----------------------------------------------------------------------===//
1525 // Target Registry Stuff
1526 //===----------------------------------------------------------------------===//
1528 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1529 unsigned SyntaxVariant,
1530 const MCAsmInfo &MAI,
1532 if (SyntaxVariant == 0)
1533 return new ARMInstPrinter(O, MAI, false);
1537 // Force static initialization.
1538 extern "C" void LLVMInitializeARMAsmPrinter() {
1539 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1540 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1542 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1543 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);