1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Assembly/Writer.h"
27 #include "llvm/CodeGen/AsmPrinter.h"
28 #include "llvm/CodeGen/DwarfWriter.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCSectionMachO.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Target/TargetRegistry.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallString.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringSet.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/FormattedStream.h"
50 #include "llvm/Support/Mangler.h"
51 #include "llvm/Support/MathExtras.h"
55 STATISTIC(EmittedInsts, "Number of machine instrs printed");
58 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
59 cl::desc("enable experimental asmprinter gunk in the arm backend"));
62 class ARMAsmPrinter : public AsmPrinter {
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when printing asm code for different targets.
66 const ARMSubtarget *Subtarget;
68 /// AFI - Keep a pointer to ARMFunctionInfo for the current
72 /// MCP - Keep a pointer to constantpool entries of the current
74 const MachineConstantPool *MCP;
77 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
78 const MCAsmInfo *T, bool V)
79 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
80 Subtarget = &TM.getSubtarget<ARMSubtarget>();
83 virtual const char *getPassName() const {
84 return "ARM Assembly Printer";
87 void printMCInst(const MCInst *MI) {
88 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
91 void printInstructionThroughMCStreamer(const MachineInstr *MI);
94 void printOperand(const MachineInstr *MI, int OpNum,
95 const char *Modifier = 0);
96 void printSOImmOperand(const MachineInstr *MI, int OpNum);
97 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
98 void printSORegOperand(const MachineInstr *MI, int OpNum);
99 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
104 const char *Modifier = 0);
105 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
108 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
109 const char *Modifier = 0);
110 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
112 void printThumbITMask(const MachineInstr *MI, int OpNum);
113 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
116 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
117 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
121 void printT2SOOperand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
128 void printPredicateOperand(const MachineInstr *MI, int OpNum);
129 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
130 void printPCLabel(const MachineInstr *MI, int OpNum);
131 void printRegisterList(const MachineInstr *MI, int OpNum);
132 void printCPInstOperand(const MachineInstr *MI, int OpNum,
133 const char *Modifier);
134 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
135 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
136 void printTBAddrMode(const MachineInstr *MI, int OpNum);
137 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
138 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
139 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
141 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
142 unsigned AsmVariant, const char *ExtraCode);
143 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
145 const char *ExtraCode);
147 void PrintGlobalVariable(const GlobalVariable* GVar);
148 void printInstruction(const MachineInstr *MI); // autogenerated.
149 static const char *getRegisterName(unsigned RegNo);
151 void printMachineInstruction(const MachineInstr *MI);
152 bool runOnMachineFunction(MachineFunction &F);
153 void EmitStartOfAsmFile(Module &M);
154 void EmitEndOfAsmFile(Module &M);
156 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
158 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
159 printDataDirective(MCPV->getType());
161 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
164 if (ACPV->isLSDA()) {
165 SmallString<16> LSDAName;
166 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
167 "_LSDA_" << getFunctionNumber();
168 Name = LSDAName.str();
169 } else if (ACPV->isBlockAddress()) {
170 Name = GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
171 } else if (ACPV->isGlobalValue()) {
172 GlobalValue *GV = ACPV->getGV();
173 bool isIndirect = Subtarget->isTargetDarwin() &&
174 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
176 Name = Mang->getMangledName(GV);
178 // FIXME: Remove this when Darwin transition to @GOT like syntax.
179 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
180 MCSymbol *Sym = OutContext.GetOrCreateSymbol(StringRef(Name));
182 MachineModuleInfoMachO &MMIMachO =
183 MMI->getObjFileInfo<MachineModuleInfoMachO>();
184 const MCSymbol *&StubSym =
185 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
186 MMIMachO.getGVStubEntry(Sym);
188 SmallString<128> NameStr;
189 Mang->getNameWithPrefix(NameStr, GV, false);
190 StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
194 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
195 Name = Mang->makeNameProper(ACPV->getSymbol());
199 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
200 if (ACPV->getPCAdjustment() != 0) {
201 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
202 << ACPV->getLabelId()
203 << "+" << (unsigned)ACPV->getPCAdjustment();
204 if (ACPV->mustAddCurrentAddress())
211 void getAnalysisUsage(AnalysisUsage &AU) const {
212 AsmPrinter::getAnalysisUsage(AU);
213 AU.setPreservesAll();
214 AU.addRequired<MachineModuleInfo>();
215 AU.addRequired<DwarfWriter>();
218 } // end of anonymous namespace
220 #include "ARMGenAsmWriter.inc"
222 /// runOnMachineFunction - This uses the printInstruction()
223 /// method to print assembly for each instruction.
225 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
228 AFI = MF.getInfo<ARMFunctionInfo>();
229 MCP = MF.getConstantPool();
231 SetupMachineFunction(MF);
234 // NOTE: we don't print out constant pools here, they are handled as
239 // Print out labels for the function.
240 const Function *F = MF.getFunction();
241 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
243 switch (F->getLinkage()) {
244 default: llvm_unreachable("Unknown linkage type!");
245 case Function::PrivateLinkage:
246 case Function::InternalLinkage:
248 case Function::ExternalLinkage:
249 O << "\t.globl\t" << CurrentFnName << "\n";
251 case Function::LinkerPrivateLinkage:
252 case Function::WeakAnyLinkage:
253 case Function::WeakODRLinkage:
254 case Function::LinkOnceAnyLinkage:
255 case Function::LinkOnceODRLinkage:
256 if (Subtarget->isTargetDarwin()) {
257 O << "\t.globl\t" << CurrentFnName << "\n";
258 O << "\t.weak_definition\t" << CurrentFnName << "\n";
260 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
265 printVisibility(CurrentFnName, F->getVisibility());
267 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
268 if (AFI->isThumbFunction()) {
269 EmitAlignment(FnAlign, F, AFI->getAlign());
270 O << "\t.code\t16\n";
271 O << "\t.thumb_func";
272 if (Subtarget->isTargetDarwin())
273 O << "\t" << CurrentFnName;
276 EmitAlignment(FnAlign, F);
279 O << CurrentFnName << ":\n";
280 // Emit pre-function debug information.
281 DW->BeginFunction(&MF);
283 if (Subtarget->isTargetDarwin()) {
284 // If the function is empty, then we need to emit *something*. Otherwise,
285 // the function's label might be associated with something that it wasn't
286 // meant to be associated with. We emit a noop in this situation.
287 MachineFunction::iterator I = MF.begin();
289 if (++I == MF.end() && MF.front().empty())
293 // Print out code for the function.
294 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
296 // Print a label for the basic block.
298 EmitBasicBlockStart(I);
300 // Print the assembly for the instruction.
301 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
303 printMachineInstruction(II);
306 if (MAI->hasDotTypeDotSizeDirective())
307 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
309 // Emit post-function debug information.
310 DW->EndFunction(&MF);
315 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
316 const char *Modifier) {
317 const MachineOperand &MO = MI->getOperand(OpNum);
318 switch (MO.getType()) {
320 assert(0 && "<unknown operand type>");
321 case MachineOperand::MO_Register: {
322 unsigned Reg = MO.getReg();
323 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
324 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
325 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
326 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
328 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
330 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
331 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
332 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
333 &ARM::DPR_VFP2RegClass);
334 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
336 O << getRegisterName(Reg);
340 case MachineOperand::MO_Immediate: {
341 int64_t Imm = MO.getImm();
344 if (strcmp(Modifier, "lo16") == 0)
346 else if (strcmp(Modifier, "hi16") == 0)
352 case MachineOperand::MO_MachineBasicBlock:
353 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
355 case MachineOperand::MO_GlobalAddress: {
356 bool isCallOp = Modifier && !strcmp(Modifier, "call");
357 GlobalValue *GV = MO.getGlobal();
358 O << Mang->getMangledName(GV);
360 printOffset(MO.getOffset());
362 if (isCallOp && Subtarget->isTargetELF() &&
363 TM.getRelocationModel() == Reloc::PIC_)
367 case MachineOperand::MO_ExternalSymbol: {
368 bool isCallOp = Modifier && !strcmp(Modifier, "call");
369 std::string Name = Mang->makeNameProper(MO.getSymbolName());
372 if (isCallOp && Subtarget->isTargetELF() &&
373 TM.getRelocationModel() == Reloc::PIC_)
377 case MachineOperand::MO_ConstantPoolIndex:
378 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
379 << '_' << MO.getIndex();
381 case MachineOperand::MO_JumpTableIndex:
382 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
383 << '_' << MO.getIndex();
388 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
389 const MCAsmInfo *MAI) {
390 // Break it up into two parts that make up a shifter immediate.
391 V = ARM_AM::getSOImmVal(V);
392 assert(V != -1 && "Not a valid so_imm value!");
394 unsigned Imm = ARM_AM::getSOImmValImm(V);
395 unsigned Rot = ARM_AM::getSOImmValRot(V);
397 // Print low-level immediate formation info, per
398 // A5.1.3: "Data-processing operands - Immediate".
400 O << "#" << Imm << ", " << Rot;
401 // Pretty printed version.
403 O.PadToColumn(MAI->getCommentColumn());
404 O << MAI->getCommentString() << ' ';
405 O << (int)ARM_AM::rotr32(Imm, Rot);
412 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
413 /// immediate in bits 0-7.
414 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
415 const MachineOperand &MO = MI->getOperand(OpNum);
416 assert(MO.isImm() && "Not a valid so_imm value!");
417 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
420 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
421 /// followed by an 'orr' to materialize.
422 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
423 const MachineOperand &MO = MI->getOperand(OpNum);
424 assert(MO.isImm() && "Not a valid so_imm value!");
425 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
426 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
427 printSOImm(O, V1, VerboseAsm, MAI);
429 printPredicateOperand(MI, 2);
435 printSOImm(O, V2, VerboseAsm, MAI);
438 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
439 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
441 // REG REG 0,SH_OPC - e.g. R5, ROR R3
442 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
443 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
444 const MachineOperand &MO1 = MI->getOperand(Op);
445 const MachineOperand &MO2 = MI->getOperand(Op+1);
446 const MachineOperand &MO3 = MI->getOperand(Op+2);
448 O << getRegisterName(MO1.getReg());
450 // Print the shift opc.
452 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
456 O << getRegisterName(MO2.getReg());
457 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
459 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
463 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
464 const MachineOperand &MO1 = MI->getOperand(Op);
465 const MachineOperand &MO2 = MI->getOperand(Op+1);
466 const MachineOperand &MO3 = MI->getOperand(Op+2);
468 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
469 printOperand(MI, Op);
473 O << "[" << getRegisterName(MO1.getReg());
476 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
478 << (char)ARM_AM::getAM2Op(MO3.getImm())
479 << ARM_AM::getAM2Offset(MO3.getImm());
485 << (char)ARM_AM::getAM2Op(MO3.getImm())
486 << getRegisterName(MO2.getReg());
488 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
490 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
495 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
496 const MachineOperand &MO1 = MI->getOperand(Op);
497 const MachineOperand &MO2 = MI->getOperand(Op+1);
500 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
501 assert(ImmOffs && "Malformed indexed load / store!");
503 << (char)ARM_AM::getAM2Op(MO2.getImm())
508 O << (char)ARM_AM::getAM2Op(MO2.getImm())
509 << getRegisterName(MO1.getReg());
511 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
513 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
517 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
518 const MachineOperand &MO1 = MI->getOperand(Op);
519 const MachineOperand &MO2 = MI->getOperand(Op+1);
520 const MachineOperand &MO3 = MI->getOperand(Op+2);
522 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
523 O << "[" << getRegisterName(MO1.getReg());
527 << (char)ARM_AM::getAM3Op(MO3.getImm())
528 << getRegisterName(MO2.getReg())
533 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
535 << (char)ARM_AM::getAM3Op(MO3.getImm())
540 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
541 const MachineOperand &MO1 = MI->getOperand(Op);
542 const MachineOperand &MO2 = MI->getOperand(Op+1);
545 O << (char)ARM_AM::getAM3Op(MO2.getImm())
546 << getRegisterName(MO1.getReg());
550 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
551 assert(ImmOffs && "Malformed indexed load / store!");
553 << (char)ARM_AM::getAM3Op(MO2.getImm())
557 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
558 const char *Modifier) {
559 const MachineOperand &MO1 = MI->getOperand(Op);
560 const MachineOperand &MO2 = MI->getOperand(Op+1);
561 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
562 if (Modifier && strcmp(Modifier, "submode") == 0) {
563 if (MO1.getReg() == ARM::SP) {
565 bool isLDM = (MI->getOpcode() == ARM::LDM ||
566 MI->getOpcode() == ARM::LDM_RET ||
567 MI->getOpcode() == ARM::t2LDM ||
568 MI->getOpcode() == ARM::t2LDM_RET);
569 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
571 O << ARM_AM::getAMSubModeStr(Mode);
572 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
573 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
574 if (Mode == ARM_AM::ia)
577 printOperand(MI, Op);
578 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
583 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
584 const char *Modifier) {
585 const MachineOperand &MO1 = MI->getOperand(Op);
586 const MachineOperand &MO2 = MI->getOperand(Op+1);
588 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
589 printOperand(MI, Op);
593 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
595 if (Modifier && strcmp(Modifier, "submode") == 0) {
596 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
597 if (MO1.getReg() == ARM::SP) {
598 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
599 MI->getOpcode() == ARM::FLDMS);
600 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
602 O << ARM_AM::getAMSubModeStr(Mode);
604 } else if (Modifier && strcmp(Modifier, "base") == 0) {
605 // Used for FSTM{D|S} and LSTM{D|S} operations.
606 O << getRegisterName(MO1.getReg());
607 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
612 O << "[" << getRegisterName(MO1.getReg());
614 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
616 << (char)ARM_AM::getAM5Op(MO2.getImm())
622 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
623 const MachineOperand &MO1 = MI->getOperand(Op);
624 const MachineOperand &MO2 = MI->getOperand(Op+1);
625 const MachineOperand &MO3 = MI->getOperand(Op+2);
627 // FIXME: No support yet for specifying alignment.
628 O << "[" << getRegisterName(MO1.getReg()) << "]";
630 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
631 if (MO2.getReg() == 0)
634 O << ", " << getRegisterName(MO2.getReg());
638 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
639 const char *Modifier) {
640 if (Modifier && strcmp(Modifier, "label") == 0) {
641 printPCLabel(MI, Op+1);
645 const MachineOperand &MO1 = MI->getOperand(Op);
646 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
647 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
651 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
652 const MachineOperand &MO = MI->getOperand(Op);
653 uint32_t v = ~MO.getImm();
654 int32_t lsb = CountTrailingZeros_32(v);
655 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
656 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
657 O << "#" << lsb << ", #" << width;
660 //===--------------------------------------------------------------------===//
663 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
664 // (3 - the number of trailing zeros) is the number of then / else.
665 unsigned Mask = MI->getOperand(Op).getImm();
666 unsigned NumTZ = CountTrailingZeros_32(Mask);
667 assert(NumTZ <= 3 && "Invalid IT mask!");
668 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
669 bool T = (Mask & (1 << Pos)) == 0;
678 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
679 const MachineOperand &MO1 = MI->getOperand(Op);
680 const MachineOperand &MO2 = MI->getOperand(Op+1);
681 O << "[" << getRegisterName(MO1.getReg());
682 O << ", " << getRegisterName(MO2.getReg()) << "]";
686 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
688 const MachineOperand &MO1 = MI->getOperand(Op);
689 const MachineOperand &MO2 = MI->getOperand(Op+1);
690 const MachineOperand &MO3 = MI->getOperand(Op+2);
692 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
693 printOperand(MI, Op);
697 O << "[" << getRegisterName(MO1.getReg());
699 O << ", " << getRegisterName(MO3.getReg());
700 else if (unsigned ImmOffs = MO2.getImm()) {
701 O << ", #" << ImmOffs;
709 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
710 printThumbAddrModeRI5Operand(MI, Op, 1);
713 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
714 printThumbAddrModeRI5Operand(MI, Op, 2);
717 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
718 printThumbAddrModeRI5Operand(MI, Op, 4);
721 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
722 const MachineOperand &MO1 = MI->getOperand(Op);
723 const MachineOperand &MO2 = MI->getOperand(Op+1);
724 O << "[" << getRegisterName(MO1.getReg());
725 if (unsigned ImmOffs = MO2.getImm())
726 O << ", #" << ImmOffs << " * 4";
730 //===--------------------------------------------------------------------===//
732 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
733 // register with shift forms.
735 // REG IMM, SH_OPC - e.g. R5, LSL #3
736 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
737 const MachineOperand &MO1 = MI->getOperand(OpNum);
738 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
740 unsigned Reg = MO1.getReg();
741 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
742 O << getRegisterName(Reg);
744 // Print the shift opc.
746 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
749 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
750 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
753 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
755 const MachineOperand &MO1 = MI->getOperand(OpNum);
756 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
758 O << "[" << getRegisterName(MO1.getReg());
760 unsigned OffImm = MO2.getImm();
761 if (OffImm) // Don't print +0.
762 O << ", #+" << OffImm;
766 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
768 const MachineOperand &MO1 = MI->getOperand(OpNum);
769 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
771 O << "[" << getRegisterName(MO1.getReg());
773 int32_t OffImm = (int32_t)MO2.getImm();
776 O << ", #-" << -OffImm;
778 O << ", #+" << OffImm;
782 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
784 const MachineOperand &MO1 = MI->getOperand(OpNum);
785 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
787 O << "[" << getRegisterName(MO1.getReg());
789 int32_t OffImm = (int32_t)MO2.getImm() / 4;
792 O << ", #-" << -OffImm << " * 4";
794 O << ", #+" << OffImm << " * 4";
798 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
800 const MachineOperand &MO1 = MI->getOperand(OpNum);
801 int32_t OffImm = (int32_t)MO1.getImm();
804 O << "#-" << -OffImm;
809 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
811 const MachineOperand &MO1 = MI->getOperand(OpNum);
812 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
813 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
815 O << "[" << getRegisterName(MO1.getReg());
817 assert(MO2.getReg() && "Invalid so_reg load / store address!");
818 O << ", " << getRegisterName(MO2.getReg());
820 unsigned ShAmt = MO3.getImm();
822 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
823 O << ", lsl #" << ShAmt;
829 //===--------------------------------------------------------------------===//
831 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
832 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
834 O << ARMCondCodeToString(CC);
837 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
838 unsigned Reg = MI->getOperand(OpNum).getReg();
840 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
845 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
846 int Id = (int)MI->getOperand(OpNum).getImm();
847 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
850 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
852 // Always skip the first operand, it's the optional (and implicit writeback).
853 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
854 if (MI->getOperand(i).isImplicit())
856 if ((int)i != OpNum+1) O << ", ";
862 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
863 const char *Modifier) {
864 assert(Modifier && "This operand only works with a modifier!");
865 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
867 if (!strcmp(Modifier, "label")) {
868 unsigned ID = MI->getOperand(OpNum).getImm();
869 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
870 << '_' << ID << ":\n";
872 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
873 unsigned CPI = MI->getOperand(OpNum).getIndex();
875 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
877 if (MCPE.isMachineConstantPoolEntry()) {
878 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
880 EmitGlobalConstant(MCPE.Val.ConstVal);
885 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
886 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
888 const MachineOperand &MO1 = MI->getOperand(OpNum);
889 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
890 unsigned JTI = MO1.getIndex();
891 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
892 << '_' << JTI << '_' << MO2.getImm() << ":\n";
894 const char *JTEntryDirective = MAI->getData32bitsDirective();
896 const MachineFunction *MF = MI->getParent()->getParent();
897 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
898 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
899 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
900 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
901 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
902 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
903 MachineBasicBlock *MBB = JTBBs[i];
904 bool isNew = JTSets.insert(MBB);
907 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
909 O << JTEntryDirective << ' ';
911 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
912 << '_' << JTI << '_' << MO2.getImm()
913 << "_set_" << MBB->getNumber();
914 else if (TM.getRelocationModel() == Reloc::PIC_) {
915 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
916 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
917 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
919 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
926 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
927 const MachineOperand &MO1 = MI->getOperand(OpNum);
928 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
929 unsigned JTI = MO1.getIndex();
930 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
931 << '_' << JTI << '_' << MO2.getImm() << ":\n";
933 const MachineFunction *MF = MI->getParent()->getParent();
934 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
935 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
936 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
937 bool ByteOffset = false, HalfWordOffset = false;
938 if (MI->getOpcode() == ARM::t2TBB)
940 else if (MI->getOpcode() == ARM::t2TBH)
941 HalfWordOffset = true;
943 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
944 MachineBasicBlock *MBB = JTBBs[i];
946 O << MAI->getData8bitsDirective();
947 else if (HalfWordOffset)
948 O << MAI->getData16bitsDirective();
949 if (ByteOffset || HalfWordOffset) {
951 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
952 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
953 << '_' << JTI << '_' << MO2.getImm() << ")/2";
956 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
962 // Make sure the instruction that follows TBB is 2-byte aligned.
963 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
964 if (ByteOffset && (JTBBs.size() & 1)) {
970 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
971 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
972 if (MI->getOpcode() == ARM::t2TBH)
977 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
978 O << MI->getOperand(OpNum).getImm();
981 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
982 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
983 O << '#' << ARM::getVFPf32Imm(FP->getValueAPF());
985 O.PadToColumn(MAI->getCommentColumn());
986 O << MAI->getCommentString() << ' ';
987 WriteAsOperand(O, FP, /*PrintType=*/false);
991 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
992 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
993 O << '#' << ARM::getVFPf64Imm(FP->getValueAPF());
995 O.PadToColumn(MAI->getCommentColumn());
996 O << MAI->getCommentString() << ' ';
997 WriteAsOperand(O, FP, /*PrintType=*/false);
1001 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1002 unsigned AsmVariant, const char *ExtraCode){
1003 // Does this asm operand have a single letter operand modifier?
1004 if (ExtraCode && ExtraCode[0]) {
1005 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1007 switch (ExtraCode[0]) {
1008 default: return true; // Unknown modifier.
1009 case 'a': // Print as a memory address.
1010 if (MI->getOperand(OpNum).isReg()) {
1011 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1015 case 'c': // Don't print "#" before an immediate operand.
1016 if (!MI->getOperand(OpNum).isImm())
1018 printNoHashImmediate(MI, OpNum);
1020 case 'P': // Print a VFP double precision register.
1021 printOperand(MI, OpNum);
1024 if (TM.getTargetData()->isLittleEndian())
1028 if (TM.getTargetData()->isBigEndian())
1031 case 'H': // Write second word of DI / DF reference.
1032 // Verify that this operand has two consecutive registers.
1033 if (!MI->getOperand(OpNum).isReg() ||
1034 OpNum+1 == MI->getNumOperands() ||
1035 !MI->getOperand(OpNum+1).isReg())
1037 ++OpNum; // Return the high-part.
1041 printOperand(MI, OpNum);
1045 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1046 unsigned OpNum, unsigned AsmVariant,
1047 const char *ExtraCode) {
1048 if (ExtraCode && ExtraCode[0])
1049 return true; // Unknown modifier.
1051 const MachineOperand &MO = MI->getOperand(OpNum);
1052 assert(MO.isReg() && "unexpected inline asm memory operand");
1053 O << "[" << getRegisterName(MO.getReg()) << "]";
1057 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1060 // Call the autogenerated instruction printer routines.
1061 processDebugLoc(MI, true);
1064 printInstructionThroughMCStreamer(MI);
1066 int Opc = MI->getOpcode();
1067 if (Opc == ARM::CONSTPOOL_ENTRY)
1070 printInstruction(MI);
1073 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1076 processDebugLoc(MI, false);
1079 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1080 if (Subtarget->isTargetDarwin()) {
1081 Reloc::Model RelocM = TM.getRelocationModel();
1082 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1083 // Declare all the text sections up front (before the DWARF sections
1084 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1085 // them together at the beginning of the object file. This helps
1086 // avoid out-of-range branches that are due a fundamental limitation of
1087 // the way symbol offsets are encoded with the current Darwin ARM
1089 TargetLoweringObjectFileMachO &TLOFMacho =
1090 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1091 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1092 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1093 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1094 if (RelocM == Reloc::DynamicNoPIC) {
1095 const MCSection *sect =
1096 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1097 MCSectionMachO::S_SYMBOL_STUBS,
1098 12, SectionKind::getText());
1099 OutStreamer.SwitchSection(sect);
1101 const MCSection *sect =
1102 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1103 MCSectionMachO::S_SYMBOL_STUBS,
1104 16, SectionKind::getText());
1105 OutStreamer.SwitchSection(sect);
1110 // Use unified assembler syntax mode for Thumb.
1111 if (Subtarget->isThumb())
1112 O << "\t.syntax unified\n";
1114 // Emit ARM Build Attributes
1115 if (Subtarget->isTargetELF()) {
1117 std::string CPUString = Subtarget->getCPUString();
1118 if (CPUString != "generic")
1119 O << "\t.cpu " << CPUString << '\n';
1121 // FIXME: Emit FPU type
1122 if (Subtarget->hasVFP2())
1123 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1125 // Signal various FP modes.
1127 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1128 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1130 if (FiniteOnlyFPMath())
1131 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1133 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1135 // 8-bytes alignment stuff.
1136 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1137 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1139 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1140 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1141 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1142 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1144 // FIXME: Should we signal R9 usage?
1148 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1149 const TargetData *TD = TM.getTargetData();
1151 if (!GVar->hasInitializer()) // External global require no code
1154 // Check to see if this is a special global used by LLVM, if so, emit it.
1156 if (EmitSpecialLLVMGlobal(GVar)) {
1157 if (Subtarget->isTargetDarwin() &&
1158 TM.getRelocationModel() == Reloc::Static) {
1159 if (GVar->getName() == "llvm.global_ctors")
1160 O << ".reference .constructors_used\n";
1161 else if (GVar->getName() == "llvm.global_dtors")
1162 O << ".reference .destructors_used\n";
1167 std::string name = Mang->getMangledName(GVar);
1168 Constant *C = GVar->getInitializer();
1169 const Type *Type = C->getType();
1170 unsigned Size = TD->getTypeAllocSize(Type);
1171 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1172 bool isDarwin = Subtarget->isTargetDarwin();
1174 printVisibility(name, GVar->getVisibility());
1176 if (Subtarget->isTargetELF())
1177 O << "\t.type " << name << ",%object\n";
1179 const MCSection *TheSection =
1180 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1181 OutStreamer.SwitchSection(TheSection);
1183 // FIXME: get this stuff from section kind flags.
1184 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1185 // Don't put things that should go in the cstring section into "comm".
1186 !TheSection->getKind().isMergeableCString()) {
1187 if (GVar->hasExternalLinkage()) {
1188 if (const char *Directive = MAI->getZeroFillDirective()) {
1189 O << "\t.globl\t" << name << "\n";
1190 O << Directive << "__DATA, __common, " << name << ", "
1191 << Size << ", " << Align << "\n";
1196 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1197 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1200 if (GVar->hasLocalLinkage()) {
1201 O << MAI->getLCOMMDirective() << name << "," << Size
1203 } else if (GVar->hasCommonLinkage()) {
1204 O << MAI->getCOMMDirective() << name << "," << Size
1207 OutStreamer.SwitchSection(TheSection);
1208 O << "\t.globl " << name << '\n'
1209 << MAI->getWeakDefDirective() << name << '\n';
1210 EmitAlignment(Align, GVar);
1213 O.PadToColumn(MAI->getCommentColumn());
1214 O << MAI->getCommentString() << ' ';
1215 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1218 EmitGlobalConstant(C);
1221 } else if (MAI->getLCOMMDirective() != NULL) {
1222 if (GVar->hasLocalLinkage()) {
1223 O << MAI->getLCOMMDirective() << name << "," << Size;
1225 O << MAI->getCOMMDirective() << name << "," << Size;
1226 if (MAI->getCOMMDirectiveTakesAlignment())
1227 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1230 if (GVar->hasLocalLinkage())
1231 O << "\t.local\t" << name << "\n";
1232 O << MAI->getCOMMDirective() << name << "," << Size;
1233 if (MAI->getCOMMDirectiveTakesAlignment())
1234 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1237 O.PadToColumn(MAI->getCommentColumn());
1238 O << MAI->getCommentString() << ' ';
1239 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1246 switch (GVar->getLinkage()) {
1247 case GlobalValue::CommonLinkage:
1248 case GlobalValue::LinkOnceAnyLinkage:
1249 case GlobalValue::LinkOnceODRLinkage:
1250 case GlobalValue::WeakAnyLinkage:
1251 case GlobalValue::WeakODRLinkage:
1252 case GlobalValue::LinkerPrivateLinkage:
1254 O << "\t.globl " << name << "\n"
1255 << "\t.weak_definition " << name << "\n";
1257 O << "\t.weak " << name << "\n";
1260 case GlobalValue::AppendingLinkage:
1261 // FIXME: appending linkage variables should go into a section of
1262 // their name or something. For now, just emit them as external.
1263 case GlobalValue::ExternalLinkage:
1264 O << "\t.globl " << name << "\n";
1266 case GlobalValue::PrivateLinkage:
1267 case GlobalValue::InternalLinkage:
1270 llvm_unreachable("Unknown linkage type!");
1273 EmitAlignment(Align, GVar);
1276 O.PadToColumn(MAI->getCommentColumn());
1277 O << MAI->getCommentString() << ' ';
1278 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1281 if (MAI->hasDotTypeDotSizeDirective())
1282 O << "\t.size " << name << ", " << Size << "\n";
1284 EmitGlobalConstant(C);
1289 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1290 if (Subtarget->isTargetDarwin()) {
1291 // All darwin targets use mach-o.
1292 TargetLoweringObjectFileMachO &TLOFMacho =
1293 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1294 MachineModuleInfoMachO &MMIMacho =
1295 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1299 // Output non-lazy-pointers for external and common global variables.
1300 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1302 if (!Stubs.empty()) {
1303 // Switch with ".non_lazy_symbol_pointer" directive.
1304 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1306 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1307 Stubs[i].first->print(O, MAI);
1308 O << ":\n\t.indirect_symbol ";
1309 Stubs[i].second->print(O, MAI);
1310 O << "\n\t.long\t0\n";
1314 Stubs = MMIMacho.GetHiddenGVStubList();
1315 if (!Stubs.empty()) {
1316 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1318 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1319 Stubs[i].first->print(O, MAI);
1321 Stubs[i].second->print(O, MAI);
1326 // Funny Darwin hack: This flag tells the linker that no global symbols
1327 // contain code that falls through to other global symbols (e.g. the obvious
1328 // implementation of multiple entry points). If this doesn't occur, the
1329 // linker can safely perform dead code stripping. Since LLVM never
1330 // generates code that does this, it is always safe to set.
1331 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1335 //===----------------------------------------------------------------------===//
1337 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1338 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1339 switch (MI->getOpcode()) {
1340 case ARM::t2MOVi32imm:
1341 assert(0 && "Should be lowered by thumb2it pass");
1343 case TargetInstrInfo::DBG_LABEL:
1344 case TargetInstrInfo::EH_LABEL:
1345 case TargetInstrInfo::GC_LABEL:
1348 case TargetInstrInfo::KILL:
1351 case TargetInstrInfo::INLINEASM:
1355 case TargetInstrInfo::IMPLICIT_DEF:
1356 printImplicitDef(MI);
1358 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1359 // This is a pseudo op for a label + instruction sequence, which looks like:
1362 // This adds the address of LPC0 to r0.
1365 // FIXME: MOVE TO SHARED PLACE.
1366 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1367 const char *Prefix = MAI->getPrivateGlobalPrefix();
1368 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)+"PC"+Twine(Id));
1369 OutStreamer.EmitLabel(Label);
1372 // Form and emit tha dd.
1374 AddInst.setOpcode(ARM::ADDrr);
1375 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1376 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1377 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1378 printMCInst(&AddInst);
1381 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1382 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1383 /// in the function. The first operand is the ID# for this instruction, the
1384 /// second is the index into the MachineConstantPool that this is, the third
1385 /// is the size in bytes of this constant pool entry.
1386 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1387 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1391 const char *Prefix = MAI->getPrivateGlobalPrefix();
1392 MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
1393 Twine(getFunctionNumber())+
1394 "_"+ Twine(LabelId));
1395 OutStreamer.EmitLabel(Label);
1397 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1398 if (MCPE.isMachineConstantPoolEntry())
1399 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1401 EmitGlobalConstant(MCPE.Val.ConstVal);
1405 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1406 // This is a hack that lowers as a two instruction sequence.
1407 unsigned DstReg = MI->getOperand(0).getReg();
1408 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1410 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1411 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1415 TmpInst.setOpcode(ARM::MOVi);
1416 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1417 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1420 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1421 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1423 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1424 printMCInst(&TmpInst);
1430 TmpInst.setOpcode(ARM::ORRri);
1431 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1432 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1433 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1435 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1436 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1438 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1439 printMCInst(&TmpInst);
1443 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1444 // This is a hack that lowers as a two instruction sequence.
1445 unsigned DstReg = MI->getOperand(0).getReg();
1446 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1450 TmpInst.setOpcode(ARM::MOVi16);
1451 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1452 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1455 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1456 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1458 printMCInst(&TmpInst);
1464 TmpInst.setOpcode(ARM::MOVTi16);
1465 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1466 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1467 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1470 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1471 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1473 printMCInst(&TmpInst);
1481 MCInstLowering.Lower(MI, TmpInst);
1483 printMCInst(&TmpInst);
1486 //===----------------------------------------------------------------------===//
1487 // Target Registry Stuff
1488 //===----------------------------------------------------------------------===//
1490 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1491 unsigned SyntaxVariant,
1492 const MCAsmInfo &MAI,
1494 if (SyntaxVariant == 0)
1495 return new ARMInstPrinter(O, MAI, false);
1499 // Force static initialization.
1500 extern "C" void LLVMInitializeARMAsmPrinter() {
1501 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1502 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1504 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1505 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);