1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Assembly/Writer.h"
27 #include "llvm/CodeGen/AsmPrinter.h"
28 #include "llvm/CodeGen/DwarfWriter.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCSectionMachO.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Target/TargetRegistry.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallString.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/StringSet.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/FormattedStream.h"
51 #include "llvm/Support/Mangler.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbITMask(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
136 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
137 void printTBAddrMode(const MachineInstr *MI, int OpNum);
138 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
139 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
140 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
142 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
143 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
145 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
146 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
148 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
149 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
151 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
152 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
155 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
156 unsigned AsmVariant, const char *ExtraCode);
157 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
159 const char *ExtraCode);
161 void PrintGlobalVariable(const GlobalVariable* GVar);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
172 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
173 printDataDirective(MCPV->getType());
175 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
178 if (ACPV->isLSDA()) {
179 SmallString<16> LSDAName;
180 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
181 "_LSDA_" << getFunctionNumber();
182 Name = LSDAName.str();
183 } else if (ACPV->isBlockAddress()) {
184 Name = GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
185 } else if (ACPV->isGlobalValue()) {
186 GlobalValue *GV = ACPV->getGV();
187 bool isIndirect = Subtarget->isTargetDarwin() &&
188 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
190 Name = Mang->getMangledName(GV);
192 // FIXME: Remove this when Darwin transition to @GOT like syntax.
193 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
194 MCSymbol *Sym = OutContext.GetOrCreateSymbol(StringRef(Name));
196 MachineModuleInfoMachO &MMIMachO =
197 MMI->getObjFileInfo<MachineModuleInfoMachO>();
198 const MCSymbol *&StubSym =
199 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
200 MMIMachO.getGVStubEntry(Sym);
202 SmallString<128> NameStr;
203 Mang->getNameWithPrefix(NameStr, GV, false);
204 StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
208 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
209 Name = Mang->makeNameProper(ACPV->getSymbol());
213 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
214 if (ACPV->getPCAdjustment() != 0) {
215 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
216 << getFunctionNumber() << "_" << ACPV->getLabelId()
217 << "+" << (unsigned)ACPV->getPCAdjustment();
218 if (ACPV->mustAddCurrentAddress())
225 void getAnalysisUsage(AnalysisUsage &AU) const {
226 AsmPrinter::getAnalysisUsage(AU);
227 AU.setPreservesAll();
228 AU.addRequired<MachineModuleInfo>();
229 AU.addRequired<DwarfWriter>();
232 } // end of anonymous namespace
234 #include "ARMGenAsmWriter.inc"
236 /// runOnMachineFunction - This uses the printInstruction()
237 /// method to print assembly for each instruction.
239 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
242 AFI = MF.getInfo<ARMFunctionInfo>();
243 MCP = MF.getConstantPool();
245 SetupMachineFunction(MF);
248 // NOTE: we don't print out constant pools here, they are handled as
253 // Print out labels for the function.
254 const Function *F = MF.getFunction();
255 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
257 switch (F->getLinkage()) {
258 default: llvm_unreachable("Unknown linkage type!");
259 case Function::PrivateLinkage:
260 case Function::InternalLinkage:
262 case Function::ExternalLinkage:
263 O << "\t.globl\t" << CurrentFnName << "\n";
265 case Function::LinkerPrivateLinkage:
266 case Function::WeakAnyLinkage:
267 case Function::WeakODRLinkage:
268 case Function::LinkOnceAnyLinkage:
269 case Function::LinkOnceODRLinkage:
270 if (Subtarget->isTargetDarwin()) {
271 O << "\t.globl\t" << CurrentFnName << "\n";
272 O << "\t.weak_definition\t" << CurrentFnName << "\n";
274 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
279 printVisibility(CurrentFnName, F->getVisibility());
281 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
282 if (AFI->isThumbFunction()) {
283 EmitAlignment(FnAlign, F, AFI->getAlign());
284 O << "\t.code\t16\n";
285 O << "\t.thumb_func";
286 if (Subtarget->isTargetDarwin())
287 O << "\t" << CurrentFnName;
290 EmitAlignment(FnAlign, F);
293 O << CurrentFnName << ":\n";
294 // Emit pre-function debug information.
295 DW->BeginFunction(&MF);
297 if (Subtarget->isTargetDarwin()) {
298 // If the function is empty, then we need to emit *something*. Otherwise,
299 // the function's label might be associated with something that it wasn't
300 // meant to be associated with. We emit a noop in this situation.
301 MachineFunction::iterator I = MF.begin();
303 if (++I == MF.end() && MF.front().empty())
307 // Print out code for the function.
308 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
310 // Print a label for the basic block.
312 EmitBasicBlockStart(I);
314 // Print the assembly for the instruction.
315 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
317 printMachineInstruction(II);
320 if (MAI->hasDotTypeDotSizeDirective())
321 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
323 // Emit post-function debug information.
324 DW->EndFunction(&MF);
329 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
330 const char *Modifier) {
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 switch (MO.getType()) {
334 assert(0 && "<unknown operand type>");
335 case MachineOperand::MO_Register: {
336 unsigned Reg = MO.getReg();
337 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
338 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
339 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
340 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
342 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
344 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
345 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
346 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
347 &ARM::DPR_VFP2RegClass);
348 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
350 assert(!MO.getSubReg() && "Subregs should be eliminated!");
351 O << getRegisterName(Reg);
355 case MachineOperand::MO_Immediate: {
356 int64_t Imm = MO.getImm();
359 if (strcmp(Modifier, "lo16") == 0)
361 else if (strcmp(Modifier, "hi16") == 0)
367 case MachineOperand::MO_MachineBasicBlock:
368 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
370 case MachineOperand::MO_GlobalAddress: {
371 bool isCallOp = Modifier && !strcmp(Modifier, "call");
372 GlobalValue *GV = MO.getGlobal();
373 O << Mang->getMangledName(GV);
375 printOffset(MO.getOffset());
377 if (isCallOp && Subtarget->isTargetELF() &&
378 TM.getRelocationModel() == Reloc::PIC_)
382 case MachineOperand::MO_ExternalSymbol: {
383 bool isCallOp = Modifier && !strcmp(Modifier, "call");
384 std::string Name = Mang->makeNameProper(MO.getSymbolName());
387 if (isCallOp && Subtarget->isTargetELF() &&
388 TM.getRelocationModel() == Reloc::PIC_)
392 case MachineOperand::MO_ConstantPoolIndex:
393 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
394 << '_' << MO.getIndex();
396 case MachineOperand::MO_JumpTableIndex:
397 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
398 << '_' << MO.getIndex();
403 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
404 const MCAsmInfo *MAI) {
405 // Break it up into two parts that make up a shifter immediate.
406 V = ARM_AM::getSOImmVal(V);
407 assert(V != -1 && "Not a valid so_imm value!");
409 unsigned Imm = ARM_AM::getSOImmValImm(V);
410 unsigned Rot = ARM_AM::getSOImmValRot(V);
412 // Print low-level immediate formation info, per
413 // A5.1.3: "Data-processing operands - Immediate".
415 O << "#" << Imm << ", " << Rot;
416 // Pretty printed version.
418 O.PadToColumn(MAI->getCommentColumn());
419 O << MAI->getCommentString() << ' ';
420 O << (int)ARM_AM::rotr32(Imm, Rot);
427 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
428 /// immediate in bits 0-7.
429 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
430 const MachineOperand &MO = MI->getOperand(OpNum);
431 assert(MO.isImm() && "Not a valid so_imm value!");
432 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
435 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
436 /// followed by an 'orr' to materialize.
437 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
438 const MachineOperand &MO = MI->getOperand(OpNum);
439 assert(MO.isImm() && "Not a valid so_imm value!");
440 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
441 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
442 printSOImm(O, V1, VerboseAsm, MAI);
444 printPredicateOperand(MI, 2);
450 printSOImm(O, V2, VerboseAsm, MAI);
453 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
454 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
456 // REG REG 0,SH_OPC - e.g. R5, ROR R3
457 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
458 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
459 const MachineOperand &MO1 = MI->getOperand(Op);
460 const MachineOperand &MO2 = MI->getOperand(Op+1);
461 const MachineOperand &MO3 = MI->getOperand(Op+2);
463 O << getRegisterName(MO1.getReg());
465 // Print the shift opc.
467 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
471 O << getRegisterName(MO2.getReg());
472 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
474 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
478 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
479 const MachineOperand &MO1 = MI->getOperand(Op);
480 const MachineOperand &MO2 = MI->getOperand(Op+1);
481 const MachineOperand &MO3 = MI->getOperand(Op+2);
483 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
484 printOperand(MI, Op);
488 O << "[" << getRegisterName(MO1.getReg());
491 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
493 << (char)ARM_AM::getAM2Op(MO3.getImm())
494 << ARM_AM::getAM2Offset(MO3.getImm());
500 << (char)ARM_AM::getAM2Op(MO3.getImm())
501 << getRegisterName(MO2.getReg());
503 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
505 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
510 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
511 const MachineOperand &MO1 = MI->getOperand(Op);
512 const MachineOperand &MO2 = MI->getOperand(Op+1);
515 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
516 assert(ImmOffs && "Malformed indexed load / store!");
518 << (char)ARM_AM::getAM2Op(MO2.getImm())
523 O << (char)ARM_AM::getAM2Op(MO2.getImm())
524 << getRegisterName(MO1.getReg());
526 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
528 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
532 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
533 const MachineOperand &MO1 = MI->getOperand(Op);
534 const MachineOperand &MO2 = MI->getOperand(Op+1);
535 const MachineOperand &MO3 = MI->getOperand(Op+2);
537 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
538 O << "[" << getRegisterName(MO1.getReg());
542 << (char)ARM_AM::getAM3Op(MO3.getImm())
543 << getRegisterName(MO2.getReg())
548 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
550 << (char)ARM_AM::getAM3Op(MO3.getImm())
555 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
556 const MachineOperand &MO1 = MI->getOperand(Op);
557 const MachineOperand &MO2 = MI->getOperand(Op+1);
560 O << (char)ARM_AM::getAM3Op(MO2.getImm())
561 << getRegisterName(MO1.getReg());
565 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
566 assert(ImmOffs && "Malformed indexed load / store!");
568 << (char)ARM_AM::getAM3Op(MO2.getImm())
572 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
573 const char *Modifier) {
574 const MachineOperand &MO1 = MI->getOperand(Op);
575 const MachineOperand &MO2 = MI->getOperand(Op+1);
576 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
577 if (Modifier && strcmp(Modifier, "submode") == 0) {
578 if (MO1.getReg() == ARM::SP) {
580 bool isLDM = (MI->getOpcode() == ARM::LDM ||
581 MI->getOpcode() == ARM::LDM_RET ||
582 MI->getOpcode() == ARM::t2LDM ||
583 MI->getOpcode() == ARM::t2LDM_RET);
584 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
586 O << ARM_AM::getAMSubModeStr(Mode);
587 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
588 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
589 if (Mode == ARM_AM::ia)
592 printOperand(MI, Op);
593 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
598 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
599 const char *Modifier) {
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
604 printOperand(MI, Op);
608 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
610 if (Modifier && strcmp(Modifier, "submode") == 0) {
611 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
612 if (MO1.getReg() == ARM::SP) {
613 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
614 MI->getOpcode() == ARM::FLDMS);
615 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
617 O << ARM_AM::getAMSubModeStr(Mode);
619 } else if (Modifier && strcmp(Modifier, "base") == 0) {
620 // Used for FSTM{D|S} and LSTM{D|S} operations.
621 O << getRegisterName(MO1.getReg());
622 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
627 O << "[" << getRegisterName(MO1.getReg());
629 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
631 << (char)ARM_AM::getAM5Op(MO2.getImm())
637 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
638 const MachineOperand &MO1 = MI->getOperand(Op);
639 const MachineOperand &MO2 = MI->getOperand(Op+1);
640 const MachineOperand &MO3 = MI->getOperand(Op+2);
642 // FIXME: No support yet for specifying alignment.
643 O << "[" << getRegisterName(MO1.getReg()) << "]";
645 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
646 if (MO2.getReg() == 0)
649 O << ", " << getRegisterName(MO2.getReg());
653 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
654 const char *Modifier) {
655 if (Modifier && strcmp(Modifier, "label") == 0) {
656 printPCLabel(MI, Op+1);
660 const MachineOperand &MO1 = MI->getOperand(Op);
661 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
662 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
666 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
667 const MachineOperand &MO = MI->getOperand(Op);
668 uint32_t v = ~MO.getImm();
669 int32_t lsb = CountTrailingZeros_32(v);
670 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
671 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
672 O << "#" << lsb << ", #" << width;
675 //===--------------------------------------------------------------------===//
678 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
679 // (3 - the number of trailing zeros) is the number of then / else.
680 unsigned Mask = MI->getOperand(Op).getImm();
681 unsigned NumTZ = CountTrailingZeros_32(Mask);
682 assert(NumTZ <= 3 && "Invalid IT mask!");
683 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
684 bool T = (Mask & (1 << Pos)) == 0;
693 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
694 const MachineOperand &MO1 = MI->getOperand(Op);
695 const MachineOperand &MO2 = MI->getOperand(Op+1);
696 O << "[" << getRegisterName(MO1.getReg());
697 O << ", " << getRegisterName(MO2.getReg()) << "]";
701 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
703 const MachineOperand &MO1 = MI->getOperand(Op);
704 const MachineOperand &MO2 = MI->getOperand(Op+1);
705 const MachineOperand &MO3 = MI->getOperand(Op+2);
707 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
708 printOperand(MI, Op);
712 O << "[" << getRegisterName(MO1.getReg());
714 O << ", " << getRegisterName(MO3.getReg());
715 else if (unsigned ImmOffs = MO2.getImm()) {
716 O << ", #" << ImmOffs;
724 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
725 printThumbAddrModeRI5Operand(MI, Op, 1);
728 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
729 printThumbAddrModeRI5Operand(MI, Op, 2);
732 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
733 printThumbAddrModeRI5Operand(MI, Op, 4);
736 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
737 const MachineOperand &MO1 = MI->getOperand(Op);
738 const MachineOperand &MO2 = MI->getOperand(Op+1);
739 O << "[" << getRegisterName(MO1.getReg());
740 if (unsigned ImmOffs = MO2.getImm())
741 O << ", #" << ImmOffs << " * 4";
745 //===--------------------------------------------------------------------===//
747 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
748 // register with shift forms.
750 // REG IMM, SH_OPC - e.g. R5, LSL #3
751 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
752 const MachineOperand &MO1 = MI->getOperand(OpNum);
753 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
755 unsigned Reg = MO1.getReg();
756 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
757 O << getRegisterName(Reg);
759 // Print the shift opc.
761 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
764 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
765 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
768 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
770 const MachineOperand &MO1 = MI->getOperand(OpNum);
771 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
773 O << "[" << getRegisterName(MO1.getReg());
775 unsigned OffImm = MO2.getImm();
776 if (OffImm) // Don't print +0.
777 O << ", #+" << OffImm;
781 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
783 const MachineOperand &MO1 = MI->getOperand(OpNum);
784 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
786 O << "[" << getRegisterName(MO1.getReg());
788 int32_t OffImm = (int32_t)MO2.getImm();
791 O << ", #-" << -OffImm;
793 O << ", #+" << OffImm;
797 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
799 const MachineOperand &MO1 = MI->getOperand(OpNum);
800 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
802 O << "[" << getRegisterName(MO1.getReg());
804 int32_t OffImm = (int32_t)MO2.getImm() / 4;
807 O << ", #-" << -OffImm << " * 4";
809 O << ", #+" << OffImm << " * 4";
813 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
815 const MachineOperand &MO1 = MI->getOperand(OpNum);
816 int32_t OffImm = (int32_t)MO1.getImm();
819 O << "#-" << -OffImm;
824 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
826 const MachineOperand &MO1 = MI->getOperand(OpNum);
827 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
828 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
830 O << "[" << getRegisterName(MO1.getReg());
832 assert(MO2.getReg() && "Invalid so_reg load / store address!");
833 O << ", " << getRegisterName(MO2.getReg());
835 unsigned ShAmt = MO3.getImm();
837 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
838 O << ", lsl #" << ShAmt;
844 //===--------------------------------------------------------------------===//
846 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
847 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
849 O << ARMCondCodeToString(CC);
852 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
853 unsigned Reg = MI->getOperand(OpNum).getReg();
855 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
860 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
861 int Id = (int)MI->getOperand(OpNum).getImm();
862 O << MAI->getPrivateGlobalPrefix()
863 << "PC" << getFunctionNumber() << "_" << Id;
866 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
868 // Always skip the first operand, it's the optional (and implicit writeback).
869 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
870 if (MI->getOperand(i).isImplicit())
872 if ((int)i != OpNum+1) O << ", ";
878 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
879 const char *Modifier) {
880 assert(Modifier && "This operand only works with a modifier!");
881 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
883 if (!strcmp(Modifier, "label")) {
884 unsigned ID = MI->getOperand(OpNum).getImm();
885 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
886 << '_' << ID << ":\n";
888 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
889 unsigned CPI = MI->getOperand(OpNum).getIndex();
891 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
893 if (MCPE.isMachineConstantPoolEntry()) {
894 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
896 EmitGlobalConstant(MCPE.Val.ConstVal);
901 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
902 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
904 const MachineOperand &MO1 = MI->getOperand(OpNum);
905 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
906 unsigned JTI = MO1.getIndex();
907 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
908 << '_' << JTI << '_' << MO2.getImm() << ":\n";
910 const char *JTEntryDirective = MAI->getData32bitsDirective();
912 const MachineFunction *MF = MI->getParent()->getParent();
913 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
914 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
915 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
916 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
917 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
918 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
919 MachineBasicBlock *MBB = JTBBs[i];
920 bool isNew = JTSets.insert(MBB);
923 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
925 O << JTEntryDirective << ' ';
927 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
928 << '_' << JTI << '_' << MO2.getImm()
929 << "_set_" << MBB->getNumber();
930 else if (TM.getRelocationModel() == Reloc::PIC_) {
931 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
932 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
933 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
935 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
942 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
943 const MachineOperand &MO1 = MI->getOperand(OpNum);
944 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
945 unsigned JTI = MO1.getIndex();
946 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
947 << '_' << JTI << '_' << MO2.getImm() << ":\n";
949 const MachineFunction *MF = MI->getParent()->getParent();
950 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
951 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
952 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
953 bool ByteOffset = false, HalfWordOffset = false;
954 if (MI->getOpcode() == ARM::t2TBB)
956 else if (MI->getOpcode() == ARM::t2TBH)
957 HalfWordOffset = true;
959 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
960 MachineBasicBlock *MBB = JTBBs[i];
962 O << MAI->getData8bitsDirective();
963 else if (HalfWordOffset)
964 O << MAI->getData16bitsDirective();
965 if (ByteOffset || HalfWordOffset) {
967 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
968 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
969 << '_' << JTI << '_' << MO2.getImm() << ")/2";
972 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
978 // Make sure the instruction that follows TBB is 2-byte aligned.
979 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
980 if (ByteOffset && (JTBBs.size() & 1)) {
986 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
987 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
988 if (MI->getOpcode() == ARM::t2TBH)
993 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
994 O << MI->getOperand(OpNum).getImm();
997 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
998 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
999 O << '#' << ARM::getVFPf32Imm(FP->getValueAPF());
1001 O.PadToColumn(MAI->getCommentColumn());
1002 O << MAI->getCommentString() << ' ';
1003 WriteAsOperand(O, FP, /*PrintType=*/false);
1007 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1008 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1009 O << '#' << ARM::getVFPf64Imm(FP->getValueAPF());
1011 O.PadToColumn(MAI->getCommentColumn());
1012 O << MAI->getCommentString() << ' ';
1013 WriteAsOperand(O, FP, /*PrintType=*/false);
1017 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1018 unsigned AsmVariant, const char *ExtraCode){
1019 // Does this asm operand have a single letter operand modifier?
1020 if (ExtraCode && ExtraCode[0]) {
1021 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1023 switch (ExtraCode[0]) {
1024 default: return true; // Unknown modifier.
1025 case 'a': // Print as a memory address.
1026 if (MI->getOperand(OpNum).isReg()) {
1027 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1031 case 'c': // Don't print "#" before an immediate operand.
1032 if (!MI->getOperand(OpNum).isImm())
1034 printNoHashImmediate(MI, OpNum);
1036 case 'P': // Print a VFP double precision register.
1037 printOperand(MI, OpNum);
1040 if (TM.getTargetData()->isLittleEndian())
1044 if (TM.getTargetData()->isBigEndian())
1047 case 'H': // Write second word of DI / DF reference.
1048 // Verify that this operand has two consecutive registers.
1049 if (!MI->getOperand(OpNum).isReg() ||
1050 OpNum+1 == MI->getNumOperands() ||
1051 !MI->getOperand(OpNum+1).isReg())
1053 ++OpNum; // Return the high-part.
1057 printOperand(MI, OpNum);
1061 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1062 unsigned OpNum, unsigned AsmVariant,
1063 const char *ExtraCode) {
1064 if (ExtraCode && ExtraCode[0])
1065 return true; // Unknown modifier.
1067 const MachineOperand &MO = MI->getOperand(OpNum);
1068 assert(MO.isReg() && "unexpected inline asm memory operand");
1069 O << "[" << getRegisterName(MO.getReg()) << "]";
1073 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1076 // Call the autogenerated instruction printer routines.
1077 processDebugLoc(MI, true);
1080 printInstructionThroughMCStreamer(MI);
1082 int Opc = MI->getOpcode();
1083 if (Opc == ARM::CONSTPOOL_ENTRY)
1086 printInstruction(MI);
1089 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1092 processDebugLoc(MI, false);
1095 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1096 if (Subtarget->isTargetDarwin()) {
1097 Reloc::Model RelocM = TM.getRelocationModel();
1098 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1099 // Declare all the text sections up front (before the DWARF sections
1100 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1101 // them together at the beginning of the object file. This helps
1102 // avoid out-of-range branches that are due a fundamental limitation of
1103 // the way symbol offsets are encoded with the current Darwin ARM
1105 TargetLoweringObjectFileMachO &TLOFMacho =
1106 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1107 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1108 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1109 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1110 if (RelocM == Reloc::DynamicNoPIC) {
1111 const MCSection *sect =
1112 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1113 MCSectionMachO::S_SYMBOL_STUBS,
1114 12, SectionKind::getText());
1115 OutStreamer.SwitchSection(sect);
1117 const MCSection *sect =
1118 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1119 MCSectionMachO::S_SYMBOL_STUBS,
1120 16, SectionKind::getText());
1121 OutStreamer.SwitchSection(sect);
1126 // Use unified assembler syntax mode for Thumb.
1127 if (Subtarget->isThumb())
1128 O << "\t.syntax unified\n";
1130 // Emit ARM Build Attributes
1131 if (Subtarget->isTargetELF()) {
1133 std::string CPUString = Subtarget->getCPUString();
1134 if (CPUString != "generic")
1135 O << "\t.cpu " << CPUString << '\n';
1137 // FIXME: Emit FPU type
1138 if (Subtarget->hasVFP2())
1139 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1141 // Signal various FP modes.
1143 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1144 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1146 if (FiniteOnlyFPMath())
1147 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1149 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1151 // 8-bytes alignment stuff.
1152 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1153 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1155 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1156 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1157 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1158 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1160 // FIXME: Should we signal R9 usage?
1164 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1165 const TargetData *TD = TM.getTargetData();
1167 if (!GVar->hasInitializer()) // External global require no code
1170 // Check to see if this is a special global used by LLVM, if so, emit it.
1172 if (EmitSpecialLLVMGlobal(GVar)) {
1173 if (Subtarget->isTargetDarwin() &&
1174 TM.getRelocationModel() == Reloc::Static) {
1175 if (GVar->getName() == "llvm.global_ctors")
1176 O << ".reference .constructors_used\n";
1177 else if (GVar->getName() == "llvm.global_dtors")
1178 O << ".reference .destructors_used\n";
1183 std::string name = Mang->getMangledName(GVar);
1184 Constant *C = GVar->getInitializer();
1185 const Type *Type = C->getType();
1186 unsigned Size = TD->getTypeAllocSize(Type);
1187 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1188 bool isDarwin = Subtarget->isTargetDarwin();
1190 printVisibility(name, GVar->getVisibility());
1192 if (Subtarget->isTargetELF())
1193 O << "\t.type " << name << ",%object\n";
1195 const MCSection *TheSection =
1196 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1197 OutStreamer.SwitchSection(TheSection);
1199 // FIXME: get this stuff from section kind flags.
1200 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1201 // Don't put things that should go in the cstring section into "comm".
1202 !TheSection->getKind().isMergeableCString()) {
1203 if (GVar->hasExternalLinkage()) {
1204 if (const char *Directive = MAI->getZeroFillDirective()) {
1205 O << "\t.globl\t" << name << "\n";
1206 O << Directive << "__DATA, __common, " << name << ", "
1207 << Size << ", " << Align << "\n";
1212 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1213 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1216 if (GVar->hasLocalLinkage()) {
1217 O << MAI->getLCOMMDirective() << name << "," << Size
1219 } else if (GVar->hasCommonLinkage()) {
1220 O << MAI->getCOMMDirective() << name << "," << Size
1223 OutStreamer.SwitchSection(TheSection);
1224 O << "\t.globl " << name << '\n'
1225 << MAI->getWeakDefDirective() << name << '\n';
1226 EmitAlignment(Align, GVar);
1229 O.PadToColumn(MAI->getCommentColumn());
1230 O << MAI->getCommentString() << ' ';
1231 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1234 EmitGlobalConstant(C);
1237 } else if (MAI->getLCOMMDirective() != NULL) {
1238 if (GVar->hasLocalLinkage()) {
1239 O << MAI->getLCOMMDirective() << name << "," << Size;
1241 O << MAI->getCOMMDirective() << name << "," << Size;
1242 if (MAI->getCOMMDirectiveTakesAlignment())
1243 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1246 if (GVar->hasLocalLinkage())
1247 O << "\t.local\t" << name << "\n";
1248 O << MAI->getCOMMDirective() << name << "," << Size;
1249 if (MAI->getCOMMDirectiveTakesAlignment())
1250 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1253 O.PadToColumn(MAI->getCommentColumn());
1254 O << MAI->getCommentString() << ' ';
1255 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1262 switch (GVar->getLinkage()) {
1263 case GlobalValue::CommonLinkage:
1264 case GlobalValue::LinkOnceAnyLinkage:
1265 case GlobalValue::LinkOnceODRLinkage:
1266 case GlobalValue::WeakAnyLinkage:
1267 case GlobalValue::WeakODRLinkage:
1268 case GlobalValue::LinkerPrivateLinkage:
1270 O << "\t.globl " << name << "\n"
1271 << "\t.weak_definition " << name << "\n";
1273 O << "\t.weak " << name << "\n";
1276 case GlobalValue::AppendingLinkage:
1277 // FIXME: appending linkage variables should go into a section of
1278 // their name or something. For now, just emit them as external.
1279 case GlobalValue::ExternalLinkage:
1280 O << "\t.globl " << name << "\n";
1282 case GlobalValue::PrivateLinkage:
1283 case GlobalValue::InternalLinkage:
1286 llvm_unreachable("Unknown linkage type!");
1289 EmitAlignment(Align, GVar);
1292 O.PadToColumn(MAI->getCommentColumn());
1293 O << MAI->getCommentString() << ' ';
1294 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1297 if (MAI->hasDotTypeDotSizeDirective())
1298 O << "\t.size " << name << ", " << Size << "\n";
1300 EmitGlobalConstant(C);
1305 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1306 if (Subtarget->isTargetDarwin()) {
1307 // All darwin targets use mach-o.
1308 TargetLoweringObjectFileMachO &TLOFMacho =
1309 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1310 MachineModuleInfoMachO &MMIMacho =
1311 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1315 // Output non-lazy-pointers for external and common global variables.
1316 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1318 if (!Stubs.empty()) {
1319 // Switch with ".non_lazy_symbol_pointer" directive.
1320 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1322 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1323 Stubs[i].first->print(O, MAI);
1324 O << ":\n\t.indirect_symbol ";
1325 Stubs[i].second->print(O, MAI);
1326 O << "\n\t.long\t0\n";
1330 Stubs = MMIMacho.GetHiddenGVStubList();
1331 if (!Stubs.empty()) {
1332 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1334 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1335 Stubs[i].first->print(O, MAI);
1337 Stubs[i].second->print(O, MAI);
1342 // Funny Darwin hack: This flag tells the linker that no global symbols
1343 // contain code that falls through to other global symbols (e.g. the obvious
1344 // implementation of multiple entry points). If this doesn't occur, the
1345 // linker can safely perform dead code stripping. Since LLVM never
1346 // generates code that does this, it is always safe to set.
1347 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1351 //===----------------------------------------------------------------------===//
1353 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1354 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1355 switch (MI->getOpcode()) {
1356 case ARM::t2MOVi32imm:
1357 assert(0 && "Should be lowered by thumb2it pass");
1359 case TargetInstrInfo::DBG_LABEL:
1360 case TargetInstrInfo::EH_LABEL:
1361 case TargetInstrInfo::GC_LABEL:
1364 case TargetInstrInfo::KILL:
1367 case TargetInstrInfo::INLINEASM:
1370 case TargetInstrInfo::IMPLICIT_DEF:
1371 printImplicitDef(MI);
1373 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1374 // This is a pseudo op for a label + instruction sequence, which looks like:
1377 // This adds the address of LPC0 to r0.
1380 // FIXME: MOVE TO SHARED PLACE.
1381 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1382 const char *Prefix = MAI->getPrivateGlobalPrefix();
1383 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1384 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1385 OutStreamer.EmitLabel(Label);
1388 // Form and emit tha dd.
1390 AddInst.setOpcode(ARM::ADDrr);
1391 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1392 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1393 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1394 printMCInst(&AddInst);
1397 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1398 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1399 /// in the function. The first operand is the ID# for this instruction, the
1400 /// second is the index into the MachineConstantPool that this is, the third
1401 /// is the size in bytes of this constant pool entry.
1402 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1403 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1407 const char *Prefix = MAI->getPrivateGlobalPrefix();
1408 MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
1409 Twine(getFunctionNumber())+
1410 "_"+ Twine(LabelId));
1411 OutStreamer.EmitLabel(Label);
1413 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1414 if (MCPE.isMachineConstantPoolEntry())
1415 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1417 EmitGlobalConstant(MCPE.Val.ConstVal);
1421 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1422 // This is a hack that lowers as a two instruction sequence.
1423 unsigned DstReg = MI->getOperand(0).getReg();
1424 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1426 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1427 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1431 TmpInst.setOpcode(ARM::MOVi);
1432 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1433 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1436 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1437 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1439 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1440 printMCInst(&TmpInst);
1446 TmpInst.setOpcode(ARM::ORRri);
1447 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1448 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1449 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1451 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1452 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1454 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1455 printMCInst(&TmpInst);
1459 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1460 // This is a hack that lowers as a two instruction sequence.
1461 unsigned DstReg = MI->getOperand(0).getReg();
1462 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1466 TmpInst.setOpcode(ARM::MOVi16);
1467 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1468 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1471 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1472 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1474 printMCInst(&TmpInst);
1480 TmpInst.setOpcode(ARM::MOVTi16);
1481 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1482 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1483 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1486 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1487 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1489 printMCInst(&TmpInst);
1497 MCInstLowering.Lower(MI, TmpInst);
1499 printMCInst(&TmpInst);
1502 //===----------------------------------------------------------------------===//
1503 // Target Registry Stuff
1504 //===----------------------------------------------------------------------===//
1506 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1507 unsigned SyntaxVariant,
1508 const MCAsmInfo &MAI,
1510 if (SyntaxVariant == 0)
1511 return new ARMInstPrinter(O, MAI, false);
1515 // Force static initialization.
1516 extern "C" void LLVMInitializeARMAsmPrinter() {
1517 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1518 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1520 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1521 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);