1 // The LLVM Compiler Infrastructure
3 // This file is distributed under the University of Illinois Open Source
4 // License. See LICENSE.TXT for details.
6 //===----------------------------------------------------------------------===//
8 // This file contains a printer that converts from our internal representation
9 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBuildAttrs.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Module.h"
22 #include "llvm/Assembly/Writer.h"
23 #include "llvm/CodeGen/AsmPrinter.h"
24 #include "llvm/CodeGen/DwarfWriter.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetRegistry.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/SmallString.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/ADT/StringSet.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/Mangler.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/FormattedStream.h"
48 STATISTIC(EmittedInsts, "Number of machine instrs printed");
51 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when printing asm code for different targets.
56 const ARMSubtarget *Subtarget;
58 /// AFI - Keep a pointer to ARMFunctionInfo for the current
62 /// MCP - Keep a pointer to constantpool entries of the current
64 const MachineConstantPool *MCP;
66 /// We name each basic block in a Function with a unique number, so
67 /// that we can consistently refer to them later. This is cleared
68 /// at the beginning of each call to runOnMachineFunction().
70 typedef std::map<const Value *, unsigned> ValueMapTy;
71 ValueMapTy NumberForBB;
73 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
74 /// non-lazy-pointers for indirect access.
75 StringMap<std::string> GVNonLazyPtrs;
77 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
78 /// visibility that require non-lazy-pointers for indirect access.
79 StringMap<std::string> HiddenGVNonLazyPtrs;
81 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
84 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
85 const MCAsmInfo *T, bool V)
86 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
88 Subtarget = &TM.getSubtarget<ARMSubtarget>();
91 virtual const char *getPassName() const {
92 return "ARM Assembly Printer";
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbITMask(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
136 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
137 void printTBAddrMode(const MachineInstr *MI, int OpNum);
138 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
141 unsigned AsmVariant, const char *ExtraCode);
142 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
144 const char *ExtraCode);
146 void PrintGlobalVariable(const GlobalVariable* GVar);
147 void printInstruction(const MachineInstr *MI); // autogenerated.
148 void printMachineInstruction(const MachineInstr *MI);
149 bool runOnMachineFunction(MachineFunction &F);
150 bool doInitialization(Module &M);
151 bool doFinalization(Module &M);
153 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
155 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
156 printDataDirective(MCPV->getType());
158 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
159 GlobalValue *GV = ACPV->getGV();
162 if (ACPV->isLSDA()) {
163 SmallString<16> LSDAName;
164 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
165 "_LSDA_" << getFunctionNumber();
166 Name = LSDAName.str();
168 bool isIndirect = Subtarget->isTargetDarwin() &&
169 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
171 Name = Mang->getMangledName(GV);
173 // FIXME: Remove this when Darwin transition to @GOT like syntax.
174 std::string SymName = Mang->getMangledName(GV);
175 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
176 if (GV->hasHiddenVisibility())
177 HiddenGVNonLazyPtrs[SymName] = Name;
179 GVNonLazyPtrs[SymName] = Name;
182 Name = Mang->makeNameProper(ACPV->getSymbol());
185 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
186 if (ACPV->getPCAdjustment() != 0) {
187 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
188 << ACPV->getLabelId()
189 << "+" << (unsigned)ACPV->getPCAdjustment();
190 if (ACPV->mustAddCurrentAddress())
197 void getAnalysisUsage(AnalysisUsage &AU) const {
198 AsmPrinter::getAnalysisUsage(AU);
199 AU.setPreservesAll();
200 AU.addRequired<MachineModuleInfo>();
201 AU.addRequired<DwarfWriter>();
204 } // end of anonymous namespace
206 #include "ARMGenAsmWriter.inc"
208 /// runOnMachineFunction - This uses the printInstruction()
209 /// method to print assembly for each instruction.
211 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
214 AFI = MF.getInfo<ARMFunctionInfo>();
215 MCP = MF.getConstantPool();
217 SetupMachineFunction(MF);
220 // NOTE: we don't print out constant pools here, they are handled as
225 // Print out labels for the function.
226 const Function *F = MF.getFunction();
227 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
229 switch (F->getLinkage()) {
230 default: llvm_unreachable("Unknown linkage type!");
231 case Function::PrivateLinkage:
232 case Function::InternalLinkage:
234 case Function::ExternalLinkage:
235 O << "\t.globl\t" << CurrentFnName << "\n";
237 case Function::LinkerPrivateLinkage:
238 case Function::WeakAnyLinkage:
239 case Function::WeakODRLinkage:
240 case Function::LinkOnceAnyLinkage:
241 case Function::LinkOnceODRLinkage:
242 if (Subtarget->isTargetDarwin()) {
243 O << "\t.globl\t" << CurrentFnName << "\n";
244 O << "\t.weak_definition\t" << CurrentFnName << "\n";
246 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
251 printVisibility(CurrentFnName, F->getVisibility());
253 if (AFI->isThumbFunction()) {
254 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
255 O << "\t.code\t16\n";
256 O << "\t.thumb_func";
257 if (Subtarget->isTargetDarwin())
258 O << "\t" << CurrentFnName;
262 EmitAlignment(MF.getAlignment(), F);
265 O << CurrentFnName << ":\n";
266 // Emit pre-function debug information.
267 DW->BeginFunction(&MF);
269 if (Subtarget->isTargetDarwin()) {
270 // If the function is empty, then we need to emit *something*. Otherwise,
271 // the function's label might be associated with something that it wasn't
272 // meant to be associated with. We emit a noop in this situation.
273 MachineFunction::iterator I = MF.begin();
275 if (++I == MF.end() && MF.front().empty())
279 // Print out code for the function.
280 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
282 // Print a label for the basic block.
283 if (I != MF.begin()) {
284 printBasicBlockLabel(I, true, true, VerboseAsm);
287 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
289 // Print the assembly for the instruction.
290 printMachineInstruction(II);
294 if (MAI->hasDotTypeDotSizeDirective())
295 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
297 // Emit post-function debug information.
298 DW->EndFunction(&MF);
303 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
304 const char *Modifier) {
305 const MachineOperand &MO = MI->getOperand(OpNum);
306 switch (MO.getType()) {
307 case MachineOperand::MO_Register: {
308 unsigned Reg = MO.getReg();
309 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
310 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
311 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
312 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
314 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
316 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
317 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
318 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
320 O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
322 O << TRI->getAsmName(Reg);
325 llvm_unreachable("not implemented");
328 case MachineOperand::MO_Immediate: {
329 O << '#' << MO.getImm();
332 case MachineOperand::MO_MachineBasicBlock:
333 printBasicBlockLabel(MO.getMBB());
335 case MachineOperand::MO_GlobalAddress: {
336 bool isCallOp = Modifier && !strcmp(Modifier, "call");
337 GlobalValue *GV = MO.getGlobal();
338 O << Mang->getMangledName(GV);
340 printOffset(MO.getOffset());
342 if (isCallOp && Subtarget->isTargetELF() &&
343 TM.getRelocationModel() == Reloc::PIC_)
347 case MachineOperand::MO_ExternalSymbol: {
348 bool isCallOp = Modifier && !strcmp(Modifier, "call");
349 std::string Name = Mang->makeNameProper(MO.getSymbolName());
352 if (isCallOp && Subtarget->isTargetELF() &&
353 TM.getRelocationModel() == Reloc::PIC_)
357 case MachineOperand::MO_ConstantPoolIndex:
358 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
359 << '_' << MO.getIndex();
361 case MachineOperand::MO_JumpTableIndex:
362 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
363 << '_' << MO.getIndex();
366 O << "<unknown operand type>"; abort (); break;
370 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
371 const MCAsmInfo *MAI) {
372 // Break it up into two parts that make up a shifter immediate.
373 V = ARM_AM::getSOImmVal(V);
374 assert(V != -1 && "Not a valid so_imm value!");
376 unsigned Imm = ARM_AM::getSOImmValImm(V);
377 unsigned Rot = ARM_AM::getSOImmValRot(V);
379 // Print low-level immediate formation info, per
380 // A5.1.3: "Data-processing operands - Immediate".
382 O << "#" << Imm << ", " << Rot;
383 // Pretty printed version.
385 O << ' ' << MAI->getCommentString()
386 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
392 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
393 /// immediate in bits 0-7.
394 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
395 const MachineOperand &MO = MI->getOperand(OpNum);
396 assert(MO.isImm() && "Not a valid so_imm value!");
397 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
400 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
401 /// followed by an 'orr' to materialize.
402 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
403 const MachineOperand &MO = MI->getOperand(OpNum);
404 assert(MO.isImm() && "Not a valid so_imm value!");
405 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
406 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
407 printSOImm(O, V1, VerboseAsm, MAI);
409 printPredicateOperand(MI, 2);
415 printSOImm(O, V2, VerboseAsm, MAI);
418 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
419 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
421 // REG REG 0,SH_OPC - e.g. R5, ROR R3
422 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
423 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
424 const MachineOperand &MO1 = MI->getOperand(Op);
425 const MachineOperand &MO2 = MI->getOperand(Op+1);
426 const MachineOperand &MO3 = MI->getOperand(Op+2);
428 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
429 O << TRI->getAsmName(MO1.getReg());
431 // Print the shift opc.
433 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
437 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
438 O << TRI->getAsmName(MO2.getReg());
439 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
441 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
445 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
446 const MachineOperand &MO1 = MI->getOperand(Op);
447 const MachineOperand &MO2 = MI->getOperand(Op+1);
448 const MachineOperand &MO3 = MI->getOperand(Op+2);
450 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
451 printOperand(MI, Op);
455 O << "[" << TRI->getAsmName(MO1.getReg());
458 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
460 << (char)ARM_AM::getAM2Op(MO3.getImm())
461 << ARM_AM::getAM2Offset(MO3.getImm());
467 << (char)ARM_AM::getAM2Op(MO3.getImm())
468 << TRI->getAsmName(MO2.getReg());
470 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
472 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
477 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
478 const MachineOperand &MO1 = MI->getOperand(Op);
479 const MachineOperand &MO2 = MI->getOperand(Op+1);
482 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
483 assert(ImmOffs && "Malformed indexed load / store!");
485 << (char)ARM_AM::getAM2Op(MO2.getImm())
490 O << (char)ARM_AM::getAM2Op(MO2.getImm())
491 << TRI->getAsmName(MO1.getReg());
493 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
495 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
499 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
500 const MachineOperand &MO1 = MI->getOperand(Op);
501 const MachineOperand &MO2 = MI->getOperand(Op+1);
502 const MachineOperand &MO3 = MI->getOperand(Op+2);
504 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
505 O << "[" << TRI->getAsmName(MO1.getReg());
509 << (char)ARM_AM::getAM3Op(MO3.getImm())
510 << TRI->getAsmName(MO2.getReg())
515 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
517 << (char)ARM_AM::getAM3Op(MO3.getImm())
522 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
523 const MachineOperand &MO1 = MI->getOperand(Op);
524 const MachineOperand &MO2 = MI->getOperand(Op+1);
527 O << (char)ARM_AM::getAM3Op(MO2.getImm())
528 << TRI->getAsmName(MO1.getReg());
532 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
533 assert(ImmOffs && "Malformed indexed load / store!");
535 << (char)ARM_AM::getAM3Op(MO2.getImm())
539 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
540 const char *Modifier) {
541 const MachineOperand &MO1 = MI->getOperand(Op);
542 const MachineOperand &MO2 = MI->getOperand(Op+1);
543 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
544 if (Modifier && strcmp(Modifier, "submode") == 0) {
545 if (MO1.getReg() == ARM::SP) {
547 bool isLDM = (MI->getOpcode() == ARM::LDM ||
548 MI->getOpcode() == ARM::LDM_RET ||
549 MI->getOpcode() == ARM::t2LDM ||
550 MI->getOpcode() == ARM::t2LDM_RET);
551 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
553 O << ARM_AM::getAMSubModeStr(Mode);
554 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
555 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
556 if (Mode == ARM_AM::ia)
559 printOperand(MI, Op);
560 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
565 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
566 const char *Modifier) {
567 const MachineOperand &MO1 = MI->getOperand(Op);
568 const MachineOperand &MO2 = MI->getOperand(Op+1);
570 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
571 printOperand(MI, Op);
575 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
577 if (Modifier && strcmp(Modifier, "submode") == 0) {
578 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
579 if (MO1.getReg() == ARM::SP) {
580 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
581 MI->getOpcode() == ARM::FLDMS);
582 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
584 O << ARM_AM::getAMSubModeStr(Mode);
586 } else if (Modifier && strcmp(Modifier, "base") == 0) {
587 // Used for FSTM{D|S} and LSTM{D|S} operations.
588 O << TRI->getAsmName(MO1.getReg());
589 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
594 O << "[" << TRI->getAsmName(MO1.getReg());
596 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
598 << (char)ARM_AM::getAM5Op(MO2.getImm())
604 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
605 const MachineOperand &MO1 = MI->getOperand(Op);
606 const MachineOperand &MO2 = MI->getOperand(Op+1);
607 const MachineOperand &MO3 = MI->getOperand(Op+2);
609 // FIXME: No support yet for specifying alignment.
610 O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
612 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
613 if (MO2.getReg() == 0)
616 O << ", " << TRI->getAsmName(MO2.getReg());
620 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
621 const char *Modifier) {
622 if (Modifier && strcmp(Modifier, "label") == 0) {
623 printPCLabel(MI, Op+1);
627 const MachineOperand &MO1 = MI->getOperand(Op);
628 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
629 O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
633 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
634 const MachineOperand &MO = MI->getOperand(Op);
635 uint32_t v = ~MO.getImm();
636 int32_t lsb = CountTrailingZeros_32(v);
637 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
638 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
639 O << "#" << lsb << ", #" << width;
642 //===--------------------------------------------------------------------===//
645 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
646 // (3 - the number of trailing zeros) is the number of then / else.
647 unsigned Mask = MI->getOperand(Op).getImm();
648 unsigned NumTZ = CountTrailingZeros_32(Mask);
649 assert(NumTZ <= 3 && "Invalid IT mask!");
650 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
651 bool T = (Mask & (1 << Pos)) == 0;
660 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
661 const MachineOperand &MO1 = MI->getOperand(Op);
662 const MachineOperand &MO2 = MI->getOperand(Op+1);
663 O << "[" << TRI->getAsmName(MO1.getReg());
664 O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
668 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
670 const MachineOperand &MO1 = MI->getOperand(Op);
671 const MachineOperand &MO2 = MI->getOperand(Op+1);
672 const MachineOperand &MO3 = MI->getOperand(Op+2);
674 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
675 printOperand(MI, Op);
679 O << "[" << TRI->getAsmName(MO1.getReg());
681 O << ", " << TRI->getAsmName(MO3.getReg());
682 else if (unsigned ImmOffs = MO2.getImm()) {
683 O << ", #" << ImmOffs;
691 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
692 printThumbAddrModeRI5Operand(MI, Op, 1);
695 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
696 printThumbAddrModeRI5Operand(MI, Op, 2);
699 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
700 printThumbAddrModeRI5Operand(MI, Op, 4);
703 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
704 const MachineOperand &MO1 = MI->getOperand(Op);
705 const MachineOperand &MO2 = MI->getOperand(Op+1);
706 O << "[" << TRI->getAsmName(MO1.getReg());
707 if (unsigned ImmOffs = MO2.getImm())
708 O << ", #" << ImmOffs << " * 4";
712 //===--------------------------------------------------------------------===//
714 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
715 // register with shift forms.
717 // REG IMM, SH_OPC - e.g. R5, LSL #3
718 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
719 const MachineOperand &MO1 = MI->getOperand(OpNum);
720 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
722 unsigned Reg = MO1.getReg();
723 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
724 O << TRI->getAsmName(Reg);
726 // Print the shift opc.
728 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
731 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
732 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
735 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
737 const MachineOperand &MO1 = MI->getOperand(OpNum);
738 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
740 O << "[" << TRI->getAsmName(MO1.getReg());
742 unsigned OffImm = MO2.getImm();
743 if (OffImm) // Don't print +0.
744 O << ", #+" << OffImm;
748 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
750 const MachineOperand &MO1 = MI->getOperand(OpNum);
751 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
753 O << "[" << TRI->getAsmName(MO1.getReg());
755 int32_t OffImm = (int32_t)MO2.getImm();
758 O << ", #-" << -OffImm;
760 O << ", #+" << OffImm;
764 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
766 const MachineOperand &MO1 = MI->getOperand(OpNum);
767 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
769 O << "[" << TRI->getAsmName(MO1.getReg());
771 int32_t OffImm = (int32_t)MO2.getImm() / 4;
774 O << ", #-" << -OffImm << " * 4";
776 O << ", #+" << OffImm << " * 4";
780 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
782 const MachineOperand &MO1 = MI->getOperand(OpNum);
783 int32_t OffImm = (int32_t)MO1.getImm();
786 O << "#-" << -OffImm;
791 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
793 const MachineOperand &MO1 = MI->getOperand(OpNum);
794 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
795 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
797 O << "[" << TRI->getAsmName(MO1.getReg());
799 assert(MO2.getReg() && "Invalid so_reg load / store address!");
800 O << ", " << TRI->getAsmName(MO2.getReg());
802 unsigned ShAmt = MO3.getImm();
804 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
805 O << ", lsl #" << ShAmt;
811 //===--------------------------------------------------------------------===//
813 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
814 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
816 O << ARMCondCodeToString(CC);
819 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
820 unsigned Reg = MI->getOperand(OpNum).getReg();
822 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
827 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
828 int Id = (int)MI->getOperand(OpNum).getImm();
829 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
832 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
834 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
835 if (MI->getOperand(i).isImplicit())
837 if ((int)i != OpNum) O << ", ";
843 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
844 const char *Modifier) {
845 assert(Modifier && "This operand only works with a modifier!");
846 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
848 if (!strcmp(Modifier, "label")) {
849 unsigned ID = MI->getOperand(OpNum).getImm();
850 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
851 << '_' << ID << ":\n";
853 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
854 unsigned CPI = MI->getOperand(OpNum).getIndex();
856 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
858 if (MCPE.isMachineConstantPoolEntry()) {
859 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
861 EmitGlobalConstant(MCPE.Val.ConstVal);
866 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
867 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
869 const MachineOperand &MO1 = MI->getOperand(OpNum);
870 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
871 unsigned JTI = MO1.getIndex();
872 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
873 << '_' << JTI << '_' << MO2.getImm() << ":\n";
875 const char *JTEntryDirective = MAI->getData32bitsDirective();
877 const MachineFunction *MF = MI->getParent()->getParent();
878 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
879 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
880 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
881 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
882 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
883 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
884 MachineBasicBlock *MBB = JTBBs[i];
885 bool isNew = JTSets.insert(MBB);
888 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
890 O << JTEntryDirective << ' ';
892 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
893 << '_' << JTI << '_' << MO2.getImm()
894 << "_set_" << MBB->getNumber();
895 else if (TM.getRelocationModel() == Reloc::PIC_) {
896 printBasicBlockLabel(MBB, false, false, false);
897 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
898 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
900 printBasicBlockLabel(MBB, false, false, false);
907 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
908 const MachineOperand &MO1 = MI->getOperand(OpNum);
909 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
910 unsigned JTI = MO1.getIndex();
911 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
912 << '_' << JTI << '_' << MO2.getImm() << ":\n";
914 const MachineFunction *MF = MI->getParent()->getParent();
915 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
916 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
917 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
918 bool ByteOffset = false, HalfWordOffset = false;
919 if (MI->getOpcode() == ARM::t2TBB)
921 else if (MI->getOpcode() == ARM::t2TBH)
922 HalfWordOffset = true;
924 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
925 MachineBasicBlock *MBB = JTBBs[i];
927 O << MAI->getData8bitsDirective();
928 else if (HalfWordOffset)
929 O << MAI->getData16bitsDirective();
930 if (ByteOffset || HalfWordOffset) {
932 printBasicBlockLabel(MBB, false, false, false);
933 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
934 << '_' << JTI << '_' << MO2.getImm() << ")/2";
937 printBasicBlockLabel(MBB, false, false, false);
943 // Make sure the instruction that follows TBB is 2-byte aligned.
944 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
945 if (ByteOffset && (JTBBs.size() & 1)) {
951 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
952 O << "[pc, " << TRI->getAsmName(MI->getOperand(OpNum).getReg());
953 if (MI->getOpcode() == ARM::t2TBH)
958 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
959 O << MI->getOperand(OpNum).getImm();
962 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
963 unsigned AsmVariant, const char *ExtraCode){
964 // Does this asm operand have a single letter operand modifier?
965 if (ExtraCode && ExtraCode[0]) {
966 if (ExtraCode[1] != 0) return true; // Unknown modifier.
968 switch (ExtraCode[0]) {
969 default: return true; // Unknown modifier.
970 case 'a': // Print as a memory address.
971 if (MI->getOperand(OpNum).isReg()) {
972 O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
976 case 'c': // Don't print "#" before an immediate operand.
977 if (!MI->getOperand(OpNum).isImm())
979 printNoHashImmediate(MI, OpNum);
981 case 'P': // Print a VFP double precision register.
982 printOperand(MI, OpNum);
985 if (TM.getTargetData()->isLittleEndian())
989 if (TM.getTargetData()->isBigEndian())
992 case 'H': // Write second word of DI / DF reference.
993 // Verify that this operand has two consecutive registers.
994 if (!MI->getOperand(OpNum).isReg() ||
995 OpNum+1 == MI->getNumOperands() ||
996 !MI->getOperand(OpNum+1).isReg())
998 ++OpNum; // Return the high-part.
1002 printOperand(MI, OpNum);
1006 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1007 unsigned OpNum, unsigned AsmVariant,
1008 const char *ExtraCode) {
1009 if (ExtraCode && ExtraCode[0])
1010 return true; // Unknown modifier.
1011 printAddrMode2Operand(MI, OpNum);
1015 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1018 int Opc = MI->getOpcode();
1020 case ARM::CONSTPOOL_ENTRY:
1021 if (!InCPMode && AFI->isThumbFunction()) {
1027 if (InCPMode && AFI->isThumbFunction())
1031 // Call the autogenerated instruction printer routines.
1032 printInstruction(MI);
1035 bool ARMAsmPrinter::doInitialization(Module &M) {
1037 bool Result = AsmPrinter::doInitialization(M);
1038 DW = getAnalysisIfAvailable<DwarfWriter>();
1040 // Use unified assembler syntax mode for Thumb.
1041 if (Subtarget->isThumb())
1042 O << "\t.syntax unified\n";
1044 // Emit ARM Build Attributes
1045 if (Subtarget->isTargetELF()) {
1047 std::string CPUString = Subtarget->getCPUString();
1048 if (CPUString != "generic")
1049 O << "\t.cpu " << CPUString << '\n';
1051 // FIXME: Emit FPU type
1052 if (Subtarget->hasVFP2())
1053 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1055 // Signal various FP modes.
1057 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1058 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1060 if (FiniteOnlyFPMath())
1061 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1063 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1065 // 8-bytes alignment stuff.
1066 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1067 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1069 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1070 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1071 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1072 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1074 // FIXME: Should we signal R9 usage?
1080 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1081 const TargetData *TD = TM.getTargetData();
1083 if (!GVar->hasInitializer()) // External global require no code
1086 // Check to see if this is a special global used by LLVM, if so, emit it.
1088 if (EmitSpecialLLVMGlobal(GVar)) {
1089 if (Subtarget->isTargetDarwin() &&
1090 TM.getRelocationModel() == Reloc::Static) {
1091 if (GVar->getName() == "llvm.global_ctors")
1092 O << ".reference .constructors_used\n";
1093 else if (GVar->getName() == "llvm.global_dtors")
1094 O << ".reference .destructors_used\n";
1099 std::string name = Mang->getMangledName(GVar);
1100 Constant *C = GVar->getInitializer();
1101 const Type *Type = C->getType();
1102 unsigned Size = TD->getTypeAllocSize(Type);
1103 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1104 bool isDarwin = Subtarget->isTargetDarwin();
1106 printVisibility(name, GVar->getVisibility());
1108 if (Subtarget->isTargetELF())
1109 O << "\t.type " << name << ",%object\n";
1111 const MCSection *TheSection =
1112 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1113 OutStreamer.SwitchSection(TheSection);
1115 // FIXME: get this stuff from section kind flags.
1116 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1117 // Don't put things that should go in the cstring section into "comm".
1118 !TheSection->getKind().isMergeableCString()) {
1119 if (GVar->hasExternalLinkage()) {
1120 if (const char *Directive = MAI->getZeroFillDirective()) {
1121 O << "\t.globl\t" << name << "\n";
1122 O << Directive << "__DATA, __common, " << name << ", "
1123 << Size << ", " << Align << "\n";
1128 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1129 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1132 if (GVar->hasLocalLinkage()) {
1133 O << MAI->getLCOMMDirective() << name << "," << Size
1135 } else if (GVar->hasCommonLinkage()) {
1136 O << MAI->getCOMMDirective() << name << "," << Size
1139 OutStreamer.SwitchSection(TheSection);
1140 O << "\t.globl " << name << '\n'
1141 << MAI->getWeakDefDirective() << name << '\n';
1142 EmitAlignment(Align, GVar);
1145 O << "\t\t\t\t" << MAI->getCommentString() << ' ';
1146 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1149 EmitGlobalConstant(C);
1152 } else if (MAI->getLCOMMDirective() != NULL) {
1153 if (GVar->hasLocalLinkage()) {
1154 O << MAI->getLCOMMDirective() << name << "," << Size;
1156 O << MAI->getCOMMDirective() << name << "," << Size;
1157 if (MAI->getCOMMDirectiveTakesAlignment())
1158 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1161 if (GVar->hasLocalLinkage())
1162 O << "\t.local\t" << name << "\n";
1163 O << MAI->getCOMMDirective() << name << "," << Size;
1164 if (MAI->getCOMMDirectiveTakesAlignment())
1165 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1168 O << "\t\t" << MAI->getCommentString() << " ";
1169 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1176 switch (GVar->getLinkage()) {
1177 case GlobalValue::CommonLinkage:
1178 case GlobalValue::LinkOnceAnyLinkage:
1179 case GlobalValue::LinkOnceODRLinkage:
1180 case GlobalValue::WeakAnyLinkage:
1181 case GlobalValue::WeakODRLinkage:
1182 case GlobalValue::LinkerPrivateLinkage:
1184 O << "\t.globl " << name << "\n"
1185 << "\t.weak_definition " << name << "\n";
1187 O << "\t.weak " << name << "\n";
1190 case GlobalValue::AppendingLinkage:
1191 // FIXME: appending linkage variables should go into a section of
1192 // their name or something. For now, just emit them as external.
1193 case GlobalValue::ExternalLinkage:
1194 O << "\t.globl " << name << "\n";
1196 case GlobalValue::PrivateLinkage:
1197 case GlobalValue::InternalLinkage:
1200 llvm_unreachable("Unknown linkage type!");
1203 EmitAlignment(Align, GVar);
1206 O << "\t\t\t\t" << MAI->getCommentString() << " ";
1207 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1210 if (MAI->hasDotTypeDotSizeDirective())
1211 O << "\t.size " << name << ", " << Size << "\n";
1213 EmitGlobalConstant(C);
1218 bool ARMAsmPrinter::doFinalization(Module &M) {
1219 if (Subtarget->isTargetDarwin()) {
1220 // All darwin targets use mach-o.
1221 TargetLoweringObjectFileMachO &TLOFMacho =
1222 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1226 // Output non-lazy-pointers for external and common global variables.
1227 if (!GVNonLazyPtrs.empty()) {
1228 // Switch with ".non_lazy_symbol_pointer" directive.
1229 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1231 for (StringMap<std::string>::iterator I = GVNonLazyPtrs.begin(),
1232 E = GVNonLazyPtrs.end(); I != E; ++I) {
1233 O << I->second << ":\n";
1234 O << "\t.indirect_symbol " << I->getKeyData() << "\n";
1235 O << "\t.long\t0\n";
1239 if (!HiddenGVNonLazyPtrs.empty()) {
1240 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1242 for (StringMap<std::string>::iterator I = HiddenGVNonLazyPtrs.begin(),
1243 E = HiddenGVNonLazyPtrs.end(); I != E; ++I) {
1244 O << I->second << ":\n";
1245 O << "\t.long " << I->getKeyData() << "\n";
1249 // Funny Darwin hack: This flag tells the linker that no global symbols
1250 // contain code that falls through to other global symbols (e.g. the obvious
1251 // implementation of multiple entry points). If this doesn't occur, the
1252 // linker can safely perform dead code stripping. Since LLVM never
1253 // generates code that does this, it is always safe to set.
1254 O << "\t.subsections_via_symbols\n";
1257 return AsmPrinter::doFinalization(M);
1260 // Force static initialization.
1261 extern "C" void LLVMInitializeARMAsmPrinter() {
1262 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1263 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);