1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Assembly/Writer.h"
27 #include "llvm/CodeGen/AsmPrinter.h"
28 #include "llvm/CodeGen/DwarfWriter.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCSectionMachO.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Target/TargetRegistry.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallString.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/StringSet.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/FormattedStream.h"
51 #include "llvm/Support/Mangler.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbITMask(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
136 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
137 void printTBAddrMode(const MachineInstr *MI, int OpNum);
138 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
139 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
140 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
142 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
143 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
145 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
146 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
148 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
149 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
151 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
152 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
155 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
156 unsigned AsmVariant, const char *ExtraCode);
157 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
159 const char *ExtraCode);
161 void PrintGlobalVariable(const GlobalVariable* GVar);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
172 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
173 printDataDirective(MCPV->getType());
175 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
178 if (ACPV->isLSDA()) {
179 SmallString<16> LSDAName;
180 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
181 "_LSDA_" << getFunctionNumber();
182 Name = LSDAName.str();
183 } else if (ACPV->isBlockAddress()) {
184 Name = GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
185 } else if (ACPV->isGlobalValue()) {
186 GlobalValue *GV = ACPV->getGV();
187 bool isIndirect = Subtarget->isTargetDarwin() &&
188 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
190 Name = Mang->getMangledName(GV);
192 // FIXME: Remove this when Darwin transition to @GOT like syntax.
193 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
194 MCSymbol *Sym = OutContext.GetOrCreateSymbol(StringRef(Name));
196 MachineModuleInfoMachO &MMIMachO =
197 MMI->getObjFileInfo<MachineModuleInfoMachO>();
198 const MCSymbol *&StubSym =
199 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
200 MMIMachO.getGVStubEntry(Sym);
202 SmallString<128> NameStr;
203 Mang->getNameWithPrefix(NameStr, GV, false);
204 StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
208 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
209 Name = Mang->makeNameProper(ACPV->getSymbol());
213 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
214 if (ACPV->getPCAdjustment() != 0) {
215 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
216 << getFunctionNumber() << "_" << ACPV->getLabelId()
217 << "+" << (unsigned)ACPV->getPCAdjustment();
218 if (ACPV->mustAddCurrentAddress())
225 void getAnalysisUsage(AnalysisUsage &AU) const {
226 AsmPrinter::getAnalysisUsage(AU);
227 AU.setPreservesAll();
228 AU.addRequired<MachineModuleInfo>();
229 AU.addRequired<DwarfWriter>();
232 } // end of anonymous namespace
234 #include "ARMGenAsmWriter.inc"
236 /// runOnMachineFunction - This uses the printInstruction()
237 /// method to print assembly for each instruction.
239 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
242 AFI = MF.getInfo<ARMFunctionInfo>();
243 MCP = MF.getConstantPool();
245 SetupMachineFunction(MF);
248 // NOTE: we don't print out constant pools here, they are handled as
253 // Print out labels for the function.
254 const Function *F = MF.getFunction();
255 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
257 switch (F->getLinkage()) {
258 default: llvm_unreachable("Unknown linkage type!");
259 case Function::PrivateLinkage:
260 case Function::InternalLinkage:
262 case Function::ExternalLinkage:
263 O << "\t.globl\t" << CurrentFnName << "\n";
265 case Function::LinkerPrivateLinkage:
266 case Function::WeakAnyLinkage:
267 case Function::WeakODRLinkage:
268 case Function::LinkOnceAnyLinkage:
269 case Function::LinkOnceODRLinkage:
270 if (Subtarget->isTargetDarwin()) {
271 O << "\t.globl\t" << CurrentFnName << "\n";
272 O << "\t.weak_definition\t" << CurrentFnName << "\n";
274 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
279 printVisibility(CurrentFnName, F->getVisibility());
281 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
282 if (AFI->isThumbFunction()) {
283 EmitAlignment(FnAlign, F, AFI->getAlign());
284 O << "\t.code\t16\n";
285 O << "\t.thumb_func";
286 if (Subtarget->isTargetDarwin())
287 O << "\t" << CurrentFnName;
290 EmitAlignment(FnAlign, F);
293 O << CurrentFnName << ":\n";
294 // Emit pre-function debug information.
295 DW->BeginFunction(&MF);
297 if (Subtarget->isTargetDarwin()) {
298 // If the function is empty, then we need to emit *something*. Otherwise,
299 // the function's label might be associated with something that it wasn't
300 // meant to be associated with. We emit a noop in this situation.
301 MachineFunction::iterator I = MF.begin();
303 if (++I == MF.end() && MF.front().empty())
307 // Print out code for the function.
308 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
310 // Print a label for the basic block.
312 EmitBasicBlockStart(I);
314 // Print the assembly for the instruction.
315 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
317 printMachineInstruction(II);
320 if (MAI->hasDotTypeDotSizeDirective())
321 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
323 // Emit post-function debug information.
324 DW->EndFunction(&MF);
329 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
330 const char *Modifier) {
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 switch (MO.getType()) {
334 assert(0 && "<unknown operand type>");
335 case MachineOperand::MO_Register: {
336 unsigned Reg = MO.getReg();
337 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
338 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
339 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
340 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
342 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
344 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
345 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
346 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
347 &ARM::DPR_VFP2RegClass);
348 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
350 if (unsigned SubReg = MO.getSubReg())
351 Reg = TRI->getSubReg(Reg, SubReg);
353 O << getRegisterName(Reg);
357 case MachineOperand::MO_Immediate: {
358 int64_t Imm = MO.getImm();
361 if (strcmp(Modifier, "lo16") == 0)
363 else if (strcmp(Modifier, "hi16") == 0)
369 case MachineOperand::MO_MachineBasicBlock:
370 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
372 case MachineOperand::MO_GlobalAddress: {
373 bool isCallOp = Modifier && !strcmp(Modifier, "call");
374 GlobalValue *GV = MO.getGlobal();
375 O << Mang->getMangledName(GV);
377 printOffset(MO.getOffset());
379 if (isCallOp && Subtarget->isTargetELF() &&
380 TM.getRelocationModel() == Reloc::PIC_)
384 case MachineOperand::MO_ExternalSymbol: {
385 bool isCallOp = Modifier && !strcmp(Modifier, "call");
386 std::string Name = Mang->makeNameProper(MO.getSymbolName());
389 if (isCallOp && Subtarget->isTargetELF() &&
390 TM.getRelocationModel() == Reloc::PIC_)
394 case MachineOperand::MO_ConstantPoolIndex:
395 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
396 << '_' << MO.getIndex();
398 case MachineOperand::MO_JumpTableIndex:
399 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
400 << '_' << MO.getIndex();
405 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
406 const MCAsmInfo *MAI) {
407 // Break it up into two parts that make up a shifter immediate.
408 V = ARM_AM::getSOImmVal(V);
409 assert(V != -1 && "Not a valid so_imm value!");
411 unsigned Imm = ARM_AM::getSOImmValImm(V);
412 unsigned Rot = ARM_AM::getSOImmValRot(V);
414 // Print low-level immediate formation info, per
415 // A5.1.3: "Data-processing operands - Immediate".
417 O << "#" << Imm << ", " << Rot;
418 // Pretty printed version.
420 O.PadToColumn(MAI->getCommentColumn());
421 O << MAI->getCommentString() << ' ';
422 O << (int)ARM_AM::rotr32(Imm, Rot);
429 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
430 /// immediate in bits 0-7.
431 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
432 const MachineOperand &MO = MI->getOperand(OpNum);
433 assert(MO.isImm() && "Not a valid so_imm value!");
434 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
437 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
438 /// followed by an 'orr' to materialize.
439 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
440 const MachineOperand &MO = MI->getOperand(OpNum);
441 assert(MO.isImm() && "Not a valid so_imm value!");
442 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
443 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
444 printSOImm(O, V1, VerboseAsm, MAI);
446 printPredicateOperand(MI, 2);
452 printSOImm(O, V2, VerboseAsm, MAI);
455 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
456 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
458 // REG REG 0,SH_OPC - e.g. R5, ROR R3
459 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
460 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
461 const MachineOperand &MO1 = MI->getOperand(Op);
462 const MachineOperand &MO2 = MI->getOperand(Op+1);
463 const MachineOperand &MO3 = MI->getOperand(Op+2);
465 O << getRegisterName(MO1.getReg());
467 // Print the shift opc.
469 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
473 O << getRegisterName(MO2.getReg());
474 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
476 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
480 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
481 const MachineOperand &MO1 = MI->getOperand(Op);
482 const MachineOperand &MO2 = MI->getOperand(Op+1);
483 const MachineOperand &MO3 = MI->getOperand(Op+2);
485 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
486 printOperand(MI, Op);
490 O << "[" << getRegisterName(MO1.getReg());
493 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
495 << (char)ARM_AM::getAM2Op(MO3.getImm())
496 << ARM_AM::getAM2Offset(MO3.getImm());
502 << (char)ARM_AM::getAM2Op(MO3.getImm())
503 << getRegisterName(MO2.getReg());
505 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
507 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
512 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
513 const MachineOperand &MO1 = MI->getOperand(Op);
514 const MachineOperand &MO2 = MI->getOperand(Op+1);
517 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
518 assert(ImmOffs && "Malformed indexed load / store!");
520 << (char)ARM_AM::getAM2Op(MO2.getImm())
525 O << (char)ARM_AM::getAM2Op(MO2.getImm())
526 << getRegisterName(MO1.getReg());
528 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
530 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
534 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
535 const MachineOperand &MO1 = MI->getOperand(Op);
536 const MachineOperand &MO2 = MI->getOperand(Op+1);
537 const MachineOperand &MO3 = MI->getOperand(Op+2);
539 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
540 O << "[" << getRegisterName(MO1.getReg());
544 << (char)ARM_AM::getAM3Op(MO3.getImm())
545 << getRegisterName(MO2.getReg())
550 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
552 << (char)ARM_AM::getAM3Op(MO3.getImm())
557 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
558 const MachineOperand &MO1 = MI->getOperand(Op);
559 const MachineOperand &MO2 = MI->getOperand(Op+1);
562 O << (char)ARM_AM::getAM3Op(MO2.getImm())
563 << getRegisterName(MO1.getReg());
567 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
568 assert(ImmOffs && "Malformed indexed load / store!");
570 << (char)ARM_AM::getAM3Op(MO2.getImm())
574 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
575 const char *Modifier) {
576 const MachineOperand &MO1 = MI->getOperand(Op);
577 const MachineOperand &MO2 = MI->getOperand(Op+1);
578 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
579 if (Modifier && strcmp(Modifier, "submode") == 0) {
580 if (MO1.getReg() == ARM::SP) {
582 bool isLDM = (MI->getOpcode() == ARM::LDM ||
583 MI->getOpcode() == ARM::LDM_RET ||
584 MI->getOpcode() == ARM::t2LDM ||
585 MI->getOpcode() == ARM::t2LDM_RET);
586 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
588 O << ARM_AM::getAMSubModeStr(Mode);
589 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
590 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
591 if (Mode == ARM_AM::ia)
594 printOperand(MI, Op);
595 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
600 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
601 const char *Modifier) {
602 const MachineOperand &MO1 = MI->getOperand(Op);
603 const MachineOperand &MO2 = MI->getOperand(Op+1);
605 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
606 printOperand(MI, Op);
610 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
612 if (Modifier && strcmp(Modifier, "submode") == 0) {
613 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
614 if (MO1.getReg() == ARM::SP) {
615 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
616 MI->getOpcode() == ARM::FLDMS);
617 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
619 O << ARM_AM::getAMSubModeStr(Mode);
621 } else if (Modifier && strcmp(Modifier, "base") == 0) {
622 // Used for FSTM{D|S} and LSTM{D|S} operations.
623 O << getRegisterName(MO1.getReg());
624 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
629 O << "[" << getRegisterName(MO1.getReg());
631 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
633 << (char)ARM_AM::getAM5Op(MO2.getImm())
639 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
640 const MachineOperand &MO1 = MI->getOperand(Op);
641 const MachineOperand &MO2 = MI->getOperand(Op+1);
642 const MachineOperand &MO3 = MI->getOperand(Op+2);
644 // FIXME: No support yet for specifying alignment.
645 O << "[" << getRegisterName(MO1.getReg()) << "]";
647 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
648 if (MO2.getReg() == 0)
651 O << ", " << getRegisterName(MO2.getReg());
655 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
656 const char *Modifier) {
657 if (Modifier && strcmp(Modifier, "label") == 0) {
658 printPCLabel(MI, Op+1);
662 const MachineOperand &MO1 = MI->getOperand(Op);
663 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
664 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
668 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
669 const MachineOperand &MO = MI->getOperand(Op);
670 uint32_t v = ~MO.getImm();
671 int32_t lsb = CountTrailingZeros_32(v);
672 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
673 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
674 O << "#" << lsb << ", #" << width;
677 //===--------------------------------------------------------------------===//
680 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
681 // (3 - the number of trailing zeros) is the number of then / else.
682 unsigned Mask = MI->getOperand(Op).getImm();
683 unsigned NumTZ = CountTrailingZeros_32(Mask);
684 assert(NumTZ <= 3 && "Invalid IT mask!");
685 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
686 bool T = (Mask & (1 << Pos)) == 0;
695 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
696 const MachineOperand &MO1 = MI->getOperand(Op);
697 const MachineOperand &MO2 = MI->getOperand(Op+1);
698 O << "[" << getRegisterName(MO1.getReg());
699 O << ", " << getRegisterName(MO2.getReg()) << "]";
703 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
705 const MachineOperand &MO1 = MI->getOperand(Op);
706 const MachineOperand &MO2 = MI->getOperand(Op+1);
707 const MachineOperand &MO3 = MI->getOperand(Op+2);
709 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
710 printOperand(MI, Op);
714 O << "[" << getRegisterName(MO1.getReg());
716 O << ", " << getRegisterName(MO3.getReg());
717 else if (unsigned ImmOffs = MO2.getImm()) {
718 O << ", #" << ImmOffs;
726 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
727 printThumbAddrModeRI5Operand(MI, Op, 1);
730 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
731 printThumbAddrModeRI5Operand(MI, Op, 2);
734 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
735 printThumbAddrModeRI5Operand(MI, Op, 4);
738 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
739 const MachineOperand &MO1 = MI->getOperand(Op);
740 const MachineOperand &MO2 = MI->getOperand(Op+1);
741 O << "[" << getRegisterName(MO1.getReg());
742 if (unsigned ImmOffs = MO2.getImm())
743 O << ", #" << ImmOffs << " * 4";
747 //===--------------------------------------------------------------------===//
749 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
750 // register with shift forms.
752 // REG IMM, SH_OPC - e.g. R5, LSL #3
753 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
754 const MachineOperand &MO1 = MI->getOperand(OpNum);
755 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
757 unsigned Reg = MO1.getReg();
758 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
759 O << getRegisterName(Reg);
761 // Print the shift opc.
763 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
766 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
767 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
770 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
772 const MachineOperand &MO1 = MI->getOperand(OpNum);
773 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
775 O << "[" << getRegisterName(MO1.getReg());
777 unsigned OffImm = MO2.getImm();
778 if (OffImm) // Don't print +0.
779 O << ", #+" << OffImm;
783 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
785 const MachineOperand &MO1 = MI->getOperand(OpNum);
786 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
788 O << "[" << getRegisterName(MO1.getReg());
790 int32_t OffImm = (int32_t)MO2.getImm();
793 O << ", #-" << -OffImm;
795 O << ", #+" << OffImm;
799 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
801 const MachineOperand &MO1 = MI->getOperand(OpNum);
802 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
804 O << "[" << getRegisterName(MO1.getReg());
806 int32_t OffImm = (int32_t)MO2.getImm() / 4;
809 O << ", #-" << -OffImm << " * 4";
811 O << ", #+" << OffImm << " * 4";
815 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
817 const MachineOperand &MO1 = MI->getOperand(OpNum);
818 int32_t OffImm = (int32_t)MO1.getImm();
821 O << "#-" << -OffImm;
826 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
828 const MachineOperand &MO1 = MI->getOperand(OpNum);
829 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
830 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
832 O << "[" << getRegisterName(MO1.getReg());
834 assert(MO2.getReg() && "Invalid so_reg load / store address!");
835 O << ", " << getRegisterName(MO2.getReg());
837 unsigned ShAmt = MO3.getImm();
839 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
840 O << ", lsl #" << ShAmt;
846 //===--------------------------------------------------------------------===//
848 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
849 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
851 O << ARMCondCodeToString(CC);
854 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
855 unsigned Reg = MI->getOperand(OpNum).getReg();
857 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
862 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
863 int Id = (int)MI->getOperand(OpNum).getImm();
864 O << MAI->getPrivateGlobalPrefix()
865 << "PC" << getFunctionNumber() << "_" << Id;
868 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
870 // Always skip the first operand, it's the optional (and implicit writeback).
871 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
872 if (MI->getOperand(i).isImplicit())
874 if ((int)i != OpNum+1) O << ", ";
880 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
881 const char *Modifier) {
882 assert(Modifier && "This operand only works with a modifier!");
883 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
885 if (!strcmp(Modifier, "label")) {
886 unsigned ID = MI->getOperand(OpNum).getImm();
887 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
888 << '_' << ID << ":\n";
890 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
891 unsigned CPI = MI->getOperand(OpNum).getIndex();
893 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
895 if (MCPE.isMachineConstantPoolEntry()) {
896 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
898 EmitGlobalConstant(MCPE.Val.ConstVal);
903 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
904 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
906 const MachineOperand &MO1 = MI->getOperand(OpNum);
907 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
908 unsigned JTI = MO1.getIndex();
909 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
910 << '_' << JTI << '_' << MO2.getImm() << ":\n";
912 const char *JTEntryDirective = MAI->getData32bitsDirective();
914 const MachineFunction *MF = MI->getParent()->getParent();
915 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
916 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
917 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
918 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
919 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
920 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
921 MachineBasicBlock *MBB = JTBBs[i];
922 bool isNew = JTSets.insert(MBB);
925 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
927 O << JTEntryDirective << ' ';
929 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
930 << '_' << JTI << '_' << MO2.getImm()
931 << "_set_" << MBB->getNumber();
932 else if (TM.getRelocationModel() == Reloc::PIC_) {
933 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
934 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
935 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
937 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
944 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
945 const MachineOperand &MO1 = MI->getOperand(OpNum);
946 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
947 unsigned JTI = MO1.getIndex();
948 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
949 << '_' << JTI << '_' << MO2.getImm() << ":\n";
951 const MachineFunction *MF = MI->getParent()->getParent();
952 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
953 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
954 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
955 bool ByteOffset = false, HalfWordOffset = false;
956 if (MI->getOpcode() == ARM::t2TBB)
958 else if (MI->getOpcode() == ARM::t2TBH)
959 HalfWordOffset = true;
961 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
962 MachineBasicBlock *MBB = JTBBs[i];
964 O << MAI->getData8bitsDirective();
965 else if (HalfWordOffset)
966 O << MAI->getData16bitsDirective();
967 if (ByteOffset || HalfWordOffset) {
969 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
970 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
971 << '_' << JTI << '_' << MO2.getImm() << ")/2";
974 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
980 // Make sure the instruction that follows TBB is 2-byte aligned.
981 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
982 if (ByteOffset && (JTBBs.size() & 1)) {
988 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
989 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
990 if (MI->getOpcode() == ARM::t2TBH)
995 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
996 O << MI->getOperand(OpNum).getImm();
999 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1000 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1001 O << '#' << ARM::getVFPf32Imm(FP->getValueAPF());
1003 O.PadToColumn(MAI->getCommentColumn());
1004 O << MAI->getCommentString() << ' ';
1005 WriteAsOperand(O, FP, /*PrintType=*/false);
1009 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1010 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1011 O << '#' << ARM::getVFPf64Imm(FP->getValueAPF());
1013 O.PadToColumn(MAI->getCommentColumn());
1014 O << MAI->getCommentString() << ' ';
1015 WriteAsOperand(O, FP, /*PrintType=*/false);
1019 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1020 unsigned AsmVariant, const char *ExtraCode){
1021 // Does this asm operand have a single letter operand modifier?
1022 if (ExtraCode && ExtraCode[0]) {
1023 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1025 switch (ExtraCode[0]) {
1026 default: return true; // Unknown modifier.
1027 case 'a': // Print as a memory address.
1028 if (MI->getOperand(OpNum).isReg()) {
1029 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1033 case 'c': // Don't print "#" before an immediate operand.
1034 if (!MI->getOperand(OpNum).isImm())
1036 printNoHashImmediate(MI, OpNum);
1038 case 'P': // Print a VFP double precision register.
1039 printOperand(MI, OpNum);
1042 if (TM.getTargetData()->isLittleEndian())
1046 if (TM.getTargetData()->isBigEndian())
1049 case 'H': // Write second word of DI / DF reference.
1050 // Verify that this operand has two consecutive registers.
1051 if (!MI->getOperand(OpNum).isReg() ||
1052 OpNum+1 == MI->getNumOperands() ||
1053 !MI->getOperand(OpNum+1).isReg())
1055 ++OpNum; // Return the high-part.
1059 printOperand(MI, OpNum);
1063 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1064 unsigned OpNum, unsigned AsmVariant,
1065 const char *ExtraCode) {
1066 if (ExtraCode && ExtraCode[0])
1067 return true; // Unknown modifier.
1069 const MachineOperand &MO = MI->getOperand(OpNum);
1070 assert(MO.isReg() && "unexpected inline asm memory operand");
1071 O << "[" << getRegisterName(MO.getReg()) << "]";
1075 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1078 // Call the autogenerated instruction printer routines.
1079 processDebugLoc(MI, true);
1082 printInstructionThroughMCStreamer(MI);
1084 int Opc = MI->getOpcode();
1085 if (Opc == ARM::CONSTPOOL_ENTRY)
1088 printInstruction(MI);
1091 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1094 processDebugLoc(MI, false);
1097 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1098 if (Subtarget->isTargetDarwin()) {
1099 Reloc::Model RelocM = TM.getRelocationModel();
1100 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1101 // Declare all the text sections up front (before the DWARF sections
1102 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1103 // them together at the beginning of the object file. This helps
1104 // avoid out-of-range branches that are due a fundamental limitation of
1105 // the way symbol offsets are encoded with the current Darwin ARM
1107 TargetLoweringObjectFileMachO &TLOFMacho =
1108 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1109 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1110 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1111 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1112 if (RelocM == Reloc::DynamicNoPIC) {
1113 const MCSection *sect =
1114 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1115 MCSectionMachO::S_SYMBOL_STUBS,
1116 12, SectionKind::getText());
1117 OutStreamer.SwitchSection(sect);
1119 const MCSection *sect =
1120 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1121 MCSectionMachO::S_SYMBOL_STUBS,
1122 16, SectionKind::getText());
1123 OutStreamer.SwitchSection(sect);
1128 // Use unified assembler syntax mode for Thumb.
1129 if (Subtarget->isThumb())
1130 O << "\t.syntax unified\n";
1132 // Emit ARM Build Attributes
1133 if (Subtarget->isTargetELF()) {
1135 std::string CPUString = Subtarget->getCPUString();
1136 if (CPUString != "generic")
1137 O << "\t.cpu " << CPUString << '\n';
1139 // FIXME: Emit FPU type
1140 if (Subtarget->hasVFP2())
1141 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1143 // Signal various FP modes.
1145 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1146 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1148 if (FiniteOnlyFPMath())
1149 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1151 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1153 // 8-bytes alignment stuff.
1154 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1155 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1157 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1158 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1159 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1160 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1162 // FIXME: Should we signal R9 usage?
1166 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1167 const TargetData *TD = TM.getTargetData();
1169 if (!GVar->hasInitializer()) // External global require no code
1172 // Check to see if this is a special global used by LLVM, if so, emit it.
1174 if (EmitSpecialLLVMGlobal(GVar)) {
1175 if (Subtarget->isTargetDarwin() &&
1176 TM.getRelocationModel() == Reloc::Static) {
1177 if (GVar->getName() == "llvm.global_ctors")
1178 O << ".reference .constructors_used\n";
1179 else if (GVar->getName() == "llvm.global_dtors")
1180 O << ".reference .destructors_used\n";
1185 std::string name = Mang->getMangledName(GVar);
1186 Constant *C = GVar->getInitializer();
1187 const Type *Type = C->getType();
1188 unsigned Size = TD->getTypeAllocSize(Type);
1189 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1190 bool isDarwin = Subtarget->isTargetDarwin();
1192 printVisibility(name, GVar->getVisibility());
1194 if (Subtarget->isTargetELF())
1195 O << "\t.type " << name << ",%object\n";
1197 const MCSection *TheSection =
1198 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1199 OutStreamer.SwitchSection(TheSection);
1201 // FIXME: get this stuff from section kind flags.
1202 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1203 // Don't put things that should go in the cstring section into "comm".
1204 !TheSection->getKind().isMergeableCString()) {
1205 if (GVar->hasExternalLinkage()) {
1206 if (const char *Directive = MAI->getZeroFillDirective()) {
1207 O << "\t.globl\t" << name << "\n";
1208 O << Directive << "__DATA, __common, " << name << ", "
1209 << Size << ", " << Align << "\n";
1214 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1215 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1218 if (GVar->hasLocalLinkage()) {
1219 O << MAI->getLCOMMDirective() << name << "," << Size
1221 } else if (GVar->hasCommonLinkage()) {
1222 O << MAI->getCOMMDirective() << name << "," << Size
1225 OutStreamer.SwitchSection(TheSection);
1226 O << "\t.globl " << name << '\n'
1227 << MAI->getWeakDefDirective() << name << '\n';
1228 EmitAlignment(Align, GVar);
1231 O.PadToColumn(MAI->getCommentColumn());
1232 O << MAI->getCommentString() << ' ';
1233 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1236 EmitGlobalConstant(C);
1239 } else if (MAI->getLCOMMDirective() != NULL) {
1240 if (GVar->hasLocalLinkage()) {
1241 O << MAI->getLCOMMDirective() << name << "," << Size;
1243 O << MAI->getCOMMDirective() << name << "," << Size;
1244 if (MAI->getCOMMDirectiveTakesAlignment())
1245 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1248 if (GVar->hasLocalLinkage())
1249 O << "\t.local\t" << name << "\n";
1250 O << MAI->getCOMMDirective() << name << "," << Size;
1251 if (MAI->getCOMMDirectiveTakesAlignment())
1252 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1255 O.PadToColumn(MAI->getCommentColumn());
1256 O << MAI->getCommentString() << ' ';
1257 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1264 switch (GVar->getLinkage()) {
1265 case GlobalValue::CommonLinkage:
1266 case GlobalValue::LinkOnceAnyLinkage:
1267 case GlobalValue::LinkOnceODRLinkage:
1268 case GlobalValue::WeakAnyLinkage:
1269 case GlobalValue::WeakODRLinkage:
1270 case GlobalValue::LinkerPrivateLinkage:
1272 O << "\t.globl " << name << "\n"
1273 << "\t.weak_definition " << name << "\n";
1275 O << "\t.weak " << name << "\n";
1278 case GlobalValue::AppendingLinkage:
1279 // FIXME: appending linkage variables should go into a section of
1280 // their name or something. For now, just emit them as external.
1281 case GlobalValue::ExternalLinkage:
1282 O << "\t.globl " << name << "\n";
1284 case GlobalValue::PrivateLinkage:
1285 case GlobalValue::InternalLinkage:
1288 llvm_unreachable("Unknown linkage type!");
1291 EmitAlignment(Align, GVar);
1294 O.PadToColumn(MAI->getCommentColumn());
1295 O << MAI->getCommentString() << ' ';
1296 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1299 if (MAI->hasDotTypeDotSizeDirective())
1300 O << "\t.size " << name << ", " << Size << "\n";
1302 EmitGlobalConstant(C);
1307 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1308 if (Subtarget->isTargetDarwin()) {
1309 // All darwin targets use mach-o.
1310 TargetLoweringObjectFileMachO &TLOFMacho =
1311 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1312 MachineModuleInfoMachO &MMIMacho =
1313 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1317 // Output non-lazy-pointers for external and common global variables.
1318 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1320 if (!Stubs.empty()) {
1321 // Switch with ".non_lazy_symbol_pointer" directive.
1322 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1324 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1325 Stubs[i].first->print(O, MAI);
1326 O << ":\n\t.indirect_symbol ";
1327 Stubs[i].second->print(O, MAI);
1328 O << "\n\t.long\t0\n";
1332 Stubs = MMIMacho.GetHiddenGVStubList();
1333 if (!Stubs.empty()) {
1334 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1336 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1337 Stubs[i].first->print(O, MAI);
1339 Stubs[i].second->print(O, MAI);
1344 // Funny Darwin hack: This flag tells the linker that no global symbols
1345 // contain code that falls through to other global symbols (e.g. the obvious
1346 // implementation of multiple entry points). If this doesn't occur, the
1347 // linker can safely perform dead code stripping. Since LLVM never
1348 // generates code that does this, it is always safe to set.
1349 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1353 //===----------------------------------------------------------------------===//
1355 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1356 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1357 switch (MI->getOpcode()) {
1358 case ARM::t2MOVi32imm:
1359 assert(0 && "Should be lowered by thumb2it pass");
1361 case TargetInstrInfo::DBG_LABEL:
1362 case TargetInstrInfo::EH_LABEL:
1363 case TargetInstrInfo::GC_LABEL:
1366 case TargetInstrInfo::KILL:
1369 case TargetInstrInfo::INLINEASM:
1372 case TargetInstrInfo::IMPLICIT_DEF:
1373 printImplicitDef(MI);
1375 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1376 // This is a pseudo op for a label + instruction sequence, which looks like:
1379 // This adds the address of LPC0 to r0.
1382 // FIXME: MOVE TO SHARED PLACE.
1383 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1384 const char *Prefix = MAI->getPrivateGlobalPrefix();
1385 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1386 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1387 OutStreamer.EmitLabel(Label);
1390 // Form and emit tha dd.
1392 AddInst.setOpcode(ARM::ADDrr);
1393 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1394 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1395 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1396 printMCInst(&AddInst);
1399 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1400 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1401 /// in the function. The first operand is the ID# for this instruction, the
1402 /// second is the index into the MachineConstantPool that this is, the third
1403 /// is the size in bytes of this constant pool entry.
1404 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1405 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1409 const char *Prefix = MAI->getPrivateGlobalPrefix();
1410 MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
1411 Twine(getFunctionNumber())+
1412 "_"+ Twine(LabelId));
1413 OutStreamer.EmitLabel(Label);
1415 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1416 if (MCPE.isMachineConstantPoolEntry())
1417 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1419 EmitGlobalConstant(MCPE.Val.ConstVal);
1423 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1424 // This is a hack that lowers as a two instruction sequence.
1425 unsigned DstReg = MI->getOperand(0).getReg();
1426 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1428 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1429 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1433 TmpInst.setOpcode(ARM::MOVi);
1434 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1435 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1438 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1439 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1441 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1442 printMCInst(&TmpInst);
1448 TmpInst.setOpcode(ARM::ORRri);
1449 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1450 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1451 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1453 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1454 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1456 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1457 printMCInst(&TmpInst);
1461 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1462 // This is a hack that lowers as a two instruction sequence.
1463 unsigned DstReg = MI->getOperand(0).getReg();
1464 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1468 TmpInst.setOpcode(ARM::MOVi16);
1469 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1470 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1473 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1474 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1476 printMCInst(&TmpInst);
1482 TmpInst.setOpcode(ARM::MOVTi16);
1483 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1484 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1485 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1488 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1489 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1491 printMCInst(&TmpInst);
1499 MCInstLowering.Lower(MI, TmpInst);
1501 printMCInst(&TmpInst);
1504 //===----------------------------------------------------------------------===//
1505 // Target Registry Stuff
1506 //===----------------------------------------------------------------------===//
1508 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1509 unsigned SyntaxVariant,
1510 const MCAsmInfo &MAI,
1512 if (SyntaxVariant == 0)
1513 return new ARMInstPrinter(O, MAI, false);
1517 // Force static initialization.
1518 extern "C" void LLVMInitializeARMAsmPrinter() {
1519 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1520 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1522 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1523 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);