1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the auto-generated portion of the assembly writer.
26 #define MachineInstr MCInst
27 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
28 #include "ARMGenAsmWriter.inc"
32 static unsigned getDPRSuperRegForSPR(unsigned Reg) {
35 assert(0 && "Unexpected register enum");
36 case ARM::S0: case ARM::S1: return ARM::D0;
37 case ARM::S2: case ARM::S3: return ARM::D1;
38 case ARM::S4: case ARM::S5: return ARM::D2;
39 case ARM::S6: case ARM::S7: return ARM::D3;
40 case ARM::S8: case ARM::S9: return ARM::D4;
41 case ARM::S10: case ARM::S11: return ARM::D5;
42 case ARM::S12: case ARM::S13: return ARM::D6;
43 case ARM::S14: case ARM::S15: return ARM::D7;
44 case ARM::S16: case ARM::S17: return ARM::D8;
45 case ARM::S18: case ARM::S19: return ARM::D9;
46 case ARM::S20: case ARM::S21: return ARM::D10;
47 case ARM::S22: case ARM::S23: return ARM::D11;
48 case ARM::S24: case ARM::S25: return ARM::D12;
49 case ARM::S26: case ARM::S27: return ARM::D13;
50 case ARM::S28: case ARM::S29: return ARM::D14;
51 case ARM::S30: case ARM::S31: return ARM::D15;
55 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
56 // Check for MOVs and print canonical forms, instead.
57 if (MI->getOpcode() == ARM::MOVs) {
58 // FIXME: Thumb variants?
59 const MCOperand &Dst = MI->getOperand(0);
60 const MCOperand &MO1 = MI->getOperand(1);
61 const MCOperand &MO2 = MI->getOperand(2);
62 const MCOperand &MO3 = MI->getOperand(3);
64 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
65 printSBitModifierOperand(MI, 6, O);
66 printPredicateOperand(MI, 4, O);
68 O << '\t' << getRegisterName(Dst.getReg())
69 << ", " << getRegisterName(MO1.getReg());
71 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
77 O << getRegisterName(MO2.getReg());
78 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
80 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
86 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
87 MI->getOperand(0).getReg() == ARM::SP) {
88 const MCOperand &MO1 = MI->getOperand(2);
89 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
91 printPredicateOperand(MI, 3, O);
93 printRegisterList(MI, 5, O);
99 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
100 MI->getOperand(0).getReg() == ARM::SP) {
101 const MCOperand &MO1 = MI->getOperand(2);
102 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
104 printPredicateOperand(MI, 3, O);
106 printRegisterList(MI, 5, O);
112 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
113 MI->getOperand(0).getReg() == ARM::SP) {
114 const MCOperand &MO1 = MI->getOperand(2);
115 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
116 O << '\t' << "vpush";
117 printPredicateOperand(MI, 3, O);
119 printRegisterList(MI, 5, O);
125 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
126 MI->getOperand(0).getReg() == ARM::SP) {
127 const MCOperand &MO1 = MI->getOperand(2);
128 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
130 printPredicateOperand(MI, 3, O);
132 printRegisterList(MI, 5, O);
137 printInstruction(MI, O);
140 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
141 raw_ostream &O, const char *Modifier) {
142 const MCOperand &Op = MI->getOperand(OpNo);
144 unsigned Reg = Op.getReg();
145 if (Modifier && strcmp(Modifier, "lane") == 0) {
146 unsigned RegNum = getARMRegisterNumbering(Reg);
147 unsigned DReg = getDPRSuperRegForSPR(Reg);
148 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
150 O << getRegisterName(Reg);
152 } else if (Op.isImm()) {
153 assert((Modifier && !strcmp(Modifier, "call")) ||
154 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
155 O << '#' << Op.getImm();
157 if (Modifier && Modifier[0] != 0 && strcmp(Modifier, "call") != 0)
158 llvm_unreachable("Unsupported modifier");
159 assert(Op.isExpr() && "unknown operand kind in printOperand");
164 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
165 const MCAsmInfo *MAI) {
166 // Break it up into two parts that make up a shifter immediate.
167 V = ARM_AM::getSOImmVal(V);
168 assert(V != -1 && "Not a valid so_imm value!");
170 unsigned Imm = ARM_AM::getSOImmValImm(V);
171 unsigned Rot = ARM_AM::getSOImmValRot(V);
173 // Print low-level immediate formation info, per
174 // A5.1.3: "Data-processing operands - Immediate".
176 O << "#" << Imm << ", " << Rot;
177 // Pretty printed version.
179 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
186 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
187 /// immediate in bits 0-7.
188 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
190 const MCOperand &MO = MI->getOperand(OpNum);
191 assert(MO.isImm() && "Not a valid so_imm value!");
192 printSOImm(O, MO.getImm(), CommentStream, &MAI);
195 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
196 /// followed by an 'orr' to materialize.
197 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
199 // FIXME: REMOVE this method.
203 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
204 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
206 // REG REG 0,SH_OPC - e.g. R5, ROR R3
207 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
208 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
210 const MCOperand &MO1 = MI->getOperand(OpNum);
211 const MCOperand &MO2 = MI->getOperand(OpNum+1);
212 const MCOperand &MO3 = MI->getOperand(OpNum+2);
214 O << getRegisterName(MO1.getReg());
216 // Print the shift opc.
217 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
218 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
220 O << ' ' << getRegisterName(MO2.getReg());
221 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
222 } else if (ShOpc != ARM_AM::rrx) {
223 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
228 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
230 const MCOperand &MO1 = MI->getOperand(Op);
231 const MCOperand &MO2 = MI->getOperand(Op+1);
232 const MCOperand &MO3 = MI->getOperand(Op+2);
234 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
235 printOperand(MI, Op, O);
239 O << "[" << getRegisterName(MO1.getReg());
242 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
244 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
245 << ARM_AM::getAM2Offset(MO3.getImm());
251 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
252 << getRegisterName(MO2.getReg());
254 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
256 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
261 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
264 const MCOperand &MO1 = MI->getOperand(OpNum);
265 const MCOperand &MO2 = MI->getOperand(OpNum+1);
268 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
270 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
275 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
276 << getRegisterName(MO1.getReg());
278 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
280 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
284 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
286 const MCOperand &MO1 = MI->getOperand(OpNum);
287 const MCOperand &MO2 = MI->getOperand(OpNum+1);
288 const MCOperand &MO3 = MI->getOperand(OpNum+2);
290 O << '[' << getRegisterName(MO1.getReg());
293 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
294 << getRegisterName(MO2.getReg()) << ']';
298 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
300 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
305 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
308 const MCOperand &MO1 = MI->getOperand(OpNum);
309 const MCOperand &MO2 = MI->getOperand(OpNum+1);
312 O << (char)ARM_AM::getAM3Op(MO2.getImm())
313 << getRegisterName(MO1.getReg());
317 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
319 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
324 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
326 const char *Modifier) {
327 const MCOperand &MO2 = MI->getOperand(OpNum+1);
328 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
329 if (Modifier && strcmp(Modifier, "submode") == 0) {
330 O << ARM_AM::getAMSubModeStr(Mode);
331 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
332 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
333 if (Mode == ARM_AM::ia)
336 printOperand(MI, OpNum, O);
340 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
342 const char *Modifier) {
343 const MCOperand &MO1 = MI->getOperand(OpNum);
344 const MCOperand &MO2 = MI->getOperand(OpNum+1);
346 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
347 printOperand(MI, OpNum, O);
351 O << "[" << getRegisterName(MO1.getReg());
353 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
355 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
361 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
363 const MCOperand &MO1 = MI->getOperand(OpNum);
364 const MCOperand &MO2 = MI->getOperand(OpNum+1);
366 O << "[" << getRegisterName(MO1.getReg());
368 // FIXME: Both darwin as and GNU as violate ARM docs here.
369 O << ", :" << (MO2.getImm() << 3);
374 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
377 const MCOperand &MO = MI->getOperand(OpNum);
378 if (MO.getReg() == 0)
381 O << ", " << getRegisterName(MO.getReg());
384 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
386 const char *Modifier) {
387 // All instructions using addrmodepc are pseudos and should have been
388 // handled explicitly in printInstructionThroughMCStreamer(). If one got
389 // here, it wasn't, so something's wrong.
390 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
393 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
396 const MCOperand &MO = MI->getOperand(OpNum);
397 uint32_t v = ~MO.getImm();
398 int32_t lsb = CountTrailingZeros_32(v);
399 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
400 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
401 O << '#' << lsb << ", #" << width;
404 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
406 unsigned val = MI->getOperand(OpNum).getImm();
407 O << ARM_MB::MemBOptToString(val);
410 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
412 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
413 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
415 case ARM_AM::no_shift:
424 assert(0 && "unexpected shift opcode for shift immediate operand");
426 O << ARM_AM::getSORegOffset(ShiftOp);
429 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
432 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
433 if (i != OpNum) O << ", ";
434 O << getRegisterName(MI->getOperand(i).getReg());
439 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
441 const MCOperand &Op = MI->getOperand(OpNum);
442 unsigned option = Op.getImm();
443 unsigned mode = option & 31;
444 bool changemode = option >> 5 & 1;
445 unsigned AIF = option >> 6 & 7;
446 unsigned imod = option >> 9 & 3;
453 if (AIF & 4) O << 'a';
454 if (AIF & 2) O << 'i';
455 if (AIF & 1) O << 'f';
456 if (AIF > 0 && changemode) O << ", ";
462 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
464 const MCOperand &Op = MI->getOperand(OpNum);
465 unsigned Mask = Op.getImm();
468 if (Mask & 8) O << 'f';
469 if (Mask & 4) O << 's';
470 if (Mask & 2) O << 'x';
471 if (Mask & 1) O << 'c';
475 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
477 const MCOperand &Op = MI->getOperand(OpNum);
480 O << '-' << (-Op.getImm() - 1);
485 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
487 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
489 O << ARMCondCodeToString(CC);
492 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
495 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
496 O << ARMCondCodeToString(CC);
499 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
501 if (MI->getOperand(OpNum).getReg()) {
502 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
503 "Expect ARM CPSR register!");
510 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
512 const char *Modifier) {
513 // FIXME: remove this.
517 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
519 O << MI->getOperand(OpNum).getImm();
523 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
525 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
528 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
530 O << "#" << MI->getOperand(OpNum).getImm() * 4;
533 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
535 // (3 - the number of trailing zeros) is the number of then / else.
536 unsigned Mask = MI->getOperand(OpNum).getImm();
537 unsigned CondBit0 = Mask >> 4 & 1;
538 unsigned NumTZ = CountTrailingZeros_32(Mask);
539 assert(NumTZ <= 3 && "Invalid IT mask!");
540 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
541 bool T = ((Mask >> Pos) & 1) == CondBit0;
549 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
551 const MCOperand &MO1 = MI->getOperand(Op);
552 const MCOperand &MO2 = MI->getOperand(Op+1);
553 O << "[" << getRegisterName(MO1.getReg());
554 O << ", " << getRegisterName(MO2.getReg()) << "]";
557 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
560 const MCOperand &MO1 = MI->getOperand(Op);
561 const MCOperand &MO2 = MI->getOperand(Op+1);
562 const MCOperand &MO3 = MI->getOperand(Op+2);
564 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
565 printOperand(MI, Op, O);
569 O << "[" << getRegisterName(MO1.getReg());
571 O << ", " << getRegisterName(MO3.getReg());
572 else if (unsigned ImmOffs = MO2.getImm())
573 O << ", #" << ImmOffs * Scale;
577 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
579 printThumbAddrModeRI5Operand(MI, Op, O, 1);
582 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
584 printThumbAddrModeRI5Operand(MI, Op, O, 2);
587 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
589 printThumbAddrModeRI5Operand(MI, Op, O, 4);
592 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
594 const MCOperand &MO1 = MI->getOperand(Op);
595 const MCOperand &MO2 = MI->getOperand(Op+1);
596 O << "[" << getRegisterName(MO1.getReg());
597 if (unsigned ImmOffs = MO2.getImm())
598 O << ", #" << ImmOffs*4;
602 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
604 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
605 if (MI->getOpcode() == ARM::t2TBH)
610 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
611 // register with shift forms.
613 // REG IMM, SH_OPC - e.g. R5, LSL #3
614 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
616 const MCOperand &MO1 = MI->getOperand(OpNum);
617 const MCOperand &MO2 = MI->getOperand(OpNum+1);
619 unsigned Reg = MO1.getReg();
620 O << getRegisterName(Reg);
622 // Print the shift opc.
623 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
624 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
625 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
626 if (ShOpc != ARM_AM::rrx)
627 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
630 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
633 const MCOperand &MO1 = MI->getOperand(OpNum);
634 const MCOperand &MO2 = MI->getOperand(OpNum+1);
636 O << "[" << getRegisterName(MO1.getReg());
638 unsigned OffImm = MO2.getImm();
639 if (OffImm) // Don't print +0.
640 O << ", #" << OffImm;
644 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
647 const MCOperand &MO1 = MI->getOperand(OpNum);
648 const MCOperand &MO2 = MI->getOperand(OpNum+1);
650 O << "[" << getRegisterName(MO1.getReg());
652 int32_t OffImm = (int32_t)MO2.getImm();
655 O << ", #-" << -OffImm;
657 O << ", #" << OffImm;
661 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
664 const MCOperand &MO1 = MI->getOperand(OpNum);
665 const MCOperand &MO2 = MI->getOperand(OpNum+1);
667 O << "[" << getRegisterName(MO1.getReg());
669 int32_t OffImm = (int32_t)MO2.getImm() / 4;
672 O << ", #-" << -OffImm * 4;
674 O << ", #" << OffImm * 4;
678 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
681 const MCOperand &MO1 = MI->getOperand(OpNum);
682 int32_t OffImm = (int32_t)MO1.getImm();
685 O << "#-" << -OffImm;
690 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
693 const MCOperand &MO1 = MI->getOperand(OpNum);
694 int32_t OffImm = (int32_t)MO1.getImm() / 4;
697 O << "#-" << -OffImm * 4;
699 O << "#" << OffImm * 4;
702 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
705 const MCOperand &MO1 = MI->getOperand(OpNum);
706 const MCOperand &MO2 = MI->getOperand(OpNum+1);
707 const MCOperand &MO3 = MI->getOperand(OpNum+2);
709 O << "[" << getRegisterName(MO1.getReg());
711 assert(MO2.getReg() && "Invalid so_reg load / store address!");
712 O << ", " << getRegisterName(MO2.getReg());
714 unsigned ShAmt = MO3.getImm();
716 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
717 O << ", lsl #" << ShAmt;
722 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
724 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
727 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
729 O << '#' << MI->getOperand(OpNum).getFPImm();
732 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
734 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
736 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
737 O << "#0x" << utohexstr(Val);
740 void ARMInstPrinter::PrintSpecial(const MCInst *MI, raw_ostream &O,
742 if (strcmp(Kind, "comment") == 0)