1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARM.h" // FIXME: FACTOR ENUMS BETTER.
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the auto-generated portion of the assembly writer.
26 #define MachineInstr MCInst
27 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
28 #include "ARMGenAsmWriter.inc"
32 static unsigned NextReg(unsigned Reg) {
35 assert(0 && "Unexpected register enum");
102 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
103 // Check for MOVs and print canonical forms, instead.
104 if (MI->getOpcode() == ARM::MOVs) {
105 const MCOperand &Dst = MI->getOperand(0);
106 const MCOperand &MO1 = MI->getOperand(1);
107 const MCOperand &MO2 = MI->getOperand(2);
108 const MCOperand &MO3 = MI->getOperand(3);
110 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
111 printSBitModifierOperand(MI, 6, O);
112 printPredicateOperand(MI, 4, O);
114 O << '\t' << getRegisterName(Dst.getReg())
115 << ", " << getRegisterName(MO1.getReg());
117 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
123 O << getRegisterName(MO2.getReg());
124 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
126 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
132 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
133 MI->getOperand(0).getReg() == ARM::SP) {
134 const MCOperand &MO1 = MI->getOperand(2);
135 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
137 printPredicateOperand(MI, 3, O);
139 printRegisterList(MI, 5, O);
145 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
146 MI->getOperand(0).getReg() == ARM::SP) {
147 const MCOperand &MO1 = MI->getOperand(2);
148 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
150 printPredicateOperand(MI, 3, O);
152 printRegisterList(MI, 5, O);
158 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
159 MI->getOperand(0).getReg() == ARM::SP) {
160 const MCOperand &MO1 = MI->getOperand(2);
161 if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) {
162 O << '\t' << "vpush";
163 printPredicateOperand(MI, 3, O);
165 printRegisterList(MI, 5, O);
171 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
172 MI->getOperand(0).getReg() == ARM::SP) {
173 const MCOperand &MO1 = MI->getOperand(2);
174 if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) {
176 printPredicateOperand(MI, 3, O);
178 printRegisterList(MI, 5, O);
183 printInstruction(MI, O);
186 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
187 raw_ostream &O, const char *Modifier) {
188 const MCOperand &Op = MI->getOperand(OpNo);
190 unsigned Reg = Op.getReg();
191 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
192 O << '{' << getRegisterName(Reg) << ", "
193 << getRegisterName(NextReg(Reg)) << '}';
195 // FIXME: Breaks e.g. ARM/vmul.ll.
198 unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0);
199 unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1);
201 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
204 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
207 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
208 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
209 &ARM::DPR_VFP2RegClass);
210 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
213 O << getRegisterName(Reg);
215 } else if (Op.isImm()) {
216 assert((Modifier && !strcmp(Modifier, "call")) ||
217 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
218 O << '#' << Op.getImm();
220 if (Modifier && Modifier[0] != 0 && strcmp(Modifier, "call") != 0)
221 llvm_unreachable("Unsupported modifier");
222 assert(Op.isExpr() && "unknown operand kind in printOperand");
227 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
228 const MCAsmInfo *MAI) {
229 // Break it up into two parts that make up a shifter immediate.
230 V = ARM_AM::getSOImmVal(V);
231 assert(V != -1 && "Not a valid so_imm value!");
233 unsigned Imm = ARM_AM::getSOImmValImm(V);
234 unsigned Rot = ARM_AM::getSOImmValRot(V);
236 // Print low-level immediate formation info, per
237 // A5.1.3: "Data-processing operands - Immediate".
239 O << "#" << Imm << ", " << Rot;
240 // Pretty printed version.
242 O << ' ' << MAI->getCommentString()
243 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
250 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
251 /// immediate in bits 0-7.
252 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
254 const MCOperand &MO = MI->getOperand(OpNum);
255 assert(MO.isImm() && "Not a valid so_imm value!");
256 printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
259 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
260 /// followed by an 'orr' to materialize.
261 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
263 // FIXME: REMOVE this method.
267 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
268 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
270 // REG REG 0,SH_OPC - e.g. R5, ROR R3
271 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
272 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
274 const MCOperand &MO1 = MI->getOperand(OpNum);
275 const MCOperand &MO2 = MI->getOperand(OpNum+1);
276 const MCOperand &MO3 = MI->getOperand(OpNum+2);
278 O << getRegisterName(MO1.getReg());
280 // Print the shift opc.
281 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
282 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
284 O << ' ' << getRegisterName(MO2.getReg());
285 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
286 } else if (ShOpc != ARM_AM::rrx) {
287 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
292 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
294 const MCOperand &MO1 = MI->getOperand(Op);
295 const MCOperand &MO2 = MI->getOperand(Op+1);
296 const MCOperand &MO3 = MI->getOperand(Op+2);
298 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
299 printOperand(MI, Op, O);
303 O << "[" << getRegisterName(MO1.getReg());
306 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
308 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
309 << ARM_AM::getAM2Offset(MO3.getImm());
315 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
316 << getRegisterName(MO2.getReg());
318 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
320 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
325 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
328 const MCOperand &MO1 = MI->getOperand(OpNum);
329 const MCOperand &MO2 = MI->getOperand(OpNum+1);
332 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
334 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
339 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
340 << getRegisterName(MO1.getReg());
342 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
344 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
348 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
350 const MCOperand &MO1 = MI->getOperand(OpNum);
351 const MCOperand &MO2 = MI->getOperand(OpNum+1);
352 const MCOperand &MO3 = MI->getOperand(OpNum+2);
354 O << '[' << getRegisterName(MO1.getReg());
357 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
358 << getRegisterName(MO2.getReg()) << ']';
362 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
364 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
369 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
372 const MCOperand &MO1 = MI->getOperand(OpNum);
373 const MCOperand &MO2 = MI->getOperand(OpNum+1);
376 O << (char)ARM_AM::getAM3Op(MO2.getImm())
377 << getRegisterName(MO1.getReg());
381 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
383 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
388 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
390 const char *Modifier) {
391 const MCOperand &MO2 = MI->getOperand(OpNum+1);
392 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
393 if (Modifier && strcmp(Modifier, "submode") == 0) {
394 O << ARM_AM::getAMSubModeStr(Mode);
395 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
396 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
397 if (Mode == ARM_AM::ia)
400 printOperand(MI, OpNum, O);
404 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
406 const char *Modifier) {
407 const MCOperand &MO1 = MI->getOperand(OpNum);
408 const MCOperand &MO2 = MI->getOperand(OpNum+1);
410 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
411 printOperand(MI, OpNum, O);
415 if (Modifier && strcmp(Modifier, "submode") == 0) {
416 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
417 O << ARM_AM::getAMSubModeStr(Mode);
419 } else if (Modifier && strcmp(Modifier, "base") == 0) {
420 // Used for FSTM{D|S} and LSTM{D|S} operations.
421 O << getRegisterName(MO1.getReg());
425 O << "[" << getRegisterName(MO1.getReg());
427 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
429 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
435 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
437 const MCOperand &MO1 = MI->getOperand(OpNum);
438 const MCOperand &MO2 = MI->getOperand(OpNum+1);
440 O << "[" << getRegisterName(MO1.getReg());
442 // FIXME: Both darwin as and GNU as violate ARM docs here.
443 O << ", :" << (MO2.getImm() << 3);
448 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
451 const MCOperand &MO = MI->getOperand(OpNum);
452 if (MO.getReg() == 0)
455 O << ", " << getRegisterName(MO.getReg());
458 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
460 const char *Modifier) {
461 assert(0 && "FIXME: Implement printAddrModePCOperand");
464 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
467 const MCOperand &MO = MI->getOperand(OpNum);
468 uint32_t v = ~MO.getImm();
469 int32_t lsb = CountTrailingZeros_32(v);
470 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
471 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
472 O << '#' << lsb << ", #" << width;
475 void ARMInstPrinter::printSatShiftOperand(const MCInst *MI, unsigned OpNum,
477 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
478 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
480 case ARM_AM::no_shift:
489 assert(0 && "unexpected shift opcode for saturate shift operand");
491 O << ARM_AM::getSORegOffset(ShiftOp);
494 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
497 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
498 if (i != OpNum) O << ", ";
499 O << getRegisterName(MI->getOperand(i).getReg());
504 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
506 const MCOperand &Op = MI->getOperand(OpNum);
507 unsigned option = Op.getImm();
508 unsigned mode = option & 31;
509 bool changemode = option >> 5 & 1;
510 unsigned AIF = option >> 6 & 7;
511 unsigned imod = option >> 9 & 3;
518 if (AIF & 4) O << 'a';
519 if (AIF & 2) O << 'i';
520 if (AIF & 1) O << 'f';
521 if (AIF > 0 && changemode) O << ", ";
527 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
529 const MCOperand &Op = MI->getOperand(OpNum);
530 unsigned Mask = Op.getImm();
533 if (Mask & 8) O << 'f';
534 if (Mask & 4) O << 's';
535 if (Mask & 2) O << 'x';
536 if (Mask & 1) O << 'c';
540 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
542 const MCOperand &Op = MI->getOperand(OpNum);
545 O << '-' << (-Op.getImm() - 1);
550 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
552 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
554 O << ARMCondCodeToString(CC);
557 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
560 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
561 O << ARMCondCodeToString(CC);
564 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
566 if (MI->getOperand(OpNum).getReg()) {
567 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
568 "Expect ARM CPSR register!");
575 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
577 const char *Modifier) {
578 // FIXME: remove this.
582 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
584 O << MI->getOperand(OpNum).getImm();
588 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
590 // FIXME: remove this.
594 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
596 O << "#" << MI->getOperand(OpNum).getImm() * 4;
599 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
601 // (3 - the number of trailing zeros) is the number of then / else.
602 unsigned Mask = MI->getOperand(OpNum).getImm();
603 unsigned CondBit0 = Mask >> 4 & 1;
604 unsigned NumTZ = CountTrailingZeros_32(Mask);
605 assert(NumTZ <= 3 && "Invalid IT mask!");
606 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
607 bool T = ((Mask >> Pos) & 1) == CondBit0;
615 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
617 const MCOperand &MO1 = MI->getOperand(Op);
618 const MCOperand &MO2 = MI->getOperand(Op+1);
619 O << "[" << getRegisterName(MO1.getReg());
620 O << ", " << getRegisterName(MO2.getReg()) << "]";
623 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
626 const MCOperand &MO1 = MI->getOperand(Op);
627 const MCOperand &MO2 = MI->getOperand(Op+1);
628 const MCOperand &MO3 = MI->getOperand(Op+2);
630 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
631 printOperand(MI, Op, O);
635 O << "[" << getRegisterName(MO1.getReg());
637 O << ", " << getRegisterName(MO3.getReg());
638 else if (unsigned ImmOffs = MO2.getImm())
639 O << ", #" << ImmOffs * Scale;
643 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
645 printThumbAddrModeRI5Operand(MI, Op, O, 1);
648 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
650 printThumbAddrModeRI5Operand(MI, Op, O, 2);
653 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
655 printThumbAddrModeRI5Operand(MI, Op, O, 4);
658 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
660 const MCOperand &MO1 = MI->getOperand(Op);
661 const MCOperand &MO2 = MI->getOperand(Op+1);
662 O << "[" << getRegisterName(MO1.getReg());
663 if (unsigned ImmOffs = MO2.getImm())
664 O << ", #" << ImmOffs*4;
668 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
670 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
671 if (MI->getOpcode() == ARM::t2TBH)
676 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
677 // register with shift forms.
679 // REG IMM, SH_OPC - e.g. R5, LSL #3
680 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
682 const MCOperand &MO1 = MI->getOperand(OpNum);
683 const MCOperand &MO2 = MI->getOperand(OpNum+1);
685 unsigned Reg = MO1.getReg();
686 O << getRegisterName(Reg);
688 // Print the shift opc.
689 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
690 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
691 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
692 if (ShOpc != ARM_AM::rrx)
693 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
696 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
699 const MCOperand &MO1 = MI->getOperand(OpNum);
700 const MCOperand &MO2 = MI->getOperand(OpNum+1);
702 O << "[" << getRegisterName(MO1.getReg());
704 unsigned OffImm = MO2.getImm();
705 if (OffImm) // Don't print +0.
706 O << ", #" << OffImm;
710 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
713 const MCOperand &MO1 = MI->getOperand(OpNum);
714 const MCOperand &MO2 = MI->getOperand(OpNum+1);
716 O << "[" << getRegisterName(MO1.getReg());
718 int32_t OffImm = (int32_t)MO2.getImm();
721 O << ", #-" << -OffImm;
723 O << ", #" << OffImm;
727 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
730 const MCOperand &MO1 = MI->getOperand(OpNum);
731 const MCOperand &MO2 = MI->getOperand(OpNum+1);
733 O << "[" << getRegisterName(MO1.getReg());
735 int32_t OffImm = (int32_t)MO2.getImm() / 4;
738 O << ", #-" << -OffImm * 4;
740 O << ", #" << OffImm * 4;
744 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
747 const MCOperand &MO1 = MI->getOperand(OpNum);
748 int32_t OffImm = (int32_t)MO1.getImm();
751 O << "#-" << -OffImm;
756 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
759 const MCOperand &MO1 = MI->getOperand(OpNum);
760 int32_t OffImm = (int32_t)MO1.getImm() / 4;
763 O << "#-" << -OffImm * 4;
765 O << "#" << OffImm * 4;
768 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
771 const MCOperand &MO1 = MI->getOperand(OpNum);
772 const MCOperand &MO2 = MI->getOperand(OpNum+1);
773 const MCOperand &MO3 = MI->getOperand(OpNum+2);
775 O << "[" << getRegisterName(MO1.getReg());
777 assert(MO2.getReg() && "Invalid so_reg load / store address!");
778 O << ", " << getRegisterName(MO2.getReg());
780 unsigned ShAmt = MO3.getImm();
782 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
783 O << ", lsl #" << ShAmt;
788 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
790 O << '#' << MI->getOperand(OpNum).getImm();
793 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
795 O << '#' << MI->getOperand(OpNum).getImm();
798 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
800 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
802 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
803 O << "#0x" << utohexstr(Val);