1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/LEB128.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI) :
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
103 const MemoryObject ®ion,
105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110 class ThumbDisassembler : public MCDisassembler {
112 /// Constructor - Initializes the disassembler.
114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
118 ~ThumbDisassembler() {
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
124 const MemoryObject ®ion,
126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
130 mutable ITStatus ITBlock;
131 DecodeStatus AddThumbPredicate(MCInst&) const;
132 void UpdateThumbVFPPredicate(MCInst&) const;
136 static bool Check(DecodeStatus &Out, DecodeStatus In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
141 case MCDisassembler::SoftFail:
144 case MCDisassembler::Fail:
148 llvm_unreachable("Invalid DecodeStatus!");
152 // Forward declare these because the autogenerated code will reference them.
153 // Definitions are further down.
154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
160 unsigned RegNo, uint64_t Address,
161 const void *Decoder);
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
179 const void *Decoder);
180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
221 const void *Decoder);
222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
327 const void *Decoder);
330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void* Decoder);
356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void* Decoder);
358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
399 uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
401 uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
404 uint64_t Address, const void *Decoder);
405 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
406 uint64_t Address, const void *Decoder);
407 #include "ARMGenDisassemblerTables.inc"
409 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
410 return new ARMDisassembler(STI);
413 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
414 return new ThumbDisassembler(STI);
417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
418 const MemoryObject &Region,
421 raw_ostream &cs) const {
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
429 // We want to read exactly 4 bytes of data.
430 if (Region.readBytes(Address, 4, bytes) == -1) {
432 return MCDisassembler::Fail;
435 // Encoded as a small-endian 32-bit word in the stream.
436 uint32_t insn = (bytes[3] << 24) |
441 // Calling the auto-generated decoder function.
442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
444 if (result != MCDisassembler::Fail) {
449 // VFP and NEON instructions, similarly, are shared between ARM
452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
453 if (result != MCDisassembler::Fail) {
459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
460 if (result != MCDisassembler::Fail) {
466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
468 if (result != MCDisassembler::Fail) {
470 // Add a fake predicate operand, because we share these instruction
471 // definitions with Thumb2 where these instructions are predicable.
472 if (!DecodePredicateOperand(MI, 0xE, Address, this))
473 return MCDisassembler::Fail;
478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
480 if (result != MCDisassembler::Fail) {
482 // Add a fake predicate operand, because we share these instruction
483 // definitions with Thumb2 where these instructions are predicable.
484 if (!DecodePredicateOperand(MI, 0xE, Address, this))
485 return MCDisassembler::Fail;
490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
492 if (result != MCDisassembler::Fail) {
494 // Add a fake predicate operand, because we share these instruction
495 // definitions with Thumb2 where these instructions are predicable.
496 if (!DecodePredicateOperand(MI, 0xE, Address, this))
497 return MCDisassembler::Fail;
504 return MCDisassembler::Fail;
508 extern const MCInstrDesc ARMInsts[];
511 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
512 /// immediate Value in the MCInst. The immediate Value has had any PC
513 /// adjustment made by the caller. If the instruction is a branch instruction
514 /// then isBranch is true, else false. If the getOpInfo() function was set as
515 /// part of the setupForSymbolicDisassembly() call then that function is called
516 /// to get any symbolic information at the Address for this instruction. If
517 /// that returns non-zero then the symbolic information it returns is used to
518 /// create an MCExpr and that is added as an operand to the MCInst. If
519 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
520 /// Value is done and if a symbol is found an MCExpr is created with that, else
521 /// an MCExpr with Value is created. This function returns true if it adds an
522 /// operand to the MCInst and false otherwise.
523 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
524 bool isBranch, uint64_t InstSize,
525 MCInst &MI, const void *Decoder) {
526 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
527 // FIXME: Does it make sense for value to be negative?
528 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
529 /* Offset */ 0, InstSize);
532 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
533 /// referenced by a load instruction with the base register that is the Pc.
534 /// These can often be values in a literal pool near the Address of the
535 /// instruction. The Address of the instruction and its immediate Value are
536 /// used as a possible literal pool entry. The SymbolLookUp call back will
537 /// return the name of a symbol referenced by the literal pool's entry if
538 /// the referenced address is that of a symbol. Or it will return a pointer to
539 /// a literal 'C' string if the referenced address of the literal pool's entry
540 /// is an address into a section with 'C' string literals.
541 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
542 const void *Decoder) {
543 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
544 Dis->tryAddingPcLoadReferenceComment(Value, Address);
547 // Thumb1 instructions don't have explicit S bits. Rather, they
548 // implicitly set CPSR. Since it's not represented in the encoding, the
549 // auto-generated decoder won't inject the CPSR operand. We need to fix
550 // that as a post-pass.
551 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
552 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
553 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
554 MCInst::iterator I = MI.begin();
555 for (unsigned i = 0; i < NumOps; ++i, ++I) {
556 if (I == MI.end()) break;
557 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
558 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
559 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
564 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
567 // Most Thumb instructions don't have explicit predicates in the
568 // encoding, but rather get their predicates from IT context. We need
569 // to fix up the predicate operands using this context information as a
571 MCDisassembler::DecodeStatus
572 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
573 MCDisassembler::DecodeStatus S = Success;
575 // A few instructions actually have predicates encoded in them. Don't
576 // try to overwrite it if we're seeing one of those.
577 switch (MI.getOpcode()) {
588 // Some instructions (mostly conditional branches) are not
589 // allowed in IT blocks.
590 if (ITBlock.instrInITBlock())
599 // Some instructions (mostly unconditional branches) can
600 // only appears at the end of, or outside of, an IT.
601 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
608 // If we're in an IT block, base the predicate on that. Otherwise,
609 // assume a predicate of AL.
611 CC = ITBlock.getITCC();
614 if (ITBlock.instrInITBlock())
615 ITBlock.advanceITState();
617 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
618 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
619 MCInst::iterator I = MI.begin();
620 for (unsigned i = 0; i < NumOps; ++i, ++I) {
621 if (I == MI.end()) break;
622 if (OpInfo[i].isPredicate()) {
623 I = MI.insert(I, MCOperand::CreateImm(CC));
626 MI.insert(I, MCOperand::CreateReg(0));
628 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
633 I = MI.insert(I, MCOperand::CreateImm(CC));
636 MI.insert(I, MCOperand::CreateReg(0));
638 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
643 // Thumb VFP instructions are a special case. Because we share their
644 // encodings between ARM and Thumb modes, and they are predicable in ARM
645 // mode, the auto-generated decoder will give them an (incorrect)
646 // predicate operand. We need to rewrite these operands based on the IT
647 // context as a post-pass.
648 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
650 CC = ITBlock.getITCC();
651 if (ITBlock.instrInITBlock())
652 ITBlock.advanceITState();
654 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
655 MCInst::iterator I = MI.begin();
656 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
657 for (unsigned i = 0; i < NumOps; ++i, ++I) {
658 if (OpInfo[i].isPredicate() ) {
664 I->setReg(ARM::CPSR);
670 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
671 const MemoryObject &Region,
674 raw_ostream &cs) const {
679 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
680 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
682 // We want to read exactly 2 bytes of data.
683 if (Region.readBytes(Address, 2, bytes) == -1) {
685 return MCDisassembler::Fail;
688 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
689 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
691 if (result != MCDisassembler::Fail) {
693 Check(result, AddThumbPredicate(MI));
698 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
702 bool InITBlock = ITBlock.instrInITBlock();
703 Check(result, AddThumbPredicate(MI));
704 AddThumb1SBit(MI, InITBlock);
709 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
711 if (result != MCDisassembler::Fail) {
714 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
715 // the Thumb predicate.
716 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
717 result = MCDisassembler::SoftFail;
719 Check(result, AddThumbPredicate(MI));
721 // If we find an IT instruction, we need to parse its condition
722 // code and mask operands so that we can apply them correctly
723 // to the subsequent instructions.
724 if (MI.getOpcode() == ARM::t2IT) {
726 unsigned Firstcond = MI.getOperand(0).getImm();
727 unsigned Mask = MI.getOperand(1).getImm();
728 ITBlock.setITState(Firstcond, Mask);
734 // We want to read exactly 4 bytes of data.
735 if (Region.readBytes(Address, 4, bytes) == -1) {
737 return MCDisassembler::Fail;
740 uint32_t insn32 = (bytes[3] << 8) |
745 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
747 if (result != MCDisassembler::Fail) {
749 bool InITBlock = ITBlock.instrInITBlock();
750 Check(result, AddThumbPredicate(MI));
751 AddThumb1SBit(MI, InITBlock);
756 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
758 if (result != MCDisassembler::Fail) {
760 Check(result, AddThumbPredicate(MI));
764 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
766 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
767 if (result != MCDisassembler::Fail) {
769 UpdateThumbVFPPredicate(MI);
775 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
776 if (result != MCDisassembler::Fail) {
781 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
783 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
785 if (result != MCDisassembler::Fail) {
787 Check(result, AddThumbPredicate(MI));
792 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
794 uint32_t NEONLdStInsn = insn32;
795 NEONLdStInsn &= 0xF0FFFFFF;
796 NEONLdStInsn |= 0x04000000;
797 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
799 if (result != MCDisassembler::Fail) {
801 Check(result, AddThumbPredicate(MI));
806 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
808 uint32_t NEONDataInsn = insn32;
809 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
810 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
811 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
812 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
814 if (result != MCDisassembler::Fail) {
816 Check(result, AddThumbPredicate(MI));
822 return MCDisassembler::Fail;
826 extern "C" void LLVMInitializeARMDisassembler() {
827 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
828 createARMDisassembler);
829 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
830 createThumbDisassembler);
833 static const uint16_t GPRDecoderTable[] = {
834 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
835 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
836 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
837 ARM::R12, ARM::SP, ARM::LR, ARM::PC
840 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
841 uint64_t Address, const void *Decoder) {
843 return MCDisassembler::Fail;
845 unsigned Register = GPRDecoderTable[RegNo];
846 Inst.addOperand(MCOperand::CreateReg(Register));
847 return MCDisassembler::Success;
851 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
852 uint64_t Address, const void *Decoder) {
853 DecodeStatus S = MCDisassembler::Success;
856 S = MCDisassembler::SoftFail;
858 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
864 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
865 uint64_t Address, const void *Decoder) {
866 DecodeStatus S = MCDisassembler::Success;
870 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
871 return MCDisassembler::Success;
874 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
878 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
879 uint64_t Address, const void *Decoder) {
881 return MCDisassembler::Fail;
882 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
885 static const uint16_t GPRPairDecoderTable[] = {
886 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
887 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
890 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
891 uint64_t Address, const void *Decoder) {
892 DecodeStatus S = MCDisassembler::Success;
895 return MCDisassembler::Fail;
897 if ((RegNo & 1) || RegNo == 0xe)
898 S = MCDisassembler::SoftFail;
900 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
901 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
905 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
906 uint64_t Address, const void *Decoder) {
907 unsigned Register = 0;
928 return MCDisassembler::Fail;
931 Inst.addOperand(MCOperand::CreateReg(Register));
932 return MCDisassembler::Success;
935 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
936 uint64_t Address, const void *Decoder) {
937 DecodeStatus S = MCDisassembler::Success;
938 if (RegNo == 13 || RegNo == 15)
939 S = MCDisassembler::SoftFail;
940 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
944 static const uint16_t SPRDecoderTable[] = {
945 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
946 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
947 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
948 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
949 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
950 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
951 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
952 ARM::S28, ARM::S29, ARM::S30, ARM::S31
955 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
956 uint64_t Address, const void *Decoder) {
958 return MCDisassembler::Fail;
960 unsigned Register = SPRDecoderTable[RegNo];
961 Inst.addOperand(MCOperand::CreateReg(Register));
962 return MCDisassembler::Success;
965 static const uint16_t DPRDecoderTable[] = {
966 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
967 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
968 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
969 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
970 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
971 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
972 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
973 ARM::D28, ARM::D29, ARM::D30, ARM::D31
976 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
977 uint64_t Address, const void *Decoder) {
979 return MCDisassembler::Fail;
981 unsigned Register = DPRDecoderTable[RegNo];
982 Inst.addOperand(MCOperand::CreateReg(Register));
983 return MCDisassembler::Success;
986 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
987 uint64_t Address, const void *Decoder) {
989 return MCDisassembler::Fail;
990 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
994 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
995 uint64_t Address, const void *Decoder) {
997 return MCDisassembler::Fail;
998 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1001 static const uint16_t QPRDecoderTable[] = {
1002 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1003 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1004 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1005 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1009 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1010 uint64_t Address, const void *Decoder) {
1011 if (RegNo > 31 || (RegNo & 1) != 0)
1012 return MCDisassembler::Fail;
1015 unsigned Register = QPRDecoderTable[RegNo];
1016 Inst.addOperand(MCOperand::CreateReg(Register));
1017 return MCDisassembler::Success;
1020 static const uint16_t DPairDecoderTable[] = {
1021 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1022 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1023 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1024 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1025 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1029 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1030 uint64_t Address, const void *Decoder) {
1032 return MCDisassembler::Fail;
1034 unsigned Register = DPairDecoderTable[RegNo];
1035 Inst.addOperand(MCOperand::CreateReg(Register));
1036 return MCDisassembler::Success;
1039 static const uint16_t DPairSpacedDecoderTable[] = {
1040 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1041 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1042 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1043 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1044 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1045 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1046 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1047 ARM::D28_D30, ARM::D29_D31
1050 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1053 const void *Decoder) {
1055 return MCDisassembler::Fail;
1057 unsigned Register = DPairSpacedDecoderTable[RegNo];
1058 Inst.addOperand(MCOperand::CreateReg(Register));
1059 return MCDisassembler::Success;
1062 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1063 uint64_t Address, const void *Decoder) {
1064 if (Val == 0xF) return MCDisassembler::Fail;
1065 // AL predicate is not allowed on Thumb1 branches.
1066 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1067 return MCDisassembler::Fail;
1068 Inst.addOperand(MCOperand::CreateImm(Val));
1069 if (Val == ARMCC::AL) {
1070 Inst.addOperand(MCOperand::CreateReg(0));
1072 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1073 return MCDisassembler::Success;
1076 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1077 uint64_t Address, const void *Decoder) {
1079 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1081 Inst.addOperand(MCOperand::CreateReg(0));
1082 return MCDisassembler::Success;
1085 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1086 uint64_t Address, const void *Decoder) {
1087 uint32_t imm = Val & 0xFF;
1088 uint32_t rot = (Val & 0xF00) >> 7;
1089 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1090 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1091 return MCDisassembler::Success;
1094 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1095 uint64_t Address, const void *Decoder) {
1096 DecodeStatus S = MCDisassembler::Success;
1098 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1099 unsigned type = fieldFromInstruction(Val, 5, 2);
1100 unsigned imm = fieldFromInstruction(Val, 7, 5);
1102 // Register-immediate
1103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1104 return MCDisassembler::Fail;
1106 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1109 Shift = ARM_AM::lsl;
1112 Shift = ARM_AM::lsr;
1115 Shift = ARM_AM::asr;
1118 Shift = ARM_AM::ror;
1122 if (Shift == ARM_AM::ror && imm == 0)
1123 Shift = ARM_AM::rrx;
1125 unsigned Op = Shift | (imm << 3);
1126 Inst.addOperand(MCOperand::CreateImm(Op));
1131 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1132 uint64_t Address, const void *Decoder) {
1133 DecodeStatus S = MCDisassembler::Success;
1135 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1136 unsigned type = fieldFromInstruction(Val, 5, 2);
1137 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1139 // Register-register
1140 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1141 return MCDisassembler::Fail;
1142 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1143 return MCDisassembler::Fail;
1145 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1148 Shift = ARM_AM::lsl;
1151 Shift = ARM_AM::lsr;
1154 Shift = ARM_AM::asr;
1157 Shift = ARM_AM::ror;
1161 Inst.addOperand(MCOperand::CreateImm(Shift));
1166 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1167 uint64_t Address, const void *Decoder) {
1168 DecodeStatus S = MCDisassembler::Success;
1170 bool writebackLoad = false;
1171 unsigned writebackReg = 0;
1172 switch (Inst.getOpcode()) {
1175 case ARM::LDMIA_UPD:
1176 case ARM::LDMDB_UPD:
1177 case ARM::LDMIB_UPD:
1178 case ARM::LDMDA_UPD:
1179 case ARM::t2LDMIA_UPD:
1180 case ARM::t2LDMDB_UPD:
1181 writebackLoad = true;
1182 writebackReg = Inst.getOperand(0).getReg();
1186 // Empty register lists are not allowed.
1187 if (Val == 0) return MCDisassembler::Fail;
1188 for (unsigned i = 0; i < 16; ++i) {
1189 if (Val & (1 << i)) {
1190 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1191 return MCDisassembler::Fail;
1192 // Writeback not allowed if Rn is in the target list.
1193 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1194 Check(S, MCDisassembler::SoftFail);
1201 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1202 uint64_t Address, const void *Decoder) {
1203 DecodeStatus S = MCDisassembler::Success;
1205 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1206 unsigned regs = fieldFromInstruction(Val, 0, 8);
1208 // In case of unpredictable encoding, tweak the operands.
1209 if (regs == 0 || (Vd + regs) > 32) {
1210 regs = Vd + regs > 32 ? 32 - Vd : regs;
1211 regs = std::max( 1u, regs);
1212 S = MCDisassembler::SoftFail;
1215 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1216 return MCDisassembler::Fail;
1217 for (unsigned i = 0; i < (regs - 1); ++i) {
1218 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1219 return MCDisassembler::Fail;
1225 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1226 uint64_t Address, const void *Decoder) {
1227 DecodeStatus S = MCDisassembler::Success;
1229 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1230 unsigned regs = fieldFromInstruction(Val, 1, 7);
1232 // In case of unpredictable encoding, tweak the operands.
1233 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1234 regs = Vd + regs > 32 ? 32 - Vd : regs;
1235 regs = std::max( 1u, regs);
1236 regs = std::min(16u, regs);
1237 S = MCDisassembler::SoftFail;
1240 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1241 return MCDisassembler::Fail;
1242 for (unsigned i = 0; i < (regs - 1); ++i) {
1243 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1244 return MCDisassembler::Fail;
1250 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1251 uint64_t Address, const void *Decoder) {
1252 // This operand encodes a mask of contiguous zeros between a specified MSB
1253 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1254 // the mask of all bits LSB-and-lower, and then xor them to create
1255 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1256 // create the final mask.
1257 unsigned msb = fieldFromInstruction(Val, 5, 5);
1258 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1260 DecodeStatus S = MCDisassembler::Success;
1262 Check(S, MCDisassembler::SoftFail);
1263 // The check above will cause the warning for the "potentially undefined
1264 // instruction encoding" but we can't build a bad MCOperand value here
1265 // with a lsb > msb or else printing the MCInst will cause a crash.
1269 uint32_t msb_mask = 0xFFFFFFFF;
1270 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1271 uint32_t lsb_mask = (1U << lsb) - 1;
1273 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1277 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1278 uint64_t Address, const void *Decoder) {
1279 DecodeStatus S = MCDisassembler::Success;
1281 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1282 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1283 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1284 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1285 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1286 unsigned U = fieldFromInstruction(Insn, 23, 1);
1288 switch (Inst.getOpcode()) {
1289 case ARM::LDC_OFFSET:
1292 case ARM::LDC_OPTION:
1293 case ARM::LDCL_OFFSET:
1295 case ARM::LDCL_POST:
1296 case ARM::LDCL_OPTION:
1297 case ARM::STC_OFFSET:
1300 case ARM::STC_OPTION:
1301 case ARM::STCL_OFFSET:
1303 case ARM::STCL_POST:
1304 case ARM::STCL_OPTION:
1305 case ARM::t2LDC_OFFSET:
1306 case ARM::t2LDC_PRE:
1307 case ARM::t2LDC_POST:
1308 case ARM::t2LDC_OPTION:
1309 case ARM::t2LDCL_OFFSET:
1310 case ARM::t2LDCL_PRE:
1311 case ARM::t2LDCL_POST:
1312 case ARM::t2LDCL_OPTION:
1313 case ARM::t2STC_OFFSET:
1314 case ARM::t2STC_PRE:
1315 case ARM::t2STC_POST:
1316 case ARM::t2STC_OPTION:
1317 case ARM::t2STCL_OFFSET:
1318 case ARM::t2STCL_PRE:
1319 case ARM::t2STCL_POST:
1320 case ARM::t2STCL_OPTION:
1321 if (coproc == 0xA || coproc == 0xB)
1322 return MCDisassembler::Fail;
1328 Inst.addOperand(MCOperand::CreateImm(coproc));
1329 Inst.addOperand(MCOperand::CreateImm(CRd));
1330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1331 return MCDisassembler::Fail;
1333 switch (Inst.getOpcode()) {
1334 case ARM::t2LDC2_OFFSET:
1335 case ARM::t2LDC2L_OFFSET:
1336 case ARM::t2LDC2_PRE:
1337 case ARM::t2LDC2L_PRE:
1338 case ARM::t2STC2_OFFSET:
1339 case ARM::t2STC2L_OFFSET:
1340 case ARM::t2STC2_PRE:
1341 case ARM::t2STC2L_PRE:
1342 case ARM::LDC2_OFFSET:
1343 case ARM::LDC2L_OFFSET:
1345 case ARM::LDC2L_PRE:
1346 case ARM::STC2_OFFSET:
1347 case ARM::STC2L_OFFSET:
1349 case ARM::STC2L_PRE:
1350 case ARM::t2LDC_OFFSET:
1351 case ARM::t2LDCL_OFFSET:
1352 case ARM::t2LDC_PRE:
1353 case ARM::t2LDCL_PRE:
1354 case ARM::t2STC_OFFSET:
1355 case ARM::t2STCL_OFFSET:
1356 case ARM::t2STC_PRE:
1357 case ARM::t2STCL_PRE:
1358 case ARM::LDC_OFFSET:
1359 case ARM::LDCL_OFFSET:
1362 case ARM::STC_OFFSET:
1363 case ARM::STCL_OFFSET:
1366 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1367 Inst.addOperand(MCOperand::CreateImm(imm));
1369 case ARM::t2LDC2_POST:
1370 case ARM::t2LDC2L_POST:
1371 case ARM::t2STC2_POST:
1372 case ARM::t2STC2L_POST:
1373 case ARM::LDC2_POST:
1374 case ARM::LDC2L_POST:
1375 case ARM::STC2_POST:
1376 case ARM::STC2L_POST:
1377 case ARM::t2LDC_POST:
1378 case ARM::t2LDCL_POST:
1379 case ARM::t2STC_POST:
1380 case ARM::t2STCL_POST:
1382 case ARM::LDCL_POST:
1384 case ARM::STCL_POST:
1388 // The 'option' variant doesn't encode 'U' in the immediate since
1389 // the immediate is unsigned [0,255].
1390 Inst.addOperand(MCOperand::CreateImm(imm));
1394 switch (Inst.getOpcode()) {
1395 case ARM::LDC_OFFSET:
1398 case ARM::LDC_OPTION:
1399 case ARM::LDCL_OFFSET:
1401 case ARM::LDCL_POST:
1402 case ARM::LDCL_OPTION:
1403 case ARM::STC_OFFSET:
1406 case ARM::STC_OPTION:
1407 case ARM::STCL_OFFSET:
1409 case ARM::STCL_POST:
1410 case ARM::STCL_OPTION:
1411 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1412 return MCDisassembler::Fail;
1422 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1423 uint64_t Address, const void *Decoder) {
1424 DecodeStatus S = MCDisassembler::Success;
1426 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1427 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1428 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1429 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1430 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1431 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1432 unsigned P = fieldFromInstruction(Insn, 24, 1);
1433 unsigned W = fieldFromInstruction(Insn, 21, 1);
1435 // On stores, the writeback operand precedes Rt.
1436 switch (Inst.getOpcode()) {
1437 case ARM::STR_POST_IMM:
1438 case ARM::STR_POST_REG:
1439 case ARM::STRB_POST_IMM:
1440 case ARM::STRB_POST_REG:
1441 case ARM::STRT_POST_REG:
1442 case ARM::STRT_POST_IMM:
1443 case ARM::STRBT_POST_REG:
1444 case ARM::STRBT_POST_IMM:
1445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1446 return MCDisassembler::Fail;
1452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1453 return MCDisassembler::Fail;
1455 // On loads, the writeback operand comes after Rt.
1456 switch (Inst.getOpcode()) {
1457 case ARM::LDR_POST_IMM:
1458 case ARM::LDR_POST_REG:
1459 case ARM::LDRB_POST_IMM:
1460 case ARM::LDRB_POST_REG:
1461 case ARM::LDRBT_POST_REG:
1462 case ARM::LDRBT_POST_IMM:
1463 case ARM::LDRT_POST_REG:
1464 case ARM::LDRT_POST_IMM:
1465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1466 return MCDisassembler::Fail;
1472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1473 return MCDisassembler::Fail;
1475 ARM_AM::AddrOpc Op = ARM_AM::add;
1476 if (!fieldFromInstruction(Insn, 23, 1))
1479 bool writeback = (P == 0) || (W == 1);
1480 unsigned idx_mode = 0;
1482 idx_mode = ARMII::IndexModePre;
1483 else if (!P && writeback)
1484 idx_mode = ARMII::IndexModePost;
1486 if (writeback && (Rn == 15 || Rn == Rt))
1487 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1490 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1491 return MCDisassembler::Fail;
1492 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1493 switch( fieldFromInstruction(Insn, 5, 2)) {
1507 return MCDisassembler::Fail;
1509 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1510 if (Opc == ARM_AM::ror && amt == 0)
1512 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1514 Inst.addOperand(MCOperand::CreateImm(imm));
1516 Inst.addOperand(MCOperand::CreateReg(0));
1517 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1518 Inst.addOperand(MCOperand::CreateImm(tmp));
1521 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1522 return MCDisassembler::Fail;
1527 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1528 uint64_t Address, const void *Decoder) {
1529 DecodeStatus S = MCDisassembler::Success;
1531 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1532 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1533 unsigned type = fieldFromInstruction(Val, 5, 2);
1534 unsigned imm = fieldFromInstruction(Val, 7, 5);
1535 unsigned U = fieldFromInstruction(Val, 12, 1);
1537 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1553 if (ShOp == ARM_AM::ror && imm == 0)
1556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1557 return MCDisassembler::Fail;
1558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1559 return MCDisassembler::Fail;
1562 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1564 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1565 Inst.addOperand(MCOperand::CreateImm(shift));
1571 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1572 uint64_t Address, const void *Decoder) {
1573 DecodeStatus S = MCDisassembler::Success;
1575 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1576 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1577 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1578 unsigned type = fieldFromInstruction(Insn, 22, 1);
1579 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1580 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1581 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1582 unsigned W = fieldFromInstruction(Insn, 21, 1);
1583 unsigned P = fieldFromInstruction(Insn, 24, 1);
1584 unsigned Rt2 = Rt + 1;
1586 bool writeback = (W == 1) | (P == 0);
1588 // For {LD,ST}RD, Rt must be even, else undefined.
1589 switch (Inst.getOpcode()) {
1592 case ARM::STRD_POST:
1595 case ARM::LDRD_POST:
1596 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1601 switch (Inst.getOpcode()) {
1604 case ARM::STRD_POST:
1605 if (P == 0 && W == 1)
1606 S = MCDisassembler::SoftFail;
1608 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1609 S = MCDisassembler::SoftFail;
1610 if (type && Rm == 15)
1611 S = MCDisassembler::SoftFail;
1613 S = MCDisassembler::SoftFail;
1614 if (!type && fieldFromInstruction(Insn, 8, 4))
1615 S = MCDisassembler::SoftFail;
1619 case ARM::STRH_POST:
1621 S = MCDisassembler::SoftFail;
1622 if (writeback && (Rn == 15 || Rn == Rt))
1623 S = MCDisassembler::SoftFail;
1624 if (!type && Rm == 15)
1625 S = MCDisassembler::SoftFail;
1629 case ARM::LDRD_POST:
1630 if (type && Rn == 15){
1632 S = MCDisassembler::SoftFail;
1635 if (P == 0 && W == 1)
1636 S = MCDisassembler::SoftFail;
1637 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1638 S = MCDisassembler::SoftFail;
1639 if (!type && writeback && Rn == 15)
1640 S = MCDisassembler::SoftFail;
1641 if (writeback && (Rn == Rt || Rn == Rt2))
1642 S = MCDisassembler::SoftFail;
1646 case ARM::LDRH_POST:
1647 if (type && Rn == 15){
1649 S = MCDisassembler::SoftFail;
1653 S = MCDisassembler::SoftFail;
1654 if (!type && Rm == 15)
1655 S = MCDisassembler::SoftFail;
1656 if (!type && writeback && (Rn == 15 || Rn == Rt))
1657 S = MCDisassembler::SoftFail;
1660 case ARM::LDRSH_PRE:
1661 case ARM::LDRSH_POST:
1663 case ARM::LDRSB_PRE:
1664 case ARM::LDRSB_POST:
1665 if (type && Rn == 15){
1667 S = MCDisassembler::SoftFail;
1670 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1671 S = MCDisassembler::SoftFail;
1672 if (!type && (Rt == 15 || Rm == 15))
1673 S = MCDisassembler::SoftFail;
1674 if (!type && writeback && (Rn == 15 || Rn == Rt))
1675 S = MCDisassembler::SoftFail;
1681 if (writeback) { // Writeback
1683 U |= ARMII::IndexModePre << 9;
1685 U |= ARMII::IndexModePost << 9;
1687 // On stores, the writeback operand precedes Rt.
1688 switch (Inst.getOpcode()) {
1691 case ARM::STRD_POST:
1694 case ARM::STRH_POST:
1695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1696 return MCDisassembler::Fail;
1703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1704 return MCDisassembler::Fail;
1705 switch (Inst.getOpcode()) {
1708 case ARM::STRD_POST:
1711 case ARM::LDRD_POST:
1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1713 return MCDisassembler::Fail;
1720 // On loads, the writeback operand comes after Rt.
1721 switch (Inst.getOpcode()) {
1724 case ARM::LDRD_POST:
1727 case ARM::LDRH_POST:
1729 case ARM::LDRSH_PRE:
1730 case ARM::LDRSH_POST:
1732 case ARM::LDRSB_PRE:
1733 case ARM::LDRSB_POST:
1736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1737 return MCDisassembler::Fail;
1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1745 return MCDisassembler::Fail;
1748 Inst.addOperand(MCOperand::CreateReg(0));
1749 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1752 return MCDisassembler::Fail;
1753 Inst.addOperand(MCOperand::CreateImm(U));
1756 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1757 return MCDisassembler::Fail;
1762 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1763 uint64_t Address, const void *Decoder) {
1764 DecodeStatus S = MCDisassembler::Success;
1766 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1767 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1784 Inst.addOperand(MCOperand::CreateImm(mode));
1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1786 return MCDisassembler::Fail;
1791 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1792 uint64_t Address, const void *Decoder) {
1793 DecodeStatus S = MCDisassembler::Success;
1795 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1796 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1797 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1798 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1801 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1803 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1804 return MCDisassembler::Fail;
1805 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1806 return MCDisassembler::Fail;
1807 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1808 return MCDisassembler::Fail;
1809 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1810 return MCDisassembler::Fail;
1814 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1816 uint64_t Address, const void *Decoder) {
1817 DecodeStatus S = MCDisassembler::Success;
1819 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1820 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1821 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1824 // Ambiguous with RFE and SRS
1825 switch (Inst.getOpcode()) {
1827 Inst.setOpcode(ARM::RFEDA);
1829 case ARM::LDMDA_UPD:
1830 Inst.setOpcode(ARM::RFEDA_UPD);
1833 Inst.setOpcode(ARM::RFEDB);
1835 case ARM::LDMDB_UPD:
1836 Inst.setOpcode(ARM::RFEDB_UPD);
1839 Inst.setOpcode(ARM::RFEIA);
1841 case ARM::LDMIA_UPD:
1842 Inst.setOpcode(ARM::RFEIA_UPD);
1845 Inst.setOpcode(ARM::RFEIB);
1847 case ARM::LDMIB_UPD:
1848 Inst.setOpcode(ARM::RFEIB_UPD);
1851 Inst.setOpcode(ARM::SRSDA);
1853 case ARM::STMDA_UPD:
1854 Inst.setOpcode(ARM::SRSDA_UPD);
1857 Inst.setOpcode(ARM::SRSDB);
1859 case ARM::STMDB_UPD:
1860 Inst.setOpcode(ARM::SRSDB_UPD);
1863 Inst.setOpcode(ARM::SRSIA);
1865 case ARM::STMIA_UPD:
1866 Inst.setOpcode(ARM::SRSIA_UPD);
1869 Inst.setOpcode(ARM::SRSIB);
1871 case ARM::STMIB_UPD:
1872 Inst.setOpcode(ARM::SRSIB_UPD);
1875 return MCDisassembler::Fail;
1878 // For stores (which become SRS's, the only operand is the mode.
1879 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1880 // Check SRS encoding constraints
1881 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1882 fieldFromInstruction(Insn, 20, 1) == 0))
1883 return MCDisassembler::Fail;
1886 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1890 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1894 return MCDisassembler::Fail;
1895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1896 return MCDisassembler::Fail; // Tied
1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1898 return MCDisassembler::Fail;
1899 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1900 return MCDisassembler::Fail;
1905 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1906 uint64_t Address, const void *Decoder) {
1907 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1908 unsigned M = fieldFromInstruction(Insn, 17, 1);
1909 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1910 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1912 DecodeStatus S = MCDisassembler::Success;
1914 // This decoder is called from multiple location that do not check
1915 // the full encoding is valid before they do.
1916 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1917 fieldFromInstruction(Insn, 16, 1) != 0 ||
1918 fieldFromInstruction(Insn, 20, 8) != 0x10)
1919 return MCDisassembler::Fail;
1921 // imod == '01' --> UNPREDICTABLE
1922 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1923 // return failure here. The '01' imod value is unprintable, so there's
1924 // nothing useful we could do even if we returned UNPREDICTABLE.
1926 if (imod == 1) return MCDisassembler::Fail;
1929 Inst.setOpcode(ARM::CPS3p);
1930 Inst.addOperand(MCOperand::CreateImm(imod));
1931 Inst.addOperand(MCOperand::CreateImm(iflags));
1932 Inst.addOperand(MCOperand::CreateImm(mode));
1933 } else if (imod && !M) {
1934 Inst.setOpcode(ARM::CPS2p);
1935 Inst.addOperand(MCOperand::CreateImm(imod));
1936 Inst.addOperand(MCOperand::CreateImm(iflags));
1937 if (mode) S = MCDisassembler::SoftFail;
1938 } else if (!imod && M) {
1939 Inst.setOpcode(ARM::CPS1p);
1940 Inst.addOperand(MCOperand::CreateImm(mode));
1941 if (iflags) S = MCDisassembler::SoftFail;
1943 // imod == '00' && M == '0' --> UNPREDICTABLE
1944 Inst.setOpcode(ARM::CPS1p);
1945 Inst.addOperand(MCOperand::CreateImm(mode));
1946 S = MCDisassembler::SoftFail;
1952 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1953 uint64_t Address, const void *Decoder) {
1954 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1955 unsigned M = fieldFromInstruction(Insn, 8, 1);
1956 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1957 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1959 DecodeStatus S = MCDisassembler::Success;
1961 // imod == '01' --> UNPREDICTABLE
1962 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1963 // return failure here. The '01' imod value is unprintable, so there's
1964 // nothing useful we could do even if we returned UNPREDICTABLE.
1966 if (imod == 1) return MCDisassembler::Fail;
1969 Inst.setOpcode(ARM::t2CPS3p);
1970 Inst.addOperand(MCOperand::CreateImm(imod));
1971 Inst.addOperand(MCOperand::CreateImm(iflags));
1972 Inst.addOperand(MCOperand::CreateImm(mode));
1973 } else if (imod && !M) {
1974 Inst.setOpcode(ARM::t2CPS2p);
1975 Inst.addOperand(MCOperand::CreateImm(imod));
1976 Inst.addOperand(MCOperand::CreateImm(iflags));
1977 if (mode) S = MCDisassembler::SoftFail;
1978 } else if (!imod && M) {
1979 Inst.setOpcode(ARM::t2CPS1p);
1980 Inst.addOperand(MCOperand::CreateImm(mode));
1981 if (iflags) S = MCDisassembler::SoftFail;
1983 // imod == '00' && M == '0' --> this is a HINT instruction
1984 int imm = fieldFromInstruction(Insn, 0, 8);
1985 // HINT are defined only for immediate in [0..4]
1986 if(imm > 4) return MCDisassembler::Fail;
1987 Inst.setOpcode(ARM::t2HINT);
1988 Inst.addOperand(MCOperand::CreateImm(imm));
1994 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1995 uint64_t Address, const void *Decoder) {
1996 DecodeStatus S = MCDisassembler::Success;
1998 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2001 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2002 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2003 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2004 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2006 if (Inst.getOpcode() == ARM::t2MOVTi16)
2007 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2008 return MCDisassembler::Fail;
2009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2010 return MCDisassembler::Fail;
2012 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2013 Inst.addOperand(MCOperand::CreateImm(imm));
2018 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2019 uint64_t Address, const void *Decoder) {
2020 DecodeStatus S = MCDisassembler::Success;
2022 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2023 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2026 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2027 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2029 if (Inst.getOpcode() == ARM::MOVTi16)
2030 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2031 return MCDisassembler::Fail;
2033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2034 return MCDisassembler::Fail;
2036 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2037 Inst.addOperand(MCOperand::CreateImm(imm));
2039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2040 return MCDisassembler::Fail;
2045 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2046 uint64_t Address, const void *Decoder) {
2047 DecodeStatus S = MCDisassembler::Success;
2049 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2050 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2051 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2052 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2053 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2056 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2058 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2059 return MCDisassembler::Fail;
2060 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2061 return MCDisassembler::Fail;
2062 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2063 return MCDisassembler::Fail;
2064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2065 return MCDisassembler::Fail;
2067 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2068 return MCDisassembler::Fail;
2073 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2074 uint64_t Address, const void *Decoder) {
2075 DecodeStatus S = MCDisassembler::Success;
2077 unsigned add = fieldFromInstruction(Val, 12, 1);
2078 unsigned imm = fieldFromInstruction(Val, 0, 12);
2079 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2082 return MCDisassembler::Fail;
2084 if (!add) imm *= -1;
2085 if (imm == 0 && !add) imm = INT32_MIN;
2086 Inst.addOperand(MCOperand::CreateImm(imm));
2088 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2093 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2094 uint64_t Address, const void *Decoder) {
2095 DecodeStatus S = MCDisassembler::Success;
2097 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2098 unsigned U = fieldFromInstruction(Val, 8, 1);
2099 unsigned imm = fieldFromInstruction(Val, 0, 8);
2101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2102 return MCDisassembler::Fail;
2105 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2107 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2112 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2113 uint64_t Address, const void *Decoder) {
2114 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2118 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2119 uint64_t Address, const void *Decoder) {
2120 DecodeStatus Status = MCDisassembler::Success;
2122 // Note the J1 and J2 values are from the encoded instruction. So here
2123 // change them to I1 and I2 values via as documented:
2124 // I1 = NOT(J1 EOR S);
2125 // I2 = NOT(J2 EOR S);
2126 // and build the imm32 with one trailing zero as documented:
2127 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2128 unsigned S = fieldFromInstruction(Insn, 26, 1);
2129 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2130 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2131 unsigned I1 = !(J1 ^ S);
2132 unsigned I2 = !(J2 ^ S);
2133 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2134 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2135 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2136 int imm32 = SignExtend32<25>(tmp << 1);
2137 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2138 true, 4, Inst, Decoder))
2139 Inst.addOperand(MCOperand::CreateImm(imm32));
2145 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2146 uint64_t Address, const void *Decoder) {
2147 DecodeStatus S = MCDisassembler::Success;
2149 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2150 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2153 Inst.setOpcode(ARM::BLXi);
2154 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2155 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2156 true, 4, Inst, Decoder))
2157 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2161 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2162 true, 4, Inst, Decoder))
2163 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2164 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2165 return MCDisassembler::Fail;
2171 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2172 uint64_t Address, const void *Decoder) {
2173 DecodeStatus S = MCDisassembler::Success;
2175 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2176 unsigned align = fieldFromInstruction(Val, 4, 2);
2178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2179 return MCDisassembler::Fail;
2181 Inst.addOperand(MCOperand::CreateImm(0));
2183 Inst.addOperand(MCOperand::CreateImm(4 << align));
2188 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2189 uint64_t Address, const void *Decoder) {
2190 DecodeStatus S = MCDisassembler::Success;
2192 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2193 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2194 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2195 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2196 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2197 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2199 // First output register
2200 switch (Inst.getOpcode()) {
2201 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2202 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2203 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2204 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2205 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2206 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2207 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2208 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2209 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2210 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2211 return MCDisassembler::Fail;
2216 case ARM::VLD2b16wb_fixed:
2217 case ARM::VLD2b16wb_register:
2218 case ARM::VLD2b32wb_fixed:
2219 case ARM::VLD2b32wb_register:
2220 case ARM::VLD2b8wb_fixed:
2221 case ARM::VLD2b8wb_register:
2222 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2223 return MCDisassembler::Fail;
2226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2227 return MCDisassembler::Fail;
2230 // Second output register
2231 switch (Inst.getOpcode()) {
2235 case ARM::VLD3d8_UPD:
2236 case ARM::VLD3d16_UPD:
2237 case ARM::VLD3d32_UPD:
2241 case ARM::VLD4d8_UPD:
2242 case ARM::VLD4d16_UPD:
2243 case ARM::VLD4d32_UPD:
2244 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2245 return MCDisassembler::Fail;
2250 case ARM::VLD3q8_UPD:
2251 case ARM::VLD3q16_UPD:
2252 case ARM::VLD3q32_UPD:
2256 case ARM::VLD4q8_UPD:
2257 case ARM::VLD4q16_UPD:
2258 case ARM::VLD4q32_UPD:
2259 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2260 return MCDisassembler::Fail;
2265 // Third output register
2266 switch(Inst.getOpcode()) {
2270 case ARM::VLD3d8_UPD:
2271 case ARM::VLD3d16_UPD:
2272 case ARM::VLD3d32_UPD:
2276 case ARM::VLD4d8_UPD:
2277 case ARM::VLD4d16_UPD:
2278 case ARM::VLD4d32_UPD:
2279 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2280 return MCDisassembler::Fail;
2285 case ARM::VLD3q8_UPD:
2286 case ARM::VLD3q16_UPD:
2287 case ARM::VLD3q32_UPD:
2291 case ARM::VLD4q8_UPD:
2292 case ARM::VLD4q16_UPD:
2293 case ARM::VLD4q32_UPD:
2294 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2295 return MCDisassembler::Fail;
2301 // Fourth output register
2302 switch (Inst.getOpcode()) {
2306 case ARM::VLD4d8_UPD:
2307 case ARM::VLD4d16_UPD:
2308 case ARM::VLD4d32_UPD:
2309 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2310 return MCDisassembler::Fail;
2315 case ARM::VLD4q8_UPD:
2316 case ARM::VLD4q16_UPD:
2317 case ARM::VLD4q32_UPD:
2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2319 return MCDisassembler::Fail;
2325 // Writeback operand
2326 switch (Inst.getOpcode()) {
2327 case ARM::VLD1d8wb_fixed:
2328 case ARM::VLD1d16wb_fixed:
2329 case ARM::VLD1d32wb_fixed:
2330 case ARM::VLD1d64wb_fixed:
2331 case ARM::VLD1d8wb_register:
2332 case ARM::VLD1d16wb_register:
2333 case ARM::VLD1d32wb_register:
2334 case ARM::VLD1d64wb_register:
2335 case ARM::VLD1q8wb_fixed:
2336 case ARM::VLD1q16wb_fixed:
2337 case ARM::VLD1q32wb_fixed:
2338 case ARM::VLD1q64wb_fixed:
2339 case ARM::VLD1q8wb_register:
2340 case ARM::VLD1q16wb_register:
2341 case ARM::VLD1q32wb_register:
2342 case ARM::VLD1q64wb_register:
2343 case ARM::VLD1d8Twb_fixed:
2344 case ARM::VLD1d8Twb_register:
2345 case ARM::VLD1d16Twb_fixed:
2346 case ARM::VLD1d16Twb_register:
2347 case ARM::VLD1d32Twb_fixed:
2348 case ARM::VLD1d32Twb_register:
2349 case ARM::VLD1d64Twb_fixed:
2350 case ARM::VLD1d64Twb_register:
2351 case ARM::VLD1d8Qwb_fixed:
2352 case ARM::VLD1d8Qwb_register:
2353 case ARM::VLD1d16Qwb_fixed:
2354 case ARM::VLD1d16Qwb_register:
2355 case ARM::VLD1d32Qwb_fixed:
2356 case ARM::VLD1d32Qwb_register:
2357 case ARM::VLD1d64Qwb_fixed:
2358 case ARM::VLD1d64Qwb_register:
2359 case ARM::VLD2d8wb_fixed:
2360 case ARM::VLD2d16wb_fixed:
2361 case ARM::VLD2d32wb_fixed:
2362 case ARM::VLD2q8wb_fixed:
2363 case ARM::VLD2q16wb_fixed:
2364 case ARM::VLD2q32wb_fixed:
2365 case ARM::VLD2d8wb_register:
2366 case ARM::VLD2d16wb_register:
2367 case ARM::VLD2d32wb_register:
2368 case ARM::VLD2q8wb_register:
2369 case ARM::VLD2q16wb_register:
2370 case ARM::VLD2q32wb_register:
2371 case ARM::VLD2b8wb_fixed:
2372 case ARM::VLD2b16wb_fixed:
2373 case ARM::VLD2b32wb_fixed:
2374 case ARM::VLD2b8wb_register:
2375 case ARM::VLD2b16wb_register:
2376 case ARM::VLD2b32wb_register:
2377 Inst.addOperand(MCOperand::CreateImm(0));
2379 case ARM::VLD3d8_UPD:
2380 case ARM::VLD3d16_UPD:
2381 case ARM::VLD3d32_UPD:
2382 case ARM::VLD3q8_UPD:
2383 case ARM::VLD3q16_UPD:
2384 case ARM::VLD3q32_UPD:
2385 case ARM::VLD4d8_UPD:
2386 case ARM::VLD4d16_UPD:
2387 case ARM::VLD4d32_UPD:
2388 case ARM::VLD4q8_UPD:
2389 case ARM::VLD4q16_UPD:
2390 case ARM::VLD4q32_UPD:
2391 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2392 return MCDisassembler::Fail;
2398 // AddrMode6 Base (register+alignment)
2399 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2400 return MCDisassembler::Fail;
2402 // AddrMode6 Offset (register)
2403 switch (Inst.getOpcode()) {
2405 // The below have been updated to have explicit am6offset split
2406 // between fixed and register offset. For those instructions not
2407 // yet updated, we need to add an additional reg0 operand for the
2410 // The fixed offset encodes as Rm == 0xd, so we check for that.
2412 Inst.addOperand(MCOperand::CreateReg(0));
2415 // Fall through to handle the register offset variant.
2416 case ARM::VLD1d8wb_fixed:
2417 case ARM::VLD1d16wb_fixed:
2418 case ARM::VLD1d32wb_fixed:
2419 case ARM::VLD1d64wb_fixed:
2420 case ARM::VLD1d8Twb_fixed:
2421 case ARM::VLD1d16Twb_fixed:
2422 case ARM::VLD1d32Twb_fixed:
2423 case ARM::VLD1d64Twb_fixed:
2424 case ARM::VLD1d8Qwb_fixed:
2425 case ARM::VLD1d16Qwb_fixed:
2426 case ARM::VLD1d32Qwb_fixed:
2427 case ARM::VLD1d64Qwb_fixed:
2428 case ARM::VLD1d8wb_register:
2429 case ARM::VLD1d16wb_register:
2430 case ARM::VLD1d32wb_register:
2431 case ARM::VLD1d64wb_register:
2432 case ARM::VLD1q8wb_fixed:
2433 case ARM::VLD1q16wb_fixed:
2434 case ARM::VLD1q32wb_fixed:
2435 case ARM::VLD1q64wb_fixed:
2436 case ARM::VLD1q8wb_register:
2437 case ARM::VLD1q16wb_register:
2438 case ARM::VLD1q32wb_register:
2439 case ARM::VLD1q64wb_register:
2440 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2441 // variant encodes Rm == 0xf. Anything else is a register offset post-
2442 // increment and we need to add the register operand to the instruction.
2443 if (Rm != 0xD && Rm != 0xF &&
2444 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2445 return MCDisassembler::Fail;
2447 case ARM::VLD2d8wb_fixed:
2448 case ARM::VLD2d16wb_fixed:
2449 case ARM::VLD2d32wb_fixed:
2450 case ARM::VLD2b8wb_fixed:
2451 case ARM::VLD2b16wb_fixed:
2452 case ARM::VLD2b32wb_fixed:
2453 case ARM::VLD2q8wb_fixed:
2454 case ARM::VLD2q16wb_fixed:
2455 case ARM::VLD2q32wb_fixed:
2462 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2463 uint64_t Address, const void *Decoder) {
2464 unsigned type = fieldFromInstruction(Insn, 8, 4);
2465 unsigned align = fieldFromInstruction(Insn, 4, 2);
2466 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2467 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2468 if (type == 10 && align == 3) return MCDisassembler::Fail;
2470 unsigned load = fieldFromInstruction(Insn, 21, 1);
2471 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2472 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2475 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2476 uint64_t Address, const void *Decoder) {
2477 unsigned size = fieldFromInstruction(Insn, 6, 2);
2478 if (size == 3) return MCDisassembler::Fail;
2480 unsigned type = fieldFromInstruction(Insn, 8, 4);
2481 unsigned align = fieldFromInstruction(Insn, 4, 2);
2482 if (type == 8 && align == 3) return MCDisassembler::Fail;
2483 if (type == 9 && align == 3) return MCDisassembler::Fail;
2485 unsigned load = fieldFromInstruction(Insn, 21, 1);
2486 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2487 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2490 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2491 uint64_t Address, const void *Decoder) {
2492 unsigned size = fieldFromInstruction(Insn, 6, 2);
2493 if (size == 3) return MCDisassembler::Fail;
2495 unsigned align = fieldFromInstruction(Insn, 4, 2);
2496 if (align & 2) return MCDisassembler::Fail;
2498 unsigned load = fieldFromInstruction(Insn, 21, 1);
2499 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2500 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2503 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2504 uint64_t Address, const void *Decoder) {
2505 unsigned size = fieldFromInstruction(Insn, 6, 2);
2506 if (size == 3) return MCDisassembler::Fail;
2508 unsigned load = fieldFromInstruction(Insn, 21, 1);
2509 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2510 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2513 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2514 uint64_t Address, const void *Decoder) {
2515 DecodeStatus S = MCDisassembler::Success;
2517 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2518 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2519 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2520 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2521 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2522 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2524 // Writeback Operand
2525 switch (Inst.getOpcode()) {
2526 case ARM::VST1d8wb_fixed:
2527 case ARM::VST1d16wb_fixed:
2528 case ARM::VST1d32wb_fixed:
2529 case ARM::VST1d64wb_fixed:
2530 case ARM::VST1d8wb_register:
2531 case ARM::VST1d16wb_register:
2532 case ARM::VST1d32wb_register:
2533 case ARM::VST1d64wb_register:
2534 case ARM::VST1q8wb_fixed:
2535 case ARM::VST1q16wb_fixed:
2536 case ARM::VST1q32wb_fixed:
2537 case ARM::VST1q64wb_fixed:
2538 case ARM::VST1q8wb_register:
2539 case ARM::VST1q16wb_register:
2540 case ARM::VST1q32wb_register:
2541 case ARM::VST1q64wb_register:
2542 case ARM::VST1d8Twb_fixed:
2543 case ARM::VST1d16Twb_fixed:
2544 case ARM::VST1d32Twb_fixed:
2545 case ARM::VST1d64Twb_fixed:
2546 case ARM::VST1d8Twb_register:
2547 case ARM::VST1d16Twb_register:
2548 case ARM::VST1d32Twb_register:
2549 case ARM::VST1d64Twb_register:
2550 case ARM::VST1d8Qwb_fixed:
2551 case ARM::VST1d16Qwb_fixed:
2552 case ARM::VST1d32Qwb_fixed:
2553 case ARM::VST1d64Qwb_fixed:
2554 case ARM::VST1d8Qwb_register:
2555 case ARM::VST1d16Qwb_register:
2556 case ARM::VST1d32Qwb_register:
2557 case ARM::VST1d64Qwb_register:
2558 case ARM::VST2d8wb_fixed:
2559 case ARM::VST2d16wb_fixed:
2560 case ARM::VST2d32wb_fixed:
2561 case ARM::VST2d8wb_register:
2562 case ARM::VST2d16wb_register:
2563 case ARM::VST2d32wb_register:
2564 case ARM::VST2q8wb_fixed:
2565 case ARM::VST2q16wb_fixed:
2566 case ARM::VST2q32wb_fixed:
2567 case ARM::VST2q8wb_register:
2568 case ARM::VST2q16wb_register:
2569 case ARM::VST2q32wb_register:
2570 case ARM::VST2b8wb_fixed:
2571 case ARM::VST2b16wb_fixed:
2572 case ARM::VST2b32wb_fixed:
2573 case ARM::VST2b8wb_register:
2574 case ARM::VST2b16wb_register:
2575 case ARM::VST2b32wb_register:
2577 return MCDisassembler::Fail;
2578 Inst.addOperand(MCOperand::CreateImm(0));
2580 case ARM::VST3d8_UPD:
2581 case ARM::VST3d16_UPD:
2582 case ARM::VST3d32_UPD:
2583 case ARM::VST3q8_UPD:
2584 case ARM::VST3q16_UPD:
2585 case ARM::VST3q32_UPD:
2586 case ARM::VST4d8_UPD:
2587 case ARM::VST4d16_UPD:
2588 case ARM::VST4d32_UPD:
2589 case ARM::VST4q8_UPD:
2590 case ARM::VST4q16_UPD:
2591 case ARM::VST4q32_UPD:
2592 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2593 return MCDisassembler::Fail;
2599 // AddrMode6 Base (register+alignment)
2600 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2601 return MCDisassembler::Fail;
2603 // AddrMode6 Offset (register)
2604 switch (Inst.getOpcode()) {
2607 Inst.addOperand(MCOperand::CreateReg(0));
2608 else if (Rm != 0xF) {
2609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2610 return MCDisassembler::Fail;
2613 case ARM::VST1d8wb_fixed:
2614 case ARM::VST1d16wb_fixed:
2615 case ARM::VST1d32wb_fixed:
2616 case ARM::VST1d64wb_fixed:
2617 case ARM::VST1q8wb_fixed:
2618 case ARM::VST1q16wb_fixed:
2619 case ARM::VST1q32wb_fixed:
2620 case ARM::VST1q64wb_fixed:
2621 case ARM::VST1d8Twb_fixed:
2622 case ARM::VST1d16Twb_fixed:
2623 case ARM::VST1d32Twb_fixed:
2624 case ARM::VST1d64Twb_fixed:
2625 case ARM::VST1d8Qwb_fixed:
2626 case ARM::VST1d16Qwb_fixed:
2627 case ARM::VST1d32Qwb_fixed:
2628 case ARM::VST1d64Qwb_fixed:
2629 case ARM::VST2d8wb_fixed:
2630 case ARM::VST2d16wb_fixed:
2631 case ARM::VST2d32wb_fixed:
2632 case ARM::VST2q8wb_fixed:
2633 case ARM::VST2q16wb_fixed:
2634 case ARM::VST2q32wb_fixed:
2635 case ARM::VST2b8wb_fixed:
2636 case ARM::VST2b16wb_fixed:
2637 case ARM::VST2b32wb_fixed:
2642 // First input register
2643 switch (Inst.getOpcode()) {
2648 case ARM::VST1q16wb_fixed:
2649 case ARM::VST1q16wb_register:
2650 case ARM::VST1q32wb_fixed:
2651 case ARM::VST1q32wb_register:
2652 case ARM::VST1q64wb_fixed:
2653 case ARM::VST1q64wb_register:
2654 case ARM::VST1q8wb_fixed:
2655 case ARM::VST1q8wb_register:
2659 case ARM::VST2d16wb_fixed:
2660 case ARM::VST2d16wb_register:
2661 case ARM::VST2d32wb_fixed:
2662 case ARM::VST2d32wb_register:
2663 case ARM::VST2d8wb_fixed:
2664 case ARM::VST2d8wb_register:
2665 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2666 return MCDisassembler::Fail;
2671 case ARM::VST2b16wb_fixed:
2672 case ARM::VST2b16wb_register:
2673 case ARM::VST2b32wb_fixed:
2674 case ARM::VST2b32wb_register:
2675 case ARM::VST2b8wb_fixed:
2676 case ARM::VST2b8wb_register:
2677 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2678 return MCDisassembler::Fail;
2681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2682 return MCDisassembler::Fail;
2685 // Second input register
2686 switch (Inst.getOpcode()) {
2690 case ARM::VST3d8_UPD:
2691 case ARM::VST3d16_UPD:
2692 case ARM::VST3d32_UPD:
2696 case ARM::VST4d8_UPD:
2697 case ARM::VST4d16_UPD:
2698 case ARM::VST4d32_UPD:
2699 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2700 return MCDisassembler::Fail;
2705 case ARM::VST3q8_UPD:
2706 case ARM::VST3q16_UPD:
2707 case ARM::VST3q32_UPD:
2711 case ARM::VST4q8_UPD:
2712 case ARM::VST4q16_UPD:
2713 case ARM::VST4q32_UPD:
2714 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2715 return MCDisassembler::Fail;
2721 // Third input register
2722 switch (Inst.getOpcode()) {
2726 case ARM::VST3d8_UPD:
2727 case ARM::VST3d16_UPD:
2728 case ARM::VST3d32_UPD:
2732 case ARM::VST4d8_UPD:
2733 case ARM::VST4d16_UPD:
2734 case ARM::VST4d32_UPD:
2735 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2736 return MCDisassembler::Fail;
2741 case ARM::VST3q8_UPD:
2742 case ARM::VST3q16_UPD:
2743 case ARM::VST3q32_UPD:
2747 case ARM::VST4q8_UPD:
2748 case ARM::VST4q16_UPD:
2749 case ARM::VST4q32_UPD:
2750 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2751 return MCDisassembler::Fail;
2757 // Fourth input register
2758 switch (Inst.getOpcode()) {
2762 case ARM::VST4d8_UPD:
2763 case ARM::VST4d16_UPD:
2764 case ARM::VST4d32_UPD:
2765 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2766 return MCDisassembler::Fail;
2771 case ARM::VST4q8_UPD:
2772 case ARM::VST4q16_UPD:
2773 case ARM::VST4q32_UPD:
2774 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2775 return MCDisassembler::Fail;
2784 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2785 uint64_t Address, const void *Decoder) {
2786 DecodeStatus S = MCDisassembler::Success;
2788 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2789 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2790 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2791 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2792 unsigned align = fieldFromInstruction(Insn, 4, 1);
2793 unsigned size = fieldFromInstruction(Insn, 6, 2);
2795 if (size == 0 && align == 1)
2796 return MCDisassembler::Fail;
2797 align *= (1 << size);
2799 switch (Inst.getOpcode()) {
2800 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2801 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2802 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2803 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2804 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2805 return MCDisassembler::Fail;
2808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2809 return MCDisassembler::Fail;
2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2814 return MCDisassembler::Fail;
2817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2818 return MCDisassembler::Fail;
2819 Inst.addOperand(MCOperand::CreateImm(align));
2821 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2822 // variant encodes Rm == 0xf. Anything else is a register offset post-
2823 // increment and we need to add the register operand to the instruction.
2824 if (Rm != 0xD && Rm != 0xF &&
2825 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2826 return MCDisassembler::Fail;
2831 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2832 uint64_t Address, const void *Decoder) {
2833 DecodeStatus S = MCDisassembler::Success;
2835 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2836 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2837 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2838 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2839 unsigned align = fieldFromInstruction(Insn, 4, 1);
2840 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2843 switch (Inst.getOpcode()) {
2844 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2845 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2846 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2847 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2848 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2849 return MCDisassembler::Fail;
2851 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2852 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2853 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2854 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2855 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2856 return MCDisassembler::Fail;
2859 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2860 return MCDisassembler::Fail;
2865 Inst.addOperand(MCOperand::CreateImm(0));
2867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2868 return MCDisassembler::Fail;
2869 Inst.addOperand(MCOperand::CreateImm(align));
2871 if (Rm != 0xD && Rm != 0xF) {
2872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2873 return MCDisassembler::Fail;
2879 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2880 uint64_t Address, const void *Decoder) {
2881 DecodeStatus S = MCDisassembler::Success;
2883 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2884 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2885 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2886 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2887 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2890 return MCDisassembler::Fail;
2891 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2892 return MCDisassembler::Fail;
2893 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2894 return MCDisassembler::Fail;
2896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2897 return MCDisassembler::Fail;
2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2901 return MCDisassembler::Fail;
2902 Inst.addOperand(MCOperand::CreateImm(0));
2905 Inst.addOperand(MCOperand::CreateReg(0));
2906 else if (Rm != 0xF) {
2907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2908 return MCDisassembler::Fail;
2914 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2915 uint64_t Address, const void *Decoder) {
2916 DecodeStatus S = MCDisassembler::Success;
2918 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2919 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2920 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2921 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2922 unsigned size = fieldFromInstruction(Insn, 6, 2);
2923 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2924 unsigned align = fieldFromInstruction(Insn, 4, 1);
2928 return MCDisassembler::Fail;
2941 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2942 return MCDisassembler::Fail;
2943 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2946 return MCDisassembler::Fail;
2947 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2948 return MCDisassembler::Fail;
2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2951 return MCDisassembler::Fail;
2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2955 return MCDisassembler::Fail;
2956 Inst.addOperand(MCOperand::CreateImm(align));
2959 Inst.addOperand(MCOperand::CreateReg(0));
2960 else if (Rm != 0xF) {
2961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2962 return MCDisassembler::Fail;
2969 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2970 uint64_t Address, const void *Decoder) {
2971 DecodeStatus S = MCDisassembler::Success;
2973 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2974 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2975 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2976 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2977 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2978 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2979 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2980 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2983 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2984 return MCDisassembler::Fail;
2986 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2987 return MCDisassembler::Fail;
2990 Inst.addOperand(MCOperand::CreateImm(imm));
2992 switch (Inst.getOpcode()) {
2993 case ARM::VORRiv4i16:
2994 case ARM::VORRiv2i32:
2995 case ARM::VBICiv4i16:
2996 case ARM::VBICiv2i32:
2997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2998 return MCDisassembler::Fail;
3000 case ARM::VORRiv8i16:
3001 case ARM::VORRiv4i32:
3002 case ARM::VBICiv8i16:
3003 case ARM::VBICiv4i32:
3004 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3005 return MCDisassembler::Fail;
3014 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3015 uint64_t Address, const void *Decoder) {
3016 DecodeStatus S = MCDisassembler::Success;
3018 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3019 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3020 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3021 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3022 unsigned size = fieldFromInstruction(Insn, 18, 2);
3024 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3025 return MCDisassembler::Fail;
3026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3027 return MCDisassembler::Fail;
3028 Inst.addOperand(MCOperand::CreateImm(8 << size));
3033 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3034 uint64_t Address, const void *Decoder) {
3035 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3036 return MCDisassembler::Success;
3039 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3040 uint64_t Address, const void *Decoder) {
3041 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3042 return MCDisassembler::Success;
3045 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3046 uint64_t Address, const void *Decoder) {
3047 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3048 return MCDisassembler::Success;
3051 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3052 uint64_t Address, const void *Decoder) {
3053 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3054 return MCDisassembler::Success;
3057 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3058 uint64_t Address, const void *Decoder) {
3059 DecodeStatus S = MCDisassembler::Success;
3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3063 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3064 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3065 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3066 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3067 unsigned op = fieldFromInstruction(Insn, 6, 1);
3069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3070 return MCDisassembler::Fail;
3072 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3073 return MCDisassembler::Fail; // Writeback
3076 switch (Inst.getOpcode()) {
3079 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3080 return MCDisassembler::Fail;
3083 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3084 return MCDisassembler::Fail;
3087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3088 return MCDisassembler::Fail;
3093 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3094 uint64_t Address, const void *Decoder) {
3095 DecodeStatus S = MCDisassembler::Success;
3097 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3098 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3100 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3101 return MCDisassembler::Fail;
3103 switch(Inst.getOpcode()) {
3105 return MCDisassembler::Fail;
3107 break; // tADR does not explicitly represent the PC as an operand.
3109 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3113 Inst.addOperand(MCOperand::CreateImm(imm));
3117 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3118 uint64_t Address, const void *Decoder) {
3119 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3120 true, 2, Inst, Decoder))
3121 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3122 return MCDisassembler::Success;
3125 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3126 uint64_t Address, const void *Decoder) {
3127 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3128 true, 4, Inst, Decoder))
3129 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3130 return MCDisassembler::Success;
3133 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3134 uint64_t Address, const void *Decoder) {
3135 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3136 true, 2, Inst, Decoder))
3137 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3138 return MCDisassembler::Success;
3141 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3142 uint64_t Address, const void *Decoder) {
3143 DecodeStatus S = MCDisassembler::Success;
3145 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3146 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3148 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3149 return MCDisassembler::Fail;
3150 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3151 return MCDisassembler::Fail;
3156 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3157 uint64_t Address, const void *Decoder) {
3158 DecodeStatus S = MCDisassembler::Success;
3160 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3161 unsigned imm = fieldFromInstruction(Val, 3, 5);
3163 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3164 return MCDisassembler::Fail;
3165 Inst.addOperand(MCOperand::CreateImm(imm));
3170 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3171 uint64_t Address, const void *Decoder) {
3172 unsigned imm = Val << 2;
3174 Inst.addOperand(MCOperand::CreateImm(imm));
3175 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3177 return MCDisassembler::Success;
3180 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3181 uint64_t Address, const void *Decoder) {
3182 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3183 Inst.addOperand(MCOperand::CreateImm(Val));
3185 return MCDisassembler::Success;
3188 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3189 uint64_t Address, const void *Decoder) {
3190 DecodeStatus S = MCDisassembler::Success;
3192 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3193 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3194 unsigned imm = fieldFromInstruction(Val, 0, 2);
3196 // Thumb stores cannot use PC as dest register.
3197 switch (Inst.getOpcode()) {
3202 return MCDisassembler::Fail;
3207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3208 return MCDisassembler::Fail;
3209 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3210 return MCDisassembler::Fail;
3211 Inst.addOperand(MCOperand::CreateImm(imm));
3216 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3217 uint64_t Address, const void *Decoder) {
3218 DecodeStatus S = MCDisassembler::Success;
3220 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3221 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3224 switch (Inst.getOpcode()) {
3226 Inst.setOpcode(ARM::t2LDRBpci);
3229 Inst.setOpcode(ARM::t2LDRHpci);
3232 Inst.setOpcode(ARM::t2LDRSHpci);
3235 Inst.setOpcode(ARM::t2LDRSBpci);
3238 Inst.setOpcode(ARM::t2LDRpci);
3241 Inst.setOpcode(ARM::t2PLDpci);
3244 Inst.setOpcode(ARM::t2PLIpci);
3247 return MCDisassembler::Fail;
3250 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3254 switch (Inst.getOpcode()) {
3256 return MCDisassembler::Fail;
3258 // FIXME: this instruction is only available with MP extensions,
3259 // this should be checked first but we don't have access to the
3260 // feature bits here.
3261 Inst.setOpcode(ARM::t2PLDWs);
3268 switch (Inst.getOpcode()) {
3274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3275 return MCDisassembler::Fail;
3278 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3279 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3280 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3281 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3282 return MCDisassembler::Fail;
3287 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3288 uint64_t Address, const void* Decoder) {
3289 DecodeStatus S = MCDisassembler::Success;
3291 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3292 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3293 unsigned U = fieldFromInstruction(Insn, 9, 1);
3294 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3299 switch (Inst.getOpcode()) {
3301 Inst.setOpcode(ARM::t2LDRpci);
3304 Inst.setOpcode(ARM::t2LDRBpci);
3306 case ARM::t2LDRSBi8:
3307 Inst.setOpcode(ARM::t2LDRSBpci);
3310 Inst.setOpcode(ARM::t2LDRHpci);
3312 case ARM::t2LDRSHi8:
3313 Inst.setOpcode(ARM::t2LDRSHpci);
3316 Inst.setOpcode(ARM::t2PLDpci);
3319 Inst.setOpcode(ARM::t2PLIpci);
3322 return MCDisassembler::Fail;
3324 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3328 switch (Inst.getOpcode()) {
3329 case ARM::t2LDRSHi8:
3330 return MCDisassembler::Fail;
3336 switch (Inst.getOpcode()) {
3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3342 return MCDisassembler::Fail;
3345 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3346 return MCDisassembler::Fail;
3350 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3351 uint64_t Address, const void* Decoder) {
3352 DecodeStatus S = MCDisassembler::Success;
3354 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3355 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3356 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3360 switch (Inst.getOpcode()) {
3362 Inst.setOpcode(ARM::t2LDRpci);
3364 case ARM::t2LDRHi12:
3365 Inst.setOpcode(ARM::t2LDRHpci);
3367 case ARM::t2LDRSHi12:
3368 Inst.setOpcode(ARM::t2LDRSHpci);
3370 case ARM::t2LDRBi12:
3371 Inst.setOpcode(ARM::t2LDRBpci);
3373 case ARM::t2LDRSBi12:
3374 Inst.setOpcode(ARM::t2LDRSBpci);
3377 Inst.setOpcode(ARM::t2PLDpci);
3380 Inst.setOpcode(ARM::t2PLIpci);
3383 return MCDisassembler::Fail;
3385 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3389 switch (Inst.getOpcode()) {
3390 case ARM::t2LDRSHi12:
3391 return MCDisassembler::Fail;
3392 case ARM::t2LDRHi12:
3393 Inst.setOpcode(ARM::t2PLDi12);
3400 switch (Inst.getOpcode()) {
3405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3406 return MCDisassembler::Fail;
3409 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3410 return MCDisassembler::Fail;
3414 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3415 uint64_t Address, const void* Decoder) {
3416 DecodeStatus S = MCDisassembler::Success;
3418 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3419 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3420 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3424 switch (Inst.getOpcode()) {
3426 Inst.setOpcode(ARM::t2LDRpci);
3429 Inst.setOpcode(ARM::t2LDRBpci);
3432 Inst.setOpcode(ARM::t2LDRHpci);
3435 Inst.setOpcode(ARM::t2LDRSBpci);
3438 Inst.setOpcode(ARM::t2LDRSHpci);
3441 return MCDisassembler::Fail;
3443 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3446 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3447 return MCDisassembler::Fail;
3448 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3449 return MCDisassembler::Fail;
3453 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3454 uint64_t Address, const void* Decoder) {
3455 DecodeStatus S = MCDisassembler::Success;
3457 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3458 unsigned U = fieldFromInstruction(Insn, 23, 1);
3459 int imm = fieldFromInstruction(Insn, 0, 12);
3462 switch (Inst.getOpcode()) {
3463 case ARM::t2LDRBpci:
3464 case ARM::t2LDRHpci:
3465 Inst.setOpcode(ARM::t2PLDpci);
3467 case ARM::t2LDRSBpci:
3468 Inst.setOpcode(ARM::t2PLIpci);
3470 case ARM::t2LDRSHpci:
3471 return MCDisassembler::Fail;
3477 switch(Inst.getOpcode()) {
3482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3483 return MCDisassembler::Fail;
3487 // Special case for #-0.
3493 Inst.addOperand(MCOperand::CreateImm(imm));
3498 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3499 uint64_t Address, const void *Decoder) {
3501 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3503 int imm = Val & 0xFF;
3505 if (!(Val & 0x100)) imm *= -1;
3506 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3509 return MCDisassembler::Success;
3512 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3513 uint64_t Address, const void *Decoder) {
3514 DecodeStatus S = MCDisassembler::Success;
3516 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3517 unsigned imm = fieldFromInstruction(Val, 0, 9);
3519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3520 return MCDisassembler::Fail;
3521 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3522 return MCDisassembler::Fail;
3527 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3528 uint64_t Address, const void *Decoder) {
3529 DecodeStatus S = MCDisassembler::Success;
3531 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3532 unsigned imm = fieldFromInstruction(Val, 0, 8);
3534 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3535 return MCDisassembler::Fail;
3537 Inst.addOperand(MCOperand::CreateImm(imm));
3542 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3543 uint64_t Address, const void *Decoder) {
3544 int imm = Val & 0xFF;
3547 else if (!(Val & 0x100))
3549 Inst.addOperand(MCOperand::CreateImm(imm));
3551 return MCDisassembler::Success;
3555 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3556 uint64_t Address, const void *Decoder) {
3557 DecodeStatus S = MCDisassembler::Success;
3559 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3560 unsigned imm = fieldFromInstruction(Val, 0, 9);
3562 // Thumb stores cannot use PC as dest register.
3563 switch (Inst.getOpcode()) {
3571 return MCDisassembler::Fail;
3577 // Some instructions always use an additive offset.
3578 switch (Inst.getOpcode()) {
3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3596 return MCDisassembler::Fail;
3601 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3602 uint64_t Address, const void *Decoder) {
3603 DecodeStatus S = MCDisassembler::Success;
3605 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3606 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3607 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3608 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3610 unsigned load = fieldFromInstruction(Insn, 20, 1);
3613 switch (Inst.getOpcode()) {
3614 case ARM::t2LDR_PRE:
3615 case ARM::t2LDR_POST:
3616 Inst.setOpcode(ARM::t2LDRpci);
3618 case ARM::t2LDRB_PRE:
3619 case ARM::t2LDRB_POST:
3620 Inst.setOpcode(ARM::t2LDRBpci);
3622 case ARM::t2LDRH_PRE:
3623 case ARM::t2LDRH_POST:
3624 Inst.setOpcode(ARM::t2LDRHpci);
3626 case ARM::t2LDRSB_PRE:
3627 case ARM::t2LDRSB_POST:
3629 Inst.setOpcode(ARM::t2PLIpci);
3631 Inst.setOpcode(ARM::t2LDRSBpci);
3633 case ARM::t2LDRSH_PRE:
3634 case ARM::t2LDRSH_POST:
3635 Inst.setOpcode(ARM::t2LDRSHpci);
3638 return MCDisassembler::Fail;
3640 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3645 return MCDisassembler::Fail;
3648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3649 return MCDisassembler::Fail;
3652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3653 return MCDisassembler::Fail;
3656 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3657 return MCDisassembler::Fail;
3662 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3663 uint64_t Address, const void *Decoder) {
3664 DecodeStatus S = MCDisassembler::Success;
3666 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3667 unsigned imm = fieldFromInstruction(Val, 0, 12);
3669 // Thumb stores cannot use PC as dest register.
3670 switch (Inst.getOpcode()) {
3672 case ARM::t2STRBi12:
3673 case ARM::t2STRHi12:
3675 return MCDisassembler::Fail;
3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3681 return MCDisassembler::Fail;
3682 Inst.addOperand(MCOperand::CreateImm(imm));
3688 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3689 uint64_t Address, const void *Decoder) {
3690 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3692 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3693 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3694 Inst.addOperand(MCOperand::CreateImm(imm));
3696 return MCDisassembler::Success;
3699 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3700 uint64_t Address, const void *Decoder) {
3701 DecodeStatus S = MCDisassembler::Success;
3703 if (Inst.getOpcode() == ARM::tADDrSP) {
3704 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3705 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3708 return MCDisassembler::Fail;
3709 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3711 return MCDisassembler::Fail;
3712 } else if (Inst.getOpcode() == ARM::tADDspr) {
3713 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3715 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3716 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3718 return MCDisassembler::Fail;
3724 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3725 uint64_t Address, const void *Decoder) {
3726 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3727 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3729 Inst.addOperand(MCOperand::CreateImm(imod));
3730 Inst.addOperand(MCOperand::CreateImm(flags));
3732 return MCDisassembler::Success;
3735 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3736 uint64_t Address, const void *Decoder) {
3737 DecodeStatus S = MCDisassembler::Success;
3738 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3739 unsigned add = fieldFromInstruction(Insn, 4, 1);
3741 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3742 return MCDisassembler::Fail;
3743 Inst.addOperand(MCOperand::CreateImm(add));
3748 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3749 uint64_t Address, const void *Decoder) {
3750 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3751 // Note only one trailing zero not two. Also the J1 and J2 values are from
3752 // the encoded instruction. So here change to I1 and I2 values via:
3753 // I1 = NOT(J1 EOR S);
3754 // I2 = NOT(J2 EOR S);
3755 // and build the imm32 with two trailing zeros as documented:
3756 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3757 unsigned S = (Val >> 23) & 1;
3758 unsigned J1 = (Val >> 22) & 1;
3759 unsigned J2 = (Val >> 21) & 1;
3760 unsigned I1 = !(J1 ^ S);
3761 unsigned I2 = !(J2 ^ S);
3762 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3763 int imm32 = SignExtend32<25>(tmp << 1);
3765 if (!tryAddingSymbolicOperand(Address,
3766 (Address & ~2u) + imm32 + 4,
3767 true, 4, Inst, Decoder))
3768 Inst.addOperand(MCOperand::CreateImm(imm32));
3769 return MCDisassembler::Success;
3772 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3773 uint64_t Address, const void *Decoder) {
3774 if (Val == 0xA || Val == 0xB)
3775 return MCDisassembler::Fail;
3777 Inst.addOperand(MCOperand::CreateImm(Val));
3778 return MCDisassembler::Success;
3782 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3783 uint64_t Address, const void *Decoder) {
3784 DecodeStatus S = MCDisassembler::Success;
3786 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3787 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3789 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3791 return MCDisassembler::Fail;
3792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3793 return MCDisassembler::Fail;
3798 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3799 uint64_t Address, const void *Decoder) {
3800 DecodeStatus S = MCDisassembler::Success;
3802 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3803 if (pred == 0xE || pred == 0xF) {
3804 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3807 return MCDisassembler::Fail;
3809 Inst.setOpcode(ARM::t2DSB);
3812 Inst.setOpcode(ARM::t2DMB);
3815 Inst.setOpcode(ARM::t2ISB);
3819 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3820 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3823 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3824 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3825 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3826 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3827 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3829 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3830 return MCDisassembler::Fail;
3831 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3832 return MCDisassembler::Fail;
3837 // Decode a shifted immediate operand. These basically consist
3838 // of an 8-bit value, and a 4-bit directive that specifies either
3839 // a splat operation or a rotation.
3840 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3841 uint64_t Address, const void *Decoder) {
3842 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3844 unsigned byte = fieldFromInstruction(Val, 8, 2);
3845 unsigned imm = fieldFromInstruction(Val, 0, 8);
3848 Inst.addOperand(MCOperand::CreateImm(imm));
3851 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3854 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3857 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3862 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3863 unsigned rot = fieldFromInstruction(Val, 7, 5);
3864 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3865 Inst.addOperand(MCOperand::CreateImm(imm));
3868 return MCDisassembler::Success;
3872 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3873 uint64_t Address, const void *Decoder){
3874 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3875 true, 2, Inst, Decoder))
3876 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3877 return MCDisassembler::Success;
3880 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3881 uint64_t Address, const void *Decoder){
3882 // Val is passed in as S:J1:J2:imm10:imm11
3883 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3884 // the encoded instruction. So here change to I1 and I2 values via:
3885 // I1 = NOT(J1 EOR S);
3886 // I2 = NOT(J2 EOR S);
3887 // and build the imm32 with one trailing zero as documented:
3888 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3889 unsigned S = (Val >> 23) & 1;
3890 unsigned J1 = (Val >> 22) & 1;
3891 unsigned J2 = (Val >> 21) & 1;
3892 unsigned I1 = !(J1 ^ S);
3893 unsigned I2 = !(J2 ^ S);
3894 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3895 int imm32 = SignExtend32<25>(tmp << 1);
3897 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3898 true, 4, Inst, Decoder))
3899 Inst.addOperand(MCOperand::CreateImm(imm32));
3900 return MCDisassembler::Success;
3903 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3904 uint64_t Address, const void *Decoder) {
3906 return MCDisassembler::Fail;
3908 Inst.addOperand(MCOperand::CreateImm(Val));
3909 return MCDisassembler::Success;
3912 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3913 uint64_t Address, const void *Decoder) {
3915 return MCDisassembler::Fail;
3917 Inst.addOperand(MCOperand::CreateImm(Val));
3918 return MCDisassembler::Success;
3921 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3922 uint64_t Address, const void *Decoder) {
3923 if (!Val) return MCDisassembler::Fail;
3924 Inst.addOperand(MCOperand::CreateImm(Val));
3925 return MCDisassembler::Success;
3928 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3929 uint64_t Address, const void *Decoder) {
3930 DecodeStatus S = MCDisassembler::Success;
3932 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3933 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3934 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3937 S = MCDisassembler::SoftFail;
3939 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3940 return MCDisassembler::Fail;
3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3942 return MCDisassembler::Fail;
3943 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3944 return MCDisassembler::Fail;
3949 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3950 uint64_t Address, const void *Decoder){
3951 DecodeStatus S = MCDisassembler::Success;
3953 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3954 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3955 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3956 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3958 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
3959 return MCDisassembler::Fail;
3961 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
3962 S = MCDisassembler::SoftFail;
3964 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3965 return MCDisassembler::Fail;
3966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3967 return MCDisassembler::Fail;
3968 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3969 return MCDisassembler::Fail;
3974 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3975 uint64_t Address, const void *Decoder) {
3976 DecodeStatus S = MCDisassembler::Success;
3978 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3979 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3980 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3981 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3982 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3983 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3985 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3988 return MCDisassembler::Fail;
3989 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3990 return MCDisassembler::Fail;
3991 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3992 return MCDisassembler::Fail;
3993 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3994 return MCDisassembler::Fail;
3999 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4000 uint64_t Address, const void *Decoder) {
4001 DecodeStatus S = MCDisassembler::Success;
4003 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4004 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4005 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4006 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4007 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4008 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4009 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4011 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4012 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4015 return MCDisassembler::Fail;
4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4017 return MCDisassembler::Fail;
4018 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4019 return MCDisassembler::Fail;
4020 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4021 return MCDisassembler::Fail;
4027 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4028 uint64_t Address, const void *Decoder) {
4029 DecodeStatus S = MCDisassembler::Success;
4031 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4032 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4033 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4034 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4035 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4036 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4038 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4041 return MCDisassembler::Fail;
4042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4043 return MCDisassembler::Fail;
4044 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4045 return MCDisassembler::Fail;
4046 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4047 return MCDisassembler::Fail;
4052 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4053 uint64_t Address, const void *Decoder) {
4054 DecodeStatus S = MCDisassembler::Success;
4056 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4057 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4058 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4059 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4060 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4061 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4063 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4066 return MCDisassembler::Fail;
4067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4068 return MCDisassembler::Fail;
4069 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4070 return MCDisassembler::Fail;
4071 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4072 return MCDisassembler::Fail;
4077 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4078 uint64_t Address, const void *Decoder) {
4079 DecodeStatus S = MCDisassembler::Success;
4081 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4082 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4083 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4084 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4085 unsigned size = fieldFromInstruction(Insn, 10, 2);
4091 return MCDisassembler::Fail;
4093 if (fieldFromInstruction(Insn, 4, 1))
4094 return MCDisassembler::Fail; // UNDEFINED
4095 index = fieldFromInstruction(Insn, 5, 3);
4098 if (fieldFromInstruction(Insn, 5, 1))
4099 return MCDisassembler::Fail; // UNDEFINED
4100 index = fieldFromInstruction(Insn, 6, 2);
4101 if (fieldFromInstruction(Insn, 4, 1))
4105 if (fieldFromInstruction(Insn, 6, 1))
4106 return MCDisassembler::Fail; // UNDEFINED
4107 index = fieldFromInstruction(Insn, 7, 1);
4109 switch (fieldFromInstruction(Insn, 4, 2)) {
4115 return MCDisassembler::Fail;
4120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4121 return MCDisassembler::Fail;
4122 if (Rm != 0xF) { // Writeback
4123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4124 return MCDisassembler::Fail;
4126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4127 return MCDisassembler::Fail;
4128 Inst.addOperand(MCOperand::CreateImm(align));
4131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4132 return MCDisassembler::Fail;
4134 Inst.addOperand(MCOperand::CreateReg(0));
4137 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4138 return MCDisassembler::Fail;
4139 Inst.addOperand(MCOperand::CreateImm(index));
4144 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4145 uint64_t Address, const void *Decoder) {
4146 DecodeStatus S = MCDisassembler::Success;
4148 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4149 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4150 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4151 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4152 unsigned size = fieldFromInstruction(Insn, 10, 2);
4158 return MCDisassembler::Fail;
4160 if (fieldFromInstruction(Insn, 4, 1))
4161 return MCDisassembler::Fail; // UNDEFINED
4162 index = fieldFromInstruction(Insn, 5, 3);
4165 if (fieldFromInstruction(Insn, 5, 1))
4166 return MCDisassembler::Fail; // UNDEFINED
4167 index = fieldFromInstruction(Insn, 6, 2);
4168 if (fieldFromInstruction(Insn, 4, 1))
4172 if (fieldFromInstruction(Insn, 6, 1))
4173 return MCDisassembler::Fail; // UNDEFINED
4174 index = fieldFromInstruction(Insn, 7, 1);
4176 switch (fieldFromInstruction(Insn, 4, 2)) {
4182 return MCDisassembler::Fail;
4187 if (Rm != 0xF) { // Writeback
4188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4189 return MCDisassembler::Fail;
4191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4192 return MCDisassembler::Fail;
4193 Inst.addOperand(MCOperand::CreateImm(align));
4196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4197 return MCDisassembler::Fail;
4199 Inst.addOperand(MCOperand::CreateReg(0));
4202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4203 return MCDisassembler::Fail;
4204 Inst.addOperand(MCOperand::CreateImm(index));
4210 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4211 uint64_t Address, const void *Decoder) {
4212 DecodeStatus S = MCDisassembler::Success;
4214 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4215 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4216 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4217 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4218 unsigned size = fieldFromInstruction(Insn, 10, 2);
4225 return MCDisassembler::Fail;
4227 index = fieldFromInstruction(Insn, 5, 3);
4228 if (fieldFromInstruction(Insn, 4, 1))
4232 index = fieldFromInstruction(Insn, 6, 2);
4233 if (fieldFromInstruction(Insn, 4, 1))
4235 if (fieldFromInstruction(Insn, 5, 1))
4239 if (fieldFromInstruction(Insn, 5, 1))
4240 return MCDisassembler::Fail; // UNDEFINED
4241 index = fieldFromInstruction(Insn, 7, 1);
4242 if (fieldFromInstruction(Insn, 4, 1) != 0)
4244 if (fieldFromInstruction(Insn, 6, 1))
4249 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4250 return MCDisassembler::Fail;
4251 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4252 return MCDisassembler::Fail;
4253 if (Rm != 0xF) { // Writeback
4254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4255 return MCDisassembler::Fail;
4257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4258 return MCDisassembler::Fail;
4259 Inst.addOperand(MCOperand::CreateImm(align));
4262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4263 return MCDisassembler::Fail;
4265 Inst.addOperand(MCOperand::CreateReg(0));
4268 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4269 return MCDisassembler::Fail;
4270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4271 return MCDisassembler::Fail;
4272 Inst.addOperand(MCOperand::CreateImm(index));
4277 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4278 uint64_t Address, const void *Decoder) {
4279 DecodeStatus S = MCDisassembler::Success;
4281 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4282 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4283 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4284 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4285 unsigned size = fieldFromInstruction(Insn, 10, 2);
4292 return MCDisassembler::Fail;
4294 index = fieldFromInstruction(Insn, 5, 3);
4295 if (fieldFromInstruction(Insn, 4, 1))
4299 index = fieldFromInstruction(Insn, 6, 2);
4300 if (fieldFromInstruction(Insn, 4, 1))
4302 if (fieldFromInstruction(Insn, 5, 1))
4306 if (fieldFromInstruction(Insn, 5, 1))
4307 return MCDisassembler::Fail; // UNDEFINED
4308 index = fieldFromInstruction(Insn, 7, 1);
4309 if (fieldFromInstruction(Insn, 4, 1) != 0)
4311 if (fieldFromInstruction(Insn, 6, 1))
4316 if (Rm != 0xF) { // Writeback
4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4318 return MCDisassembler::Fail;
4320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4321 return MCDisassembler::Fail;
4322 Inst.addOperand(MCOperand::CreateImm(align));
4325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4326 return MCDisassembler::Fail;
4328 Inst.addOperand(MCOperand::CreateReg(0));
4331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4332 return MCDisassembler::Fail;
4333 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4334 return MCDisassembler::Fail;
4335 Inst.addOperand(MCOperand::CreateImm(index));
4341 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4342 uint64_t Address, const void *Decoder) {
4343 DecodeStatus S = MCDisassembler::Success;
4345 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4346 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4347 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4348 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4349 unsigned size = fieldFromInstruction(Insn, 10, 2);
4356 return MCDisassembler::Fail;
4358 if (fieldFromInstruction(Insn, 4, 1))
4359 return MCDisassembler::Fail; // UNDEFINED
4360 index = fieldFromInstruction(Insn, 5, 3);
4363 if (fieldFromInstruction(Insn, 4, 1))
4364 return MCDisassembler::Fail; // UNDEFINED
4365 index = fieldFromInstruction(Insn, 6, 2);
4366 if (fieldFromInstruction(Insn, 5, 1))
4370 if (fieldFromInstruction(Insn, 4, 2))
4371 return MCDisassembler::Fail; // UNDEFINED
4372 index = fieldFromInstruction(Insn, 7, 1);
4373 if (fieldFromInstruction(Insn, 6, 1))
4378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4379 return MCDisassembler::Fail;
4380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4381 return MCDisassembler::Fail;
4382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4383 return MCDisassembler::Fail;
4385 if (Rm != 0xF) { // Writeback
4386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4387 return MCDisassembler::Fail;
4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4390 return MCDisassembler::Fail;
4391 Inst.addOperand(MCOperand::CreateImm(align));
4394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4395 return MCDisassembler::Fail;
4397 Inst.addOperand(MCOperand::CreateReg(0));
4400 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4401 return MCDisassembler::Fail;
4402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4405 return MCDisassembler::Fail;
4406 Inst.addOperand(MCOperand::CreateImm(index));
4411 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4412 uint64_t Address, const void *Decoder) {
4413 DecodeStatus S = MCDisassembler::Success;
4415 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4416 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4417 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4418 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4419 unsigned size = fieldFromInstruction(Insn, 10, 2);
4426 return MCDisassembler::Fail;
4428 if (fieldFromInstruction(Insn, 4, 1))
4429 return MCDisassembler::Fail; // UNDEFINED
4430 index = fieldFromInstruction(Insn, 5, 3);
4433 if (fieldFromInstruction(Insn, 4, 1))
4434 return MCDisassembler::Fail; // UNDEFINED
4435 index = fieldFromInstruction(Insn, 6, 2);
4436 if (fieldFromInstruction(Insn, 5, 1))
4440 if (fieldFromInstruction(Insn, 4, 2))
4441 return MCDisassembler::Fail; // UNDEFINED
4442 index = fieldFromInstruction(Insn, 7, 1);
4443 if (fieldFromInstruction(Insn, 6, 1))
4448 if (Rm != 0xF) { // Writeback
4449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4450 return MCDisassembler::Fail;
4452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4453 return MCDisassembler::Fail;
4454 Inst.addOperand(MCOperand::CreateImm(align));
4457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4458 return MCDisassembler::Fail;
4460 Inst.addOperand(MCOperand::CreateReg(0));
4463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4464 return MCDisassembler::Fail;
4465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4466 return MCDisassembler::Fail;
4467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4468 return MCDisassembler::Fail;
4469 Inst.addOperand(MCOperand::CreateImm(index));
4475 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4476 uint64_t Address, const void *Decoder) {
4477 DecodeStatus S = MCDisassembler::Success;
4479 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4480 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4481 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4482 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4483 unsigned size = fieldFromInstruction(Insn, 10, 2);
4490 return MCDisassembler::Fail;
4492 if (fieldFromInstruction(Insn, 4, 1))
4494 index = fieldFromInstruction(Insn, 5, 3);
4497 if (fieldFromInstruction(Insn, 4, 1))
4499 index = fieldFromInstruction(Insn, 6, 2);
4500 if (fieldFromInstruction(Insn, 5, 1))
4504 switch (fieldFromInstruction(Insn, 4, 2)) {
4508 return MCDisassembler::Fail;
4510 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4513 index = fieldFromInstruction(Insn, 7, 1);
4514 if (fieldFromInstruction(Insn, 6, 1))
4519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4520 return MCDisassembler::Fail;
4521 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4522 return MCDisassembler::Fail;
4523 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4524 return MCDisassembler::Fail;
4525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4526 return MCDisassembler::Fail;
4528 if (Rm != 0xF) { // Writeback
4529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4530 return MCDisassembler::Fail;
4532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4533 return MCDisassembler::Fail;
4534 Inst.addOperand(MCOperand::CreateImm(align));
4537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4538 return MCDisassembler::Fail;
4540 Inst.addOperand(MCOperand::CreateReg(0));
4543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4544 return MCDisassembler::Fail;
4545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4546 return MCDisassembler::Fail;
4547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4548 return MCDisassembler::Fail;
4549 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4550 return MCDisassembler::Fail;
4551 Inst.addOperand(MCOperand::CreateImm(index));
4556 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4557 uint64_t Address, const void *Decoder) {
4558 DecodeStatus S = MCDisassembler::Success;
4560 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4561 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4562 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4563 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4564 unsigned size = fieldFromInstruction(Insn, 10, 2);
4571 return MCDisassembler::Fail;
4573 if (fieldFromInstruction(Insn, 4, 1))
4575 index = fieldFromInstruction(Insn, 5, 3);
4578 if (fieldFromInstruction(Insn, 4, 1))
4580 index = fieldFromInstruction(Insn, 6, 2);
4581 if (fieldFromInstruction(Insn, 5, 1))
4585 switch (fieldFromInstruction(Insn, 4, 2)) {
4589 return MCDisassembler::Fail;
4591 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4594 index = fieldFromInstruction(Insn, 7, 1);
4595 if (fieldFromInstruction(Insn, 6, 1))
4600 if (Rm != 0xF) { // Writeback
4601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4602 return MCDisassembler::Fail;
4604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4605 return MCDisassembler::Fail;
4606 Inst.addOperand(MCOperand::CreateImm(align));
4609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4610 return MCDisassembler::Fail;
4612 Inst.addOperand(MCOperand::CreateReg(0));
4615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4616 return MCDisassembler::Fail;
4617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4618 return MCDisassembler::Fail;
4619 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4620 return MCDisassembler::Fail;
4621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4622 return MCDisassembler::Fail;
4623 Inst.addOperand(MCOperand::CreateImm(index));
4628 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4629 uint64_t Address, const void *Decoder) {
4630 DecodeStatus S = MCDisassembler::Success;
4631 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4632 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4633 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4634 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4635 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4637 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4638 S = MCDisassembler::SoftFail;
4640 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4641 return MCDisassembler::Fail;
4642 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4643 return MCDisassembler::Fail;
4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4645 return MCDisassembler::Fail;
4646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4647 return MCDisassembler::Fail;
4648 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4649 return MCDisassembler::Fail;
4654 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4655 uint64_t Address, const void *Decoder) {
4656 DecodeStatus S = MCDisassembler::Success;
4657 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4658 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4659 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4660 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4661 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4663 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4664 S = MCDisassembler::SoftFail;
4666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4667 return MCDisassembler::Fail;
4668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4669 return MCDisassembler::Fail;
4670 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4671 return MCDisassembler::Fail;
4672 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4673 return MCDisassembler::Fail;
4674 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4675 return MCDisassembler::Fail;
4680 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4681 uint64_t Address, const void *Decoder) {
4682 DecodeStatus S = MCDisassembler::Success;
4683 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4684 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4688 S = MCDisassembler::SoftFail;
4692 return MCDisassembler::Fail;
4694 Inst.addOperand(MCOperand::CreateImm(pred));
4695 Inst.addOperand(MCOperand::CreateImm(mask));
4700 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4701 uint64_t Address, const void *Decoder) {
4702 DecodeStatus S = MCDisassembler::Success;
4704 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4705 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4706 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4707 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4708 unsigned W = fieldFromInstruction(Insn, 21, 1);
4709 unsigned U = fieldFromInstruction(Insn, 23, 1);
4710 unsigned P = fieldFromInstruction(Insn, 24, 1);
4711 bool writeback = (W == 1) | (P == 0);
4713 addr |= (U << 8) | (Rn << 9);
4715 if (writeback && (Rn == Rt || Rn == Rt2))
4716 Check(S, MCDisassembler::SoftFail);
4718 Check(S, MCDisassembler::SoftFail);
4721 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4722 return MCDisassembler::Fail;
4724 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4725 return MCDisassembler::Fail;
4726 // Writeback operand
4727 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4728 return MCDisassembler::Fail;
4730 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4731 return MCDisassembler::Fail;
4737 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4738 uint64_t Address, const void *Decoder) {
4739 DecodeStatus S = MCDisassembler::Success;
4741 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4742 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4743 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4744 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4745 unsigned W = fieldFromInstruction(Insn, 21, 1);
4746 unsigned U = fieldFromInstruction(Insn, 23, 1);
4747 unsigned P = fieldFromInstruction(Insn, 24, 1);
4748 bool writeback = (W == 1) | (P == 0);
4750 addr |= (U << 8) | (Rn << 9);
4752 if (writeback && (Rn == Rt || Rn == Rt2))
4753 Check(S, MCDisassembler::SoftFail);
4755 // Writeback operand
4756 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4757 return MCDisassembler::Fail;
4759 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4760 return MCDisassembler::Fail;
4762 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4763 return MCDisassembler::Fail;
4765 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4766 return MCDisassembler::Fail;
4771 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4772 uint64_t Address, const void *Decoder) {
4773 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4774 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4775 if (sign1 != sign2) return MCDisassembler::Fail;
4777 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4778 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4779 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4781 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4783 return MCDisassembler::Success;
4786 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4788 const void *Decoder) {
4789 DecodeStatus S = MCDisassembler::Success;
4791 // Shift of "asr #32" is not allowed in Thumb2 mode.
4792 if (Val == 0x20) S = MCDisassembler::SoftFail;
4793 Inst.addOperand(MCOperand::CreateImm(Val));
4797 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4798 uint64_t Address, const void *Decoder) {
4799 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4800 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4801 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4802 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4805 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4807 DecodeStatus S = MCDisassembler::Success;
4809 if (Rt == Rn || Rn == Rt2)
4810 S = MCDisassembler::SoftFail;
4812 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4813 return MCDisassembler::Fail;
4814 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4815 return MCDisassembler::Fail;
4816 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4817 return MCDisassembler::Fail;
4818 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4819 return MCDisassembler::Fail;
4824 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4825 uint64_t Address, const void *Decoder) {
4826 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4827 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4828 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4829 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4830 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4831 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4832 unsigned op = fieldFromInstruction(Insn, 5, 1);
4834 DecodeStatus S = MCDisassembler::Success;
4836 // VMOVv2f32 is ambiguous with these decodings.
4837 if (!(imm & 0x38) && cmode == 0xF) {
4838 if (op == 1) return MCDisassembler::Fail;
4839 Inst.setOpcode(ARM::VMOVv2f32);
4840 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4843 if (!(imm & 0x20)) return MCDisassembler::Fail;
4845 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4846 return MCDisassembler::Fail;
4847 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4848 return MCDisassembler::Fail;
4849 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4854 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4855 uint64_t Address, const void *Decoder) {
4856 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4857 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4858 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4859 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4860 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4861 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4862 unsigned op = fieldFromInstruction(Insn, 5, 1);
4864 DecodeStatus S = MCDisassembler::Success;
4866 // VMOVv4f32 is ambiguous with these decodings.
4867 if (!(imm & 0x38) && cmode == 0xF) {
4868 if (op == 1) return MCDisassembler::Fail;
4869 Inst.setOpcode(ARM::VMOVv4f32);
4870 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4873 if (!(imm & 0x20)) return MCDisassembler::Fail;
4875 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4876 return MCDisassembler::Fail;
4877 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4878 return MCDisassembler::Fail;
4879 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4884 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
4885 const void *Decoder)
4887 unsigned Imm = fieldFromInstruction(Insn, 0, 3);
4888 if (Imm > 4) return MCDisassembler::Fail;
4889 Inst.addOperand(MCOperand::CreateImm(Imm));
4890 return MCDisassembler::Success;
4893 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4894 uint64_t Address, const void *Decoder) {
4895 DecodeStatus S = MCDisassembler::Success;
4897 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4898 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4899 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4900 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4901 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4903 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4904 S = MCDisassembler::SoftFail;
4906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4907 return MCDisassembler::Fail;
4908 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4909 return MCDisassembler::Fail;
4910 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4911 return MCDisassembler::Fail;
4912 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4913 return MCDisassembler::Fail;
4914 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4915 return MCDisassembler::Fail;
4920 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4921 uint64_t Address, const void *Decoder) {
4923 DecodeStatus S = MCDisassembler::Success;
4925 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4926 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4927 unsigned cop = fieldFromInstruction(Val, 8, 4);
4928 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4929 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4931 if ((cop & ~0x1) == 0xa)
4932 return MCDisassembler::Fail;
4935 S = MCDisassembler::SoftFail;
4937 Inst.addOperand(MCOperand::CreateImm(cop));
4938 Inst.addOperand(MCOperand::CreateImm(opc1));
4939 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4940 return MCDisassembler::Fail;
4941 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4942 return MCDisassembler::Fail;
4943 Inst.addOperand(MCOperand::CreateImm(CRm));