1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to implement the public interfaces of ARMDisassembler and
12 // ThumbDisassembler, both of which are instances of MCDisassembler.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassembler.h"
19 #include "ARMDisassemblerCore.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Target/TargetRegistry.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
28 /// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from
29 /// ARMDecoderEmitter.cpp TableGen backend. It contains:
31 /// o Mappings from opcode to ARM/Thumb instruction format
33 /// o static uint16_t decodeInstruction(uint32_t insn) - the decoding function
34 /// for an ARM instruction.
36 /// o static uint16_t decodeThumbInstruction(field_t insn) - the decoding
37 /// function for a Thumb instruction.
39 #include "../ARMGenDecoderTables.inc"
43 /// showBitVector - Use the raw_ostream to log a diagnostic message describing
44 /// the inidividual bits of the instruction.
46 static inline void showBitVector(raw_ostream &os, const uint32_t &insn) {
47 // Split the bit position markers into more than one lines to fit 80 columns.
48 os << " 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11"
49 << " 10 9 8 7 6 5 4 3 2 1 0 \n";
50 os << "---------------------------------------------------------------"
51 << "----------------------------------\n";
53 for (unsigned i = 32; i != 0; --i) {
54 if (insn >> (i - 1) & 0x01)
58 os << (i%4 == 1 ? '|' : ':');
61 // Split the bit position markers into more than one lines to fit 80 columns.
62 os << "---------------------------------------------------------------"
63 << "----------------------------------\n";
67 /// decodeARMInstruction is a decorator function which tries special cases of
68 /// instruction matching before calling the auto-generated decoder function.
69 static unsigned decodeARMInstruction(uint32_t &insn) {
70 if (slice(insn, 31, 28) == 15)
71 goto AutoGenedDecoder;
73 // Special case processing, if any, goes here....
75 // LLVM combines the offset mode of A8.6.197 & A8.6.198 into STRB.
76 // The insufficient encoding information of the combined instruction confuses
77 // the decoder wrt BFC/BFI. Therefore, we try to recover here.
78 // For BFC, Inst{27-21} = 0b0111110 & Inst{6-0} = 0b0011111.
79 // For BFI, Inst{27-21} = 0b0111110 & Inst{6-4} = 0b001 & Inst{3-0} =! 0b1111.
80 if (slice(insn, 27, 21) == 0x3e && slice(insn, 6, 4) == 1) {
81 if (slice(insn, 3, 0) == 15)
87 // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
88 // As a result, the decoder fails to decode UMULL properly.
89 if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) {
93 // Ditto for STR_PRE, which is a super-instruction for A8.6.194 & A8.6.195.
94 // As a result, the decoder fails to decode SBFX properly.
95 if (slice(insn, 27, 21) == 0x3d && slice(insn, 6, 4) == 5)
98 // And STRB_PRE, which is a super-instruction for A8.6.197 & A8.6.198.
99 // As a result, the decoder fails to decode UBFX properly.
100 if (slice(insn, 27, 21) == 0x3f && slice(insn, 6, 4) == 5)
103 // Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1 & A2.
104 // As a result, the decoder fails to deocode SSAT properly.
105 if (slice(insn, 27, 21) == 0x35 && slice(insn, 5, 4) == 1)
106 return slice(insn, 6, 6) == 0 ? ARM::SSATlsl : ARM::SSATasr;
108 // Ditto for RSCrs, which is a super-instruction for A8.6.146 & A8.6.147.
109 // As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
110 if (slice(insn, 27, 24) == 0) {
111 switch (slice(insn, 21, 20)) {
113 switch (slice(insn, 7, 4)) {
117 break; // fallthrough
121 switch (slice(insn, 7, 4)) {
129 break; // fallthrough
133 break; // fallthrough
137 // Ditto for SBCrs, which is a super-instruction for A8.6.152 & A8.6.153.
138 // As a result, the decoder fails to decode STRH_Post/LDRD_POST/STRD_POST
140 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 0) {
141 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
142 switch (slice(insn, 7, 4)) {
147 case 3: // Pre-indexed
148 return ARM::STRH_PRE;
149 case 0: // Post-indexed
150 return ARM::STRH_POST;
152 break; // fallthrough
159 case 3: // Pre-indexed
160 return ARM::LDRD_PRE;
161 case 0: // Post-indexed
162 return ARM::LDRD_POST;
164 break; // fallthrough
171 case 3: // Pre-indexed
172 return ARM::STRD_PRE;
173 case 0: // Post-indexed
174 return ARM::STRD_POST;
176 break; // fallthrough
180 break; // fallthrough
184 // Ditto for SBCSSrs, which is a super-instruction for A8.6.152 & A8.6.153.
185 // As a result, the decoder fails to decode LDRH_POST/LDRSB_POST/LDRSH_POST
187 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 1) {
188 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
189 switch (slice(insn, 7, 4)) {
194 case 3: // Pre-indexed
195 return ARM::LDRH_PRE;
196 case 0: // Post-indexed
197 return ARM::LDRH_POST;
199 break; // fallthrough
206 case 3: // Pre-indexed
207 return ARM::LDRSB_PRE;
208 case 0: // Post-indexed
209 return ARM::LDRSB_POST;
211 break; // fallthrough
218 case 3: // Pre-indexed
219 return ARM::LDRSH_PRE;
220 case 0: // Post-indexed
221 return ARM::LDRSH_POST;
223 break; // fallthrough
227 break; // fallthrough
232 // Calling the auto-generated decoder function.
233 return decodeInstruction(insn);
236 // Helper function for special case handling of LDR (literal) and friends.
237 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
238 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
239 // before returning it.
240 static unsigned T2Morph2LoadLiteral(unsigned Opcode) {
243 return Opcode; // Return unmorphed opcode.
246 return ARM::t2LDRDpci;
248 case ARM::t2LDR_POST: case ARM::t2LDR_PRE:
249 case ARM::t2LDRi12: case ARM::t2LDRi8:
251 return ARM::t2LDRpci;
253 case ARM::t2LDRB_POST: case ARM::t2LDRB_PRE:
254 case ARM::t2LDRBi12: case ARM::t2LDRBi8:
256 return ARM::t2LDRBpci;
258 case ARM::t2LDRH_POST: case ARM::t2LDRH_PRE:
259 case ARM::t2LDRHi12: case ARM::t2LDRHi8:
261 return ARM::t2LDRHpci;
263 case ARM::t2LDRSB_POST: case ARM::t2LDRSB_PRE:
264 case ARM::t2LDRSBi12: case ARM::t2LDRSBi8:
266 return ARM::t2LDRSBpci;
268 case ARM::t2LDRSH_POST: case ARM::t2LDRSH_PRE:
269 case ARM::t2LDRSHi12: case ARM::t2LDRSHi8:
271 return ARM::t2LDRSHpci;
275 /// decodeThumbSideEffect is a decorator function which can potentially twiddle
276 /// the instruction or morph the returned opcode under Thumb2.
278 /// First it checks whether the insn is a NEON or VFP instr; if true, bit
279 /// twiddling could be performed on insn to turn it into an ARM NEON/VFP
280 /// equivalent instruction and decodeInstruction is called with the transformed
283 /// Next, there is special handling for Load byte/halfword/word instruction by
284 /// checking whether Rn=0b1111 and call T2Morph2LoadLiteral() on the decoded
285 /// Thumb2 instruction. See comments below for further details.
287 /// Finally, one last check is made to see whether the insn is a NEON/VFP and
288 /// decodeInstruction(insn) is invoked on the original insn.
290 /// Otherwise, decodeThumbInstruction is called with the original insn.
291 static unsigned decodeThumbSideEffect(bool IsThumb2, uint32_t &insn) {
293 uint16_t op1 = slice(insn, 28, 27);
294 uint16_t op2 = slice(insn, 26, 20);
296 // A6.3 32-bit Thumb instruction encoding
297 // Table A6-9 32-bit Thumb instruction encoding
299 // The coprocessor instructions of interest are transformed to their ARM
302 // --------- Transform Begin Marker ---------
303 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 4) == 7) {
304 // A7.4 Advanced SIMD data-processing instructions
305 // U bit of Thumb corresponds to Inst{24} of ARM.
306 uint16_t U = slice(op1, 1, 1);
308 // Inst{28-24} of ARM = {1,0,0,1,U};
309 uint16_t bits28_24 = 9 << 1 | U;
310 DEBUG(showBitVector(errs(), insn));
311 setSlice(insn, 28, 24, bits28_24);
312 return decodeInstruction(insn);
315 if (op1 == 3 && slice(op2, 6, 4) == 1 && slice(op2, 0, 0) == 0) {
316 // A7.7 Advanced SIMD element or structure load/store instructions
317 // Inst{27-24} of Thumb = 0b1001
318 // Inst{27-24} of ARM = 0b0100
319 DEBUG(showBitVector(errs(), insn));
320 setSlice(insn, 27, 24, 4);
321 return decodeInstruction(insn);
323 // --------- Transform End Marker ---------
325 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
326 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
327 // before returning it to our caller.
328 if (op1 == 3 && slice(op2, 6, 5) == 0 && slice(op2, 0, 0) == 1
329 && slice(insn, 19, 16) == 15)
330 return T2Morph2LoadLiteral(decodeThumbInstruction(insn));
332 // One last check for NEON/VFP instructions.
333 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 6) == 1)
334 return decodeInstruction(insn);
339 return decodeThumbInstruction(insn);
342 static inline bool Thumb2PreloadOpcodeNoPCI(unsigned Opcode) {
346 case ARM::t2PLDi12: case ARM::t2PLDi8:
347 case ARM::t2PLDr: case ARM::t2PLDs:
348 case ARM::t2PLDWi12: case ARM::t2PLDWi8:
349 case ARM::t2PLDWr: case ARM::t2PLDWs:
350 case ARM::t2PLIi12: case ARM::t2PLIi8:
351 case ARM::t2PLIr: case ARM::t2PLIs:
356 static inline unsigned T2Morph2Preload2PCI(unsigned Opcode) {
360 case ARM::t2PLDi12: case ARM::t2PLDi8:
361 case ARM::t2PLDr: case ARM::t2PLDs:
362 return ARM::t2PLDpci;
363 case ARM::t2PLDWi12: case ARM::t2PLDWi8:
364 case ARM::t2PLDWr: case ARM::t2PLDWs:
365 return ARM::t2PLDWpci;
366 case ARM::t2PLIi12: case ARM::t2PLIi8:
367 case ARM::t2PLIr: case ARM::t2PLIs:
368 return ARM::t2PLIpci;
373 // Public interface for the disassembler
376 bool ARMDisassembler::getInstruction(MCInst &MI,
378 const MemoryObject &Region,
380 raw_ostream &os) const {
381 // The machine instruction.
385 // We want to read exactly 4 bytes of data.
386 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
389 // Encoded as a small-endian 32-bit word in the stream.
390 insn = (bytes[3] << 24) |
395 unsigned Opcode = decodeARMInstruction(insn);
396 ARMFormat Format = ARMFormats[Opcode];
400 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
401 << " Format=" << stringForARMFormat(Format) << '(' << (int)Format
403 showBitVector(errs(), insn);
406 ARMBasicMCBuilder *Builder = CreateMCBuilder(Opcode, Format);
411 if (!Builder->Build(MI, insn))
419 bool ThumbDisassembler::getInstruction(MCInst &MI,
421 const MemoryObject &Region,
423 raw_ostream &os) const {
424 // The Thumb instruction stream is a sequence of halhwords.
426 // This represents the first halfword as well as the machine instruction
427 // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top
428 // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to
429 // the top half followed by the second halfword.
431 // Possible second halfword.
434 // A6.1 Thumb instruction set encoding
436 // If bits [15:11] of the halfword being decoded take any of the following
437 // values, the halfword is the first halfword of a 32-bit instruction:
442 // Otherwise, the halfword is a 16-bit instruction.
444 // Read 2 bytes of data first.
446 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
449 // Encoded as a small-endian 16-bit halfword in the stream.
450 insn = (bytes[1] << 8) | bytes[0];
451 unsigned bits15_11 = slice(insn, 15, 11);
452 bool IsThumb2 = false;
454 // 32-bit instructions if the bits [15:11] of the halfword matches
455 // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }.
456 if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) {
458 if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1)
460 // Encoded as a small-endian 16-bit halfword in the stream.
461 insn1 = (bytes[1] << 8) | bytes[0];
462 insn = (insn << 16 | insn1);
465 // The insn could potentially be bit-twiddled in order to be decoded as an ARM
466 // NEON/VFP opcode. In such case, the modified insn is later disassembled as
467 // an ARM NEON/VFP instruction.
469 // This is a short term solution for lack of encoding bits specified for the
470 // Thumb2 NEON/VFP instructions. The long term solution could be adding some
471 // infrastructure to have each instruction support more than one encodings.
472 // Which encoding is used would be based on which subtarget the compiler/
473 // disassembler is working with at the time. This would allow the sharing of
474 // the NEON patterns between ARM and Thumb2, as well as potential greater
475 // sharing between the regular ARM instructions and the 32-bit wide Thumb2
476 // instructions as well.
477 unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
479 // A8.6.117/119/120/121.
480 // PLD/PLDW/PLI instructions with Rn==15 is transformed to the pci variant.
481 if (Thumb2PreloadOpcodeNoPCI(Opcode) && slice(insn, 19, 16) == 15)
482 Opcode = T2Morph2Preload2PCI(Opcode);
484 ARMFormat Format = ARMFormats[Opcode];
485 Size = IsThumb2 ? 4 : 2;
488 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
489 << " Format=" << stringForARMFormat(Format) << '(' << (int)Format
491 showBitVector(errs(), insn);
494 ARMBasicMCBuilder *Builder = CreateMCBuilder(Opcode, Format);
495 Builder->setSession(const_cast<Session *>(&SO));
500 if (!Builder->Build(MI, insn))
509 static unsigned short CountITSize(unsigned ITMask) {
510 // First count the trailing zeros of the IT mask.
511 unsigned TZ = CountTrailingZeros_32(ITMask);
512 assert(TZ <= 3 && "Encoding error");
517 void Session::InitIT(unsigned short bits7_0) {
518 ITCounter = CountITSize(slice(bits7_0, 3, 0));
522 /// Update ITState if necessary.
523 void Session::UpdateIT() {
529 unsigned short NewITState4_0 = slice(ITState, 4, 0) << 1;
530 setSlice(ITState, 4, 0, NewITState4_0);
534 static MCDisassembler *createARMDisassembler(const Target &T) {
535 return new ARMDisassembler;
538 static MCDisassembler *createThumbDisassembler(const Target &T) {
539 return new ThumbDisassembler;
542 extern "C" void LLVMInitializeARMDisassembler() {
543 // Register the disassembler.
544 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
545 createARMDisassembler);
546 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
547 createThumbDisassembler);