1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to implement the public interfaces of ARMDisassembler and
12 // ThumbDisassembler, both of which are instances of MCDisassembler.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassembler.h"
19 #include "ARMDisassemblerCore.h"
21 #include "llvm/MC/EDInstInfo.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
29 //#define DEBUG(X) do { X; } while (0)
31 /// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from
32 /// ARMDecoderEmitter.cpp TableGen backend. It contains:
34 /// o Mappings from opcode to ARM/Thumb instruction format
36 /// o static uint16_t decodeInstruction(uint32_t insn) - the decoding function
37 /// for an ARM instruction.
39 /// o static uint16_t decodeThumbInstruction(field_t insn) - the decoding
40 /// function for a Thumb instruction.
42 #include "ARMGenDecoderTables.inc"
44 #include "ARMGenEDInfo.inc"
48 /// showBitVector - Use the raw_ostream to log a diagnostic message describing
49 /// the inidividual bits of the instruction.
51 static inline void showBitVector(raw_ostream &os, const uint32_t &insn) {
52 // Split the bit position markers into more than one lines to fit 80 columns.
53 os << " 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11"
54 << " 10 9 8 7 6 5 4 3 2 1 0 \n";
55 os << "---------------------------------------------------------------"
56 << "----------------------------------\n";
58 for (unsigned i = 32; i != 0; --i) {
59 if (insn >> (i - 1) & 0x01)
63 os << (i%4 == 1 ? '|' : ':');
66 // Split the bit position markers into more than one lines to fit 80 columns.
67 os << "---------------------------------------------------------------"
68 << "----------------------------------\n";
72 /// decodeARMInstruction is a decorator function which tries special cases of
73 /// instruction matching before calling the auto-generated decoder function.
74 static unsigned decodeARMInstruction(uint32_t &insn) {
75 if (slice(insn, 31, 28) == 15)
76 goto AutoGenedDecoder;
78 // Special case processing, if any, goes here....
80 // LLVM combines the offset mode of A8.6.197 & A8.6.198 into STRB.
81 // The insufficient encoding information of the combined instruction confuses
82 // the decoder wrt BFC/BFI. Therefore, we try to recover here.
83 // For BFC, Inst{27-21} = 0b0111110 & Inst{6-0} = 0b0011111.
84 // For BFI, Inst{27-21} = 0b0111110 & Inst{6-4} = 0b001 & Inst{3-0} =! 0b1111.
85 if (slice(insn, 27, 21) == 0x3e && slice(insn, 6, 4) == 1) {
86 if (slice(insn, 3, 0) == 15)
92 // Ditto for STRBT, which is a super-instruction for A8.6.199 Encodings
94 // As a result, the decoder fails to deocode USAT properly.
95 if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
97 // As a result, the decoder fails to deocode UQADD16 properly.
98 if (slice(insn, 27, 20) == 0x66 && slice(insn, 7, 4) == 1)
101 // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
102 // As a result, the decoder fails to decode UMULL properly.
103 if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) {
107 // Ditto for STR_PRE, which is a super-instruction for A8.6.194 & A8.6.195.
108 // As a result, the decoder fails to decode SBFX properly.
109 if (slice(insn, 27, 21) == 0x3d && slice(insn, 6, 4) == 5)
112 // And STRB_PRE, which is a super-instruction for A8.6.197 & A8.6.198.
113 // As a result, the decoder fails to decode UBFX properly.
114 if (slice(insn, 27, 21) == 0x3f && slice(insn, 6, 4) == 5)
117 // Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1 & A2.
118 // As a result, the decoder fails to deocode SSAT properly.
119 if (slice(insn, 27, 21) == 0x35 && slice(insn, 5, 4) == 1)
122 // Ditto for RSCrs, which is a super-instruction for A8.6.146 & A8.6.147.
123 // As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
124 if (slice(insn, 27, 24) == 0) {
125 switch (slice(insn, 21, 20)) {
127 switch (slice(insn, 7, 4)) {
131 break; // fallthrough
135 switch (slice(insn, 7, 4)) {
143 break; // fallthrough
147 break; // fallthrough
151 // Ditto for SBCrs, which is a super-instruction for A8.6.152 & A8.6.153.
152 // As a result, the decoder fails to decode STRH_Post/LDRD_POST/STRD_POST
154 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 0) {
155 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
156 switch (slice(insn, 7, 4)) {
161 case 3: // Pre-indexed
162 return ARM::STRH_PRE;
163 case 0: // Post-indexed
164 return ARM::STRH_POST;
166 break; // fallthrough
173 case 3: // Pre-indexed
174 return ARM::LDRD_PRE;
175 case 0: // Post-indexed
176 return ARM::LDRD_POST;
178 break; // fallthrough
185 case 3: // Pre-indexed
186 return ARM::STRD_PRE;
187 case 0: // Post-indexed
188 return ARM::STRD_POST;
190 break; // fallthrough
194 break; // fallthrough
198 // Ditto for SBCSSrs, which is a super-instruction for A8.6.152 & A8.6.153.
199 // As a result, the decoder fails to decode LDRH_POST/LDRSB_POST/LDRSH_POST
201 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 1) {
202 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
203 switch (slice(insn, 7, 4)) {
208 case 3: // Pre-indexed
209 return ARM::LDRH_PRE;
210 case 0: // Post-indexed
211 return ARM::LDRH_POST;
213 break; // fallthrough
220 case 3: // Pre-indexed
221 return ARM::LDRSB_PRE;
222 case 0: // Post-indexed
223 return ARM::LDRSB_POST;
225 break; // fallthrough
232 case 3: // Pre-indexed
233 return ARM::LDRSH_PRE;
234 case 0: // Post-indexed
235 return ARM::LDRSH_POST;
237 break; // fallthrough
241 break; // fallthrough
246 // Calling the auto-generated decoder function.
247 return decodeInstruction(insn);
250 // Helper function for special case handling of LDR (literal) and friends.
251 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
252 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
253 // before returning it.
254 static unsigned T2Morph2LoadLiteral(unsigned Opcode) {
257 return Opcode; // Return unmorphed opcode.
259 case ARM::t2LDR_POST: case ARM::t2LDR_PRE:
260 case ARM::t2LDRi12: case ARM::t2LDRi8:
261 case ARM::t2LDRs: case ARM::t2LDRT:
262 return ARM::t2LDRpci;
264 case ARM::t2LDRB_POST: case ARM::t2LDRB_PRE:
265 case ARM::t2LDRBi12: case ARM::t2LDRBi8:
266 case ARM::t2LDRBs: case ARM::t2LDRBT:
267 return ARM::t2LDRBpci;
269 case ARM::t2LDRH_POST: case ARM::t2LDRH_PRE:
270 case ARM::t2LDRHi12: case ARM::t2LDRHi8:
271 case ARM::t2LDRHs: case ARM::t2LDRHT:
272 return ARM::t2LDRHpci;
274 case ARM::t2LDRSB_POST: case ARM::t2LDRSB_PRE:
275 case ARM::t2LDRSBi12: case ARM::t2LDRSBi8:
276 case ARM::t2LDRSBs: case ARM::t2LDRSBT:
277 return ARM::t2LDRSBpci;
279 case ARM::t2LDRSH_POST: case ARM::t2LDRSH_PRE:
280 case ARM::t2LDRSHi12: case ARM::t2LDRSHi8:
281 case ARM::t2LDRSHs: case ARM::t2LDRSHT:
282 return ARM::t2LDRSHpci;
286 /// decodeThumbSideEffect is a decorator function which can potentially twiddle
287 /// the instruction or morph the returned opcode under Thumb2.
289 /// First it checks whether the insn is a NEON or VFP instr; if true, bit
290 /// twiddling could be performed on insn to turn it into an ARM NEON/VFP
291 /// equivalent instruction and decodeInstruction is called with the transformed
294 /// Next, there is special handling for Load byte/halfword/word instruction by
295 /// checking whether Rn=0b1111 and call T2Morph2LoadLiteral() on the decoded
296 /// Thumb2 instruction. See comments below for further details.
298 /// Finally, one last check is made to see whether the insn is a NEON/VFP and
299 /// decodeInstruction(insn) is invoked on the original insn.
301 /// Otherwise, decodeThumbInstruction is called with the original insn.
302 static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) {
304 uint16_t op1 = slice(insn, 28, 27);
305 uint16_t op2 = slice(insn, 26, 20);
307 // A6.3 32-bit Thumb instruction encoding
308 // Table A6-9 32-bit Thumb instruction encoding
310 // The coprocessor instructions of interest are transformed to their ARM
313 // --------- Transform Begin Marker ---------
314 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 4) == 7) {
315 // A7.4 Advanced SIMD data-processing instructions
316 // U bit of Thumb corresponds to Inst{24} of ARM.
317 uint16_t U = slice(op1, 1, 1);
319 // Inst{28-24} of ARM = {1,0,0,1,U};
320 uint16_t bits28_24 = 9 << 1 | U;
321 DEBUG(showBitVector(errs(), insn));
322 setSlice(insn, 28, 24, bits28_24);
323 return decodeInstruction(insn);
326 if (op1 == 3 && slice(op2, 6, 4) == 1 && slice(op2, 0, 0) == 0) {
327 // A7.7 Advanced SIMD element or structure load/store instructions
328 // Inst{27-24} of Thumb = 0b1001
329 // Inst{27-24} of ARM = 0b0100
330 DEBUG(showBitVector(errs(), insn));
331 setSlice(insn, 27, 24, 4);
332 return decodeInstruction(insn);
334 // --------- Transform End Marker ---------
336 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
337 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
338 // before returning it to our caller.
339 if (op1 == 3 && slice(op2, 6, 5) == 0 && slice(op2, 0, 0) == 1
340 && slice(insn, 19, 16) == 15)
341 return T2Morph2LoadLiteral(decodeThumbInstruction(insn));
343 // One last check for NEON/VFP instructions.
344 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 6) == 1)
345 return decodeInstruction(insn);
350 return decodeThumbInstruction(insn);
354 // Public interface for the disassembler
357 bool ARMDisassembler::getInstruction(MCInst &MI,
359 const MemoryObject &Region,
361 raw_ostream &os) const {
362 // The machine instruction.
366 // We want to read exactly 4 bytes of data.
367 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
370 // Encoded as a small-endian 32-bit word in the stream.
371 insn = (bytes[3] << 24) |
376 unsigned Opcode = decodeARMInstruction(insn);
377 ARMFormat Format = ARMFormats[Opcode];
381 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
382 << " Format=" << stringForARMFormat(Format) << '(' << (int)Format
384 showBitVector(errs(), insn);
387 ARMBasicMCBuilder *Builder = CreateMCBuilder(Opcode, Format);
391 if (!Builder->Build(MI, insn))
399 bool ThumbDisassembler::getInstruction(MCInst &MI,
401 const MemoryObject &Region,
403 raw_ostream &os) const {
404 // The Thumb instruction stream is a sequence of halhwords.
406 // This represents the first halfword as well as the machine instruction
407 // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top
408 // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to
409 // the top half followed by the second halfword.
411 // Possible second halfword.
414 // A6.1 Thumb instruction set encoding
416 // If bits [15:11] of the halfword being decoded take any of the following
417 // values, the halfword is the first halfword of a 32-bit instruction:
422 // Otherwise, the halfword is a 16-bit instruction.
424 // Read 2 bytes of data first.
426 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
429 // Encoded as a small-endian 16-bit halfword in the stream.
430 insn = (bytes[1] << 8) | bytes[0];
431 unsigned bits15_11 = slice(insn, 15, 11);
432 bool IsThumb2 = false;
434 // 32-bit instructions if the bits [15:11] of the halfword matches
435 // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }.
436 if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) {
438 if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1)
440 // Encoded as a small-endian 16-bit halfword in the stream.
441 insn1 = (bytes[1] << 8) | bytes[0];
442 insn = (insn << 16 | insn1);
445 // The insn could potentially be bit-twiddled in order to be decoded as an ARM
446 // NEON/VFP opcode. In such case, the modified insn is later disassembled as
447 // an ARM NEON/VFP instruction.
449 // This is a short term solution for lack of encoding bits specified for the
450 // Thumb2 NEON/VFP instructions. The long term solution could be adding some
451 // infrastructure to have each instruction support more than one encodings.
452 // Which encoding is used would be based on which subtarget the compiler/
453 // disassembler is working with at the time. This would allow the sharing of
454 // the NEON patterns between ARM and Thumb2, as well as potential greater
455 // sharing between the regular ARM instructions and the 32-bit wide Thumb2
456 // instructions as well.
457 unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
459 ARMFormat Format = ARMFormats[Opcode];
460 Size = IsThumb2 ? 4 : 2;
463 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
464 << " Format=" << stringForARMFormat(Format) << '(' << (int)Format
466 showBitVector(errs(), insn);
469 ARMBasicMCBuilder *Builder = CreateMCBuilder(Opcode, Format);
473 Builder->SetSession(const_cast<Session *>(&SO));
475 if (!Builder->Build(MI, insn))
484 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
485 static unsigned short CountITSize(unsigned ITMask) {
486 // First count the trailing zeros of the IT mask.
487 unsigned TZ = CountTrailingZeros_32(ITMask);
489 DEBUG(errs() << "Encoding error: IT Mask '0000'");
495 /// Init ITState. Note that at least one bit is always 1 in mask.
496 bool Session::InitIT(unsigned short bits7_0) {
497 ITCounter = CountITSize(slice(bits7_0, 3, 0));
502 unsigned short FirstCond = slice(bits7_0, 7, 4);
503 if (FirstCond == 0xF) {
504 DEBUG(errs() << "Encoding error: IT FirstCond '1111'");
507 if (FirstCond == 0xE && ITCounter != 1) {
508 DEBUG(errs() << "Encoding error: IT FirstCond '1110' && Mask != '1000'");
517 /// Update ITState if necessary.
518 void Session::UpdateIT() {
524 unsigned short NewITState4_0 = slice(ITState, 4, 0) << 1;
525 setSlice(ITState, 4, 0, NewITState4_0);
529 static MCDisassembler *createARMDisassembler(const Target &T) {
530 return new ARMDisassembler;
533 static MCDisassembler *createThumbDisassembler(const Target &T) {
534 return new ThumbDisassembler;
537 extern "C" void LLVMInitializeARMDisassembler() {
538 // Register the disassembler.
539 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
540 createARMDisassembler);
541 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
542 createThumbDisassembler);
545 EDInstInfo *ARMDisassembler::getEDInfo() const {
549 EDInstInfo *ThumbDisassembler::getEDInfo() const {