1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "llvm/MC/EDInstInfo.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCFixedLenDisassembler.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/LEB128.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
33 typedef MCDisassembler::DecodeStatus DecodeStatus;
36 // Handles the condition code status of instructions in IT blocks
40 // Returns the condition code for instruction in IT block
42 unsigned CC = ARMCC::AL;
48 // Advances the IT block state to the next T or E
49 void advanceITState() {
53 // Returns true if the current instruction is in an IT block
54 bool instrInITBlock() {
55 return !ITStates.empty();
58 // Returns true if current instruction is the last instruction in an IT block
59 bool instrLastInITBlock() {
60 return ITStates.size() == 1;
63 // Called when decoding an IT instruction. Sets the IT state for the following
64 // instructions that for the IT block. Firstcond and Mask correspond to the
65 // fields in the IT instruction encoding.
66 void setITState(char Firstcond, char Mask) {
67 // (3 - the number of trailing zeros) is the number of then / else.
68 unsigned CondBit0 = Firstcond & 1;
69 unsigned NumTZ = CountTrailingZeros_32(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
74 bool T = ((Mask >> Pos) & 1) == CondBit0;
76 ITStates.push_back(CCBits);
78 ITStates.push_back(CCBits ^ 1);
80 ITStates.push_back(CCBits);
84 std::vector<unsigned char> ITStates;
89 /// ARMDisassembler - ARM disassembler for all ARM platforms.
90 class ARMDisassembler : public MCDisassembler {
92 /// Constructor - Initializes the disassembler.
94 ARMDisassembler(const MCSubtargetInfo &STI) :
101 /// getInstruction - See MCDisassembler.
102 DecodeStatus getInstruction(MCInst &instr,
104 const MemoryObject ®ion,
106 raw_ostream &vStream,
107 raw_ostream &cStream) const;
109 /// getEDInfo - See MCDisassembler.
110 const EDInstInfo *getEDInfo() const;
114 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
115 class ThumbDisassembler : public MCDisassembler {
117 /// Constructor - Initializes the disassembler.
119 ThumbDisassembler(const MCSubtargetInfo &STI) :
120 MCDisassembler(STI) {
123 ~ThumbDisassembler() {
126 /// getInstruction - See MCDisassembler.
127 DecodeStatus getInstruction(MCInst &instr,
129 const MemoryObject ®ion,
131 raw_ostream &vStream,
132 raw_ostream &cStream) const;
134 /// getEDInfo - See MCDisassembler.
135 const EDInstInfo *getEDInfo() const;
137 mutable ITStatus ITBlock;
138 DecodeStatus AddThumbPredicate(MCInst&) const;
139 void UpdateThumbVFPPredicate(MCInst&) const;
143 static bool Check(DecodeStatus &Out, DecodeStatus In) {
145 case MCDisassembler::Success:
146 // Out stays the same.
148 case MCDisassembler::SoftFail:
151 case MCDisassembler::Fail:
155 llvm_unreachable("Invalid DecodeStatus!");
159 // Forward declare these because the autogenerated code will reference them.
160 // Definitions are further down.
161 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
164 unsigned RegNo, uint64_t Address,
165 const void *Decoder);
166 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
181 const void *Decoder);
182 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
187 unsigned RegNo, uint64_t Address,
188 const void *Decoder);
190 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
210 const void *Decoder);
211 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
223 const void *Decoder);
224 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
387 #include "ARMGenDisassemblerTables.inc"
388 #include "ARMGenEDInfo.inc"
390 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
391 return new ARMDisassembler(STI);
394 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
395 return new ThumbDisassembler(STI);
398 const EDInstInfo *ARMDisassembler::getEDInfo() const {
402 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
406 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
407 const MemoryObject &Region,
410 raw_ostream &cs) const {
415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
418 // We want to read exactly 4 bytes of data.
419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
421 return MCDisassembler::Fail;
424 // Encoded as a small-endian 32-bit word in the stream.
425 uint32_t insn = (bytes[3] << 24) |
430 // Calling the auto-generated decoder function.
431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
433 if (result != MCDisassembler::Fail) {
438 // VFP and NEON instructions, similarly, are shared between ARM
441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
442 if (result != MCDisassembler::Fail) {
448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
450 if (result != MCDisassembler::Fail) {
452 // Add a fake predicate operand, because we share these instruction
453 // definitions with Thumb2 where these instructions are predicable.
454 if (!DecodePredicateOperand(MI, 0xE, Address, this))
455 return MCDisassembler::Fail;
460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
462 if (result != MCDisassembler::Fail) {
464 // Add a fake predicate operand, because we share these instruction
465 // definitions with Thumb2 where these instructions are predicable.
466 if (!DecodePredicateOperand(MI, 0xE, Address, this))
467 return MCDisassembler::Fail;
472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
474 if (result != MCDisassembler::Fail) {
476 // Add a fake predicate operand, because we share these instruction
477 // definitions with Thumb2 where these instructions are predicable.
478 if (!DecodePredicateOperand(MI, 0xE, Address, this))
479 return MCDisassembler::Fail;
486 return MCDisassembler::Fail;
490 extern const MCInstrDesc ARMInsts[];
493 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
494 /// immediate Value in the MCInst. The immediate Value has had any PC
495 /// adjustment made by the caller. If the instruction is a branch instruction
496 /// then isBranch is true, else false. If the getOpInfo() function was set as
497 /// part of the setupForSymbolicDisassembly() call then that function is called
498 /// to get any symbolic information at the Address for this instruction. If
499 /// that returns non-zero then the symbolic information it returns is used to
500 /// create an MCExpr and that is added as an operand to the MCInst. If
501 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
502 /// Value is done and if a symbol is found an MCExpr is created with that, else
503 /// an MCExpr with Value is created. This function returns true if it adds an
504 /// operand to the MCInst and false otherwise.
505 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
506 bool isBranch, uint64_t InstSize,
507 MCInst &MI, const void *Decoder) {
508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
510 struct LLVMOpInfo1 SymbolicOp;
511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
512 SymbolicOp.Value = Value;
513 void *DisInfo = Dis->getDisInfoBlock();
516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
517 // Clear SymbolicOp.Value from above and also all other fields.
518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
522 uint64_t ReferenceType;
524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
527 const char *ReferenceName;
528 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
531 SymbolicOp.AddSymbol.Name = Name;
532 SymbolicOp.AddSymbol.Present = true;
534 // For branches always create an MCExpr so it gets printed as hex address.
536 SymbolicOp.Value = Value;
538 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
539 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
540 if (!Name && !isBranch)
544 MCContext *Ctx = Dis->getMCContext();
545 const MCExpr *Add = NULL;
546 if (SymbolicOp.AddSymbol.Present) {
547 if (SymbolicOp.AddSymbol.Name) {
548 StringRef Name(SymbolicOp.AddSymbol.Name);
549 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
550 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
552 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
556 const MCExpr *Sub = NULL;
557 if (SymbolicOp.SubtractSymbol.Present) {
558 if (SymbolicOp.SubtractSymbol.Name) {
559 StringRef Name(SymbolicOp.SubtractSymbol.Name);
560 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
561 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
563 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
567 const MCExpr *Off = NULL;
568 if (SymbolicOp.Value != 0)
569 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
575 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
577 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
579 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
584 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
591 Expr = MCConstantExpr::Create(0, *Ctx);
594 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
595 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
596 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
597 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
598 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
599 MI.addOperand(MCOperand::CreateExpr(Expr));
601 llvm_unreachable("bad SymbolicOp.VariantKind");
606 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
607 /// referenced by a load instruction with the base register that is the Pc.
608 /// These can often be values in a literal pool near the Address of the
609 /// instruction. The Address of the instruction and its immediate Value are
610 /// used as a possible literal pool entry. The SymbolLookUp call back will
611 /// return the name of a symbol referenced by the literal pool's entry if
612 /// the referenced address is that of a symbol. Or it will return a pointer to
613 /// a literal 'C' string if the referenced address of the literal pool's entry
614 /// is an address into a section with 'C' string literals.
615 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
616 const void *Decoder) {
617 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
618 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
620 void *DisInfo = Dis->getDisInfoBlock();
621 uint64_t ReferenceType;
622 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
623 const char *ReferenceName;
624 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
625 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
626 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
627 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
631 // Thumb1 instructions don't have explicit S bits. Rather, they
632 // implicitly set CPSR. Since it's not represented in the encoding, the
633 // auto-generated decoder won't inject the CPSR operand. We need to fix
634 // that as a post-pass.
635 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
636 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
637 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
638 MCInst::iterator I = MI.begin();
639 for (unsigned i = 0; i < NumOps; ++i, ++I) {
640 if (I == MI.end()) break;
641 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
642 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
648 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
651 // Most Thumb instructions don't have explicit predicates in the
652 // encoding, but rather get their predicates from IT context. We need
653 // to fix up the predicate operands using this context information as a
655 MCDisassembler::DecodeStatus
656 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
657 MCDisassembler::DecodeStatus S = Success;
659 // A few instructions actually have predicates encoded in them. Don't
660 // try to overwrite it if we're seeing one of those.
661 switch (MI.getOpcode()) {
672 // Some instructions (mostly conditional branches) are not
673 // allowed in IT blocks.
674 if (ITBlock.instrInITBlock())
683 // Some instructions (mostly unconditional branches) can
684 // only appears at the end of, or outside of, an IT.
685 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
692 // If we're in an IT block, base the predicate on that. Otherwise,
693 // assume a predicate of AL.
695 CC = ITBlock.getITCC();
698 if (ITBlock.instrInITBlock())
699 ITBlock.advanceITState();
701 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
702 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
703 MCInst::iterator I = MI.begin();
704 for (unsigned i = 0; i < NumOps; ++i, ++I) {
705 if (I == MI.end()) break;
706 if (OpInfo[i].isPredicate()) {
707 I = MI.insert(I, MCOperand::CreateImm(CC));
710 MI.insert(I, MCOperand::CreateReg(0));
712 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
717 I = MI.insert(I, MCOperand::CreateImm(CC));
720 MI.insert(I, MCOperand::CreateReg(0));
722 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
727 // Thumb VFP instructions are a special case. Because we share their
728 // encodings between ARM and Thumb modes, and they are predicable in ARM
729 // mode, the auto-generated decoder will give them an (incorrect)
730 // predicate operand. We need to rewrite these operands based on the IT
731 // context as a post-pass.
732 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
734 CC = ITBlock.getITCC();
735 if (ITBlock.instrInITBlock())
736 ITBlock.advanceITState();
738 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
739 MCInst::iterator I = MI.begin();
740 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
741 for (unsigned i = 0; i < NumOps; ++i, ++I) {
742 if (OpInfo[i].isPredicate() ) {
748 I->setReg(ARM::CPSR);
754 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
755 const MemoryObject &Region,
758 raw_ostream &cs) const {
763 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
764 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
766 // We want to read exactly 2 bytes of data.
767 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
769 return MCDisassembler::Fail;
772 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
773 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
775 if (result != MCDisassembler::Fail) {
777 Check(result, AddThumbPredicate(MI));
782 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
786 bool InITBlock = ITBlock.instrInITBlock();
787 Check(result, AddThumbPredicate(MI));
788 AddThumb1SBit(MI, InITBlock);
793 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
795 if (result != MCDisassembler::Fail) {
798 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
799 // the Thumb predicate.
800 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
801 result = MCDisassembler::SoftFail;
803 Check(result, AddThumbPredicate(MI));
805 // If we find an IT instruction, we need to parse its condition
806 // code and mask operands so that we can apply them correctly
807 // to the subsequent instructions.
808 if (MI.getOpcode() == ARM::t2IT) {
810 unsigned Firstcond = MI.getOperand(0).getImm();
811 unsigned Mask = MI.getOperand(1).getImm();
812 ITBlock.setITState(Firstcond, Mask);
818 // We want to read exactly 4 bytes of data.
819 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
821 return MCDisassembler::Fail;
824 uint32_t insn32 = (bytes[3] << 8) |
829 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
831 if (result != MCDisassembler::Fail) {
833 bool InITBlock = ITBlock.instrInITBlock();
834 Check(result, AddThumbPredicate(MI));
835 AddThumb1SBit(MI, InITBlock);
840 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
842 if (result != MCDisassembler::Fail) {
844 Check(result, AddThumbPredicate(MI));
849 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
850 if (result != MCDisassembler::Fail) {
852 UpdateThumbVFPPredicate(MI);
857 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
859 if (result != MCDisassembler::Fail) {
861 Check(result, AddThumbPredicate(MI));
865 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
867 uint32_t NEONLdStInsn = insn32;
868 NEONLdStInsn &= 0xF0FFFFFF;
869 NEONLdStInsn |= 0x04000000;
870 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
872 if (result != MCDisassembler::Fail) {
874 Check(result, AddThumbPredicate(MI));
879 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
881 uint32_t NEONDataInsn = insn32;
882 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
883 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
884 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
885 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
887 if (result != MCDisassembler::Fail) {
889 Check(result, AddThumbPredicate(MI));
895 return MCDisassembler::Fail;
899 extern "C" void LLVMInitializeARMDisassembler() {
900 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
901 createARMDisassembler);
902 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
903 createThumbDisassembler);
906 static const uint16_t GPRDecoderTable[] = {
907 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
908 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
909 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
910 ARM::R12, ARM::SP, ARM::LR, ARM::PC
913 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
914 uint64_t Address, const void *Decoder) {
916 return MCDisassembler::Fail;
918 unsigned Register = GPRDecoderTable[RegNo];
919 Inst.addOperand(MCOperand::CreateReg(Register));
920 return MCDisassembler::Success;
924 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
925 uint64_t Address, const void *Decoder) {
926 DecodeStatus S = MCDisassembler::Success;
929 S = MCDisassembler::SoftFail;
931 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
936 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
937 uint64_t Address, const void *Decoder) {
939 return MCDisassembler::Fail;
940 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
943 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
944 uint64_t Address, const void *Decoder) {
945 unsigned Register = 0;
966 return MCDisassembler::Fail;
969 Inst.addOperand(MCOperand::CreateReg(Register));
970 return MCDisassembler::Success;
973 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
974 uint64_t Address, const void *Decoder) {
975 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
976 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
979 static const uint16_t SPRDecoderTable[] = {
980 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
981 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
982 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
983 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
984 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
985 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
986 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
987 ARM::S28, ARM::S29, ARM::S30, ARM::S31
990 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
991 uint64_t Address, const void *Decoder) {
993 return MCDisassembler::Fail;
995 unsigned Register = SPRDecoderTable[RegNo];
996 Inst.addOperand(MCOperand::CreateReg(Register));
997 return MCDisassembler::Success;
1000 static const uint16_t DPRDecoderTable[] = {
1001 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1002 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1003 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1004 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1005 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1006 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1007 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1008 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1011 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1012 uint64_t Address, const void *Decoder) {
1014 return MCDisassembler::Fail;
1016 unsigned Register = DPRDecoderTable[RegNo];
1017 Inst.addOperand(MCOperand::CreateReg(Register));
1018 return MCDisassembler::Success;
1021 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1022 uint64_t Address, const void *Decoder) {
1024 return MCDisassembler::Fail;
1025 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1029 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1030 uint64_t Address, const void *Decoder) {
1032 return MCDisassembler::Fail;
1033 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1036 static const uint16_t QPRDecoderTable[] = {
1037 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1038 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1039 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1040 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1044 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1045 uint64_t Address, const void *Decoder) {
1047 return MCDisassembler::Fail;
1050 unsigned Register = QPRDecoderTable[RegNo];
1051 Inst.addOperand(MCOperand::CreateReg(Register));
1052 return MCDisassembler::Success;
1055 static const uint16_t DPairDecoderTable[] = {
1056 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1057 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1058 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1059 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1060 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1064 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1065 uint64_t Address, const void *Decoder) {
1067 return MCDisassembler::Fail;
1069 unsigned Register = DPairDecoderTable[RegNo];
1070 Inst.addOperand(MCOperand::CreateReg(Register));
1071 return MCDisassembler::Success;
1074 static const uint16_t DPairSpacedDecoderTable[] = {
1075 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1076 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1077 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1078 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1079 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1080 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1081 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1082 ARM::D28_D30, ARM::D29_D31
1085 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1088 const void *Decoder) {
1090 return MCDisassembler::Fail;
1092 unsigned Register = DPairSpacedDecoderTable[RegNo];
1093 Inst.addOperand(MCOperand::CreateReg(Register));
1094 return MCDisassembler::Success;
1097 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1098 uint64_t Address, const void *Decoder) {
1099 if (Val == 0xF) return MCDisassembler::Fail;
1100 // AL predicate is not allowed on Thumb1 branches.
1101 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1102 return MCDisassembler::Fail;
1103 Inst.addOperand(MCOperand::CreateImm(Val));
1104 if (Val == ARMCC::AL) {
1105 Inst.addOperand(MCOperand::CreateReg(0));
1107 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1108 return MCDisassembler::Success;
1111 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1112 uint64_t Address, const void *Decoder) {
1114 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1116 Inst.addOperand(MCOperand::CreateReg(0));
1117 return MCDisassembler::Success;
1120 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1121 uint64_t Address, const void *Decoder) {
1122 uint32_t imm = Val & 0xFF;
1123 uint32_t rot = (Val & 0xF00) >> 7;
1124 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1125 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1126 return MCDisassembler::Success;
1129 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1130 uint64_t Address, const void *Decoder) {
1131 DecodeStatus S = MCDisassembler::Success;
1133 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1134 unsigned type = fieldFromInstruction(Val, 5, 2);
1135 unsigned imm = fieldFromInstruction(Val, 7, 5);
1137 // Register-immediate
1138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1139 return MCDisassembler::Fail;
1141 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1144 Shift = ARM_AM::lsl;
1147 Shift = ARM_AM::lsr;
1150 Shift = ARM_AM::asr;
1153 Shift = ARM_AM::ror;
1157 if (Shift == ARM_AM::ror && imm == 0)
1158 Shift = ARM_AM::rrx;
1160 unsigned Op = Shift | (imm << 3);
1161 Inst.addOperand(MCOperand::CreateImm(Op));
1166 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1167 uint64_t Address, const void *Decoder) {
1168 DecodeStatus S = MCDisassembler::Success;
1170 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1171 unsigned type = fieldFromInstruction(Val, 5, 2);
1172 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1174 // Register-register
1175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1176 return MCDisassembler::Fail;
1177 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1178 return MCDisassembler::Fail;
1180 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1183 Shift = ARM_AM::lsl;
1186 Shift = ARM_AM::lsr;
1189 Shift = ARM_AM::asr;
1192 Shift = ARM_AM::ror;
1196 Inst.addOperand(MCOperand::CreateImm(Shift));
1201 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1202 uint64_t Address, const void *Decoder) {
1203 DecodeStatus S = MCDisassembler::Success;
1205 bool writebackLoad = false;
1206 unsigned writebackReg = 0;
1207 switch (Inst.getOpcode()) {
1210 case ARM::LDMIA_UPD:
1211 case ARM::LDMDB_UPD:
1212 case ARM::LDMIB_UPD:
1213 case ARM::LDMDA_UPD:
1214 case ARM::t2LDMIA_UPD:
1215 case ARM::t2LDMDB_UPD:
1216 writebackLoad = true;
1217 writebackReg = Inst.getOperand(0).getReg();
1221 // Empty register lists are not allowed.
1222 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1223 for (unsigned i = 0; i < 16; ++i) {
1224 if (Val & (1 << i)) {
1225 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1226 return MCDisassembler::Fail;
1227 // Writeback not allowed if Rn is in the target list.
1228 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1229 Check(S, MCDisassembler::SoftFail);
1236 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1237 uint64_t Address, const void *Decoder) {
1238 DecodeStatus S = MCDisassembler::Success;
1240 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1241 unsigned regs = fieldFromInstruction(Val, 0, 8);
1243 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1244 return MCDisassembler::Fail;
1245 for (unsigned i = 0; i < (regs - 1); ++i) {
1246 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1247 return MCDisassembler::Fail;
1253 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1254 uint64_t Address, const void *Decoder) {
1255 DecodeStatus S = MCDisassembler::Success;
1257 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1258 unsigned regs = fieldFromInstruction(Val, 0, 8);
1262 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1263 return MCDisassembler::Fail;
1264 for (unsigned i = 0; i < (regs - 1); ++i) {
1265 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1266 return MCDisassembler::Fail;
1272 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1273 uint64_t Address, const void *Decoder) {
1274 // This operand encodes a mask of contiguous zeros between a specified MSB
1275 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1276 // the mask of all bits LSB-and-lower, and then xor them to create
1277 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1278 // create the final mask.
1279 unsigned msb = fieldFromInstruction(Val, 5, 5);
1280 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1282 DecodeStatus S = MCDisassembler::Success;
1283 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1285 uint32_t msb_mask = 0xFFFFFFFF;
1286 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1287 uint32_t lsb_mask = (1U << lsb) - 1;
1289 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1293 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1294 uint64_t Address, const void *Decoder) {
1295 DecodeStatus S = MCDisassembler::Success;
1297 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1298 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1299 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1300 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1301 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1302 unsigned U = fieldFromInstruction(Insn, 23, 1);
1304 switch (Inst.getOpcode()) {
1305 case ARM::LDC_OFFSET:
1308 case ARM::LDC_OPTION:
1309 case ARM::LDCL_OFFSET:
1311 case ARM::LDCL_POST:
1312 case ARM::LDCL_OPTION:
1313 case ARM::STC_OFFSET:
1316 case ARM::STC_OPTION:
1317 case ARM::STCL_OFFSET:
1319 case ARM::STCL_POST:
1320 case ARM::STCL_OPTION:
1321 case ARM::t2LDC_OFFSET:
1322 case ARM::t2LDC_PRE:
1323 case ARM::t2LDC_POST:
1324 case ARM::t2LDC_OPTION:
1325 case ARM::t2LDCL_OFFSET:
1326 case ARM::t2LDCL_PRE:
1327 case ARM::t2LDCL_POST:
1328 case ARM::t2LDCL_OPTION:
1329 case ARM::t2STC_OFFSET:
1330 case ARM::t2STC_PRE:
1331 case ARM::t2STC_POST:
1332 case ARM::t2STC_OPTION:
1333 case ARM::t2STCL_OFFSET:
1334 case ARM::t2STCL_PRE:
1335 case ARM::t2STCL_POST:
1336 case ARM::t2STCL_OPTION:
1337 if (coproc == 0xA || coproc == 0xB)
1338 return MCDisassembler::Fail;
1344 Inst.addOperand(MCOperand::CreateImm(coproc));
1345 Inst.addOperand(MCOperand::CreateImm(CRd));
1346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1347 return MCDisassembler::Fail;
1349 switch (Inst.getOpcode()) {
1350 case ARM::t2LDC2_OFFSET:
1351 case ARM::t2LDC2L_OFFSET:
1352 case ARM::t2LDC2_PRE:
1353 case ARM::t2LDC2L_PRE:
1354 case ARM::t2STC2_OFFSET:
1355 case ARM::t2STC2L_OFFSET:
1356 case ARM::t2STC2_PRE:
1357 case ARM::t2STC2L_PRE:
1358 case ARM::LDC2_OFFSET:
1359 case ARM::LDC2L_OFFSET:
1361 case ARM::LDC2L_PRE:
1362 case ARM::STC2_OFFSET:
1363 case ARM::STC2L_OFFSET:
1365 case ARM::STC2L_PRE:
1366 case ARM::t2LDC_OFFSET:
1367 case ARM::t2LDCL_OFFSET:
1368 case ARM::t2LDC_PRE:
1369 case ARM::t2LDCL_PRE:
1370 case ARM::t2STC_OFFSET:
1371 case ARM::t2STCL_OFFSET:
1372 case ARM::t2STC_PRE:
1373 case ARM::t2STCL_PRE:
1374 case ARM::LDC_OFFSET:
1375 case ARM::LDCL_OFFSET:
1378 case ARM::STC_OFFSET:
1379 case ARM::STCL_OFFSET:
1382 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1383 Inst.addOperand(MCOperand::CreateImm(imm));
1385 case ARM::t2LDC2_POST:
1386 case ARM::t2LDC2L_POST:
1387 case ARM::t2STC2_POST:
1388 case ARM::t2STC2L_POST:
1389 case ARM::LDC2_POST:
1390 case ARM::LDC2L_POST:
1391 case ARM::STC2_POST:
1392 case ARM::STC2L_POST:
1393 case ARM::t2LDC_POST:
1394 case ARM::t2LDCL_POST:
1395 case ARM::t2STC_POST:
1396 case ARM::t2STCL_POST:
1398 case ARM::LDCL_POST:
1400 case ARM::STCL_POST:
1404 // The 'option' variant doesn't encode 'U' in the immediate since
1405 // the immediate is unsigned [0,255].
1406 Inst.addOperand(MCOperand::CreateImm(imm));
1410 switch (Inst.getOpcode()) {
1411 case ARM::LDC_OFFSET:
1414 case ARM::LDC_OPTION:
1415 case ARM::LDCL_OFFSET:
1417 case ARM::LDCL_POST:
1418 case ARM::LDCL_OPTION:
1419 case ARM::STC_OFFSET:
1422 case ARM::STC_OPTION:
1423 case ARM::STCL_OFFSET:
1425 case ARM::STCL_POST:
1426 case ARM::STCL_OPTION:
1427 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1428 return MCDisassembler::Fail;
1438 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1439 uint64_t Address, const void *Decoder) {
1440 DecodeStatus S = MCDisassembler::Success;
1442 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1443 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1444 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1445 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1446 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1447 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1448 unsigned P = fieldFromInstruction(Insn, 24, 1);
1449 unsigned W = fieldFromInstruction(Insn, 21, 1);
1451 // On stores, the writeback operand precedes Rt.
1452 switch (Inst.getOpcode()) {
1453 case ARM::STR_POST_IMM:
1454 case ARM::STR_POST_REG:
1455 case ARM::STRB_POST_IMM:
1456 case ARM::STRB_POST_REG:
1457 case ARM::STRT_POST_REG:
1458 case ARM::STRT_POST_IMM:
1459 case ARM::STRBT_POST_REG:
1460 case ARM::STRBT_POST_IMM:
1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1462 return MCDisassembler::Fail;
1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1469 return MCDisassembler::Fail;
1471 // On loads, the writeback operand comes after Rt.
1472 switch (Inst.getOpcode()) {
1473 case ARM::LDR_POST_IMM:
1474 case ARM::LDR_POST_REG:
1475 case ARM::LDRB_POST_IMM:
1476 case ARM::LDRB_POST_REG:
1477 case ARM::LDRBT_POST_REG:
1478 case ARM::LDRBT_POST_IMM:
1479 case ARM::LDRT_POST_REG:
1480 case ARM::LDRT_POST_IMM:
1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1482 return MCDisassembler::Fail;
1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1489 return MCDisassembler::Fail;
1491 ARM_AM::AddrOpc Op = ARM_AM::add;
1492 if (!fieldFromInstruction(Insn, 23, 1))
1495 bool writeback = (P == 0) || (W == 1);
1496 unsigned idx_mode = 0;
1498 idx_mode = ARMII::IndexModePre;
1499 else if (!P && writeback)
1500 idx_mode = ARMII::IndexModePost;
1502 if (writeback && (Rn == 15 || Rn == Rt))
1503 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1506 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1507 return MCDisassembler::Fail;
1508 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1509 switch( fieldFromInstruction(Insn, 5, 2)) {
1523 return MCDisassembler::Fail;
1525 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1526 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1528 Inst.addOperand(MCOperand::CreateImm(imm));
1530 Inst.addOperand(MCOperand::CreateReg(0));
1531 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1532 Inst.addOperand(MCOperand::CreateImm(tmp));
1535 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1536 return MCDisassembler::Fail;
1541 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1542 uint64_t Address, const void *Decoder) {
1543 DecodeStatus S = MCDisassembler::Success;
1545 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1546 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1547 unsigned type = fieldFromInstruction(Val, 5, 2);
1548 unsigned imm = fieldFromInstruction(Val, 7, 5);
1549 unsigned U = fieldFromInstruction(Val, 12, 1);
1551 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1568 return MCDisassembler::Fail;
1569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1570 return MCDisassembler::Fail;
1573 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1575 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1576 Inst.addOperand(MCOperand::CreateImm(shift));
1582 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1583 uint64_t Address, const void *Decoder) {
1584 DecodeStatus S = MCDisassembler::Success;
1586 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1587 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1588 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1589 unsigned type = fieldFromInstruction(Insn, 22, 1);
1590 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1591 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1592 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1593 unsigned W = fieldFromInstruction(Insn, 21, 1);
1594 unsigned P = fieldFromInstruction(Insn, 24, 1);
1595 unsigned Rt2 = Rt + 1;
1597 bool writeback = (W == 1) | (P == 0);
1599 // For {LD,ST}RD, Rt must be even, else undefined.
1600 switch (Inst.getOpcode()) {
1603 case ARM::STRD_POST:
1606 case ARM::LDRD_POST:
1607 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1612 switch (Inst.getOpcode()) {
1615 case ARM::STRD_POST:
1616 if (P == 0 && W == 1)
1617 S = MCDisassembler::SoftFail;
1619 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1620 S = MCDisassembler::SoftFail;
1621 if (type && Rm == 15)
1622 S = MCDisassembler::SoftFail;
1624 S = MCDisassembler::SoftFail;
1625 if (!type && fieldFromInstruction(Insn, 8, 4))
1626 S = MCDisassembler::SoftFail;
1630 case ARM::STRH_POST:
1632 S = MCDisassembler::SoftFail;
1633 if (writeback && (Rn == 15 || Rn == Rt))
1634 S = MCDisassembler::SoftFail;
1635 if (!type && Rm == 15)
1636 S = MCDisassembler::SoftFail;
1640 case ARM::LDRD_POST:
1641 if (type && Rn == 15){
1643 S = MCDisassembler::SoftFail;
1646 if (P == 0 && W == 1)
1647 S = MCDisassembler::SoftFail;
1648 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1649 S = MCDisassembler::SoftFail;
1650 if (!type && writeback && Rn == 15)
1651 S = MCDisassembler::SoftFail;
1652 if (writeback && (Rn == Rt || Rn == Rt2))
1653 S = MCDisassembler::SoftFail;
1657 case ARM::LDRH_POST:
1658 if (type && Rn == 15){
1660 S = MCDisassembler::SoftFail;
1664 S = MCDisassembler::SoftFail;
1665 if (!type && Rm == 15)
1666 S = MCDisassembler::SoftFail;
1667 if (!type && writeback && (Rn == 15 || Rn == Rt))
1668 S = MCDisassembler::SoftFail;
1671 case ARM::LDRSH_PRE:
1672 case ARM::LDRSH_POST:
1674 case ARM::LDRSB_PRE:
1675 case ARM::LDRSB_POST:
1676 if (type && Rn == 15){
1678 S = MCDisassembler::SoftFail;
1681 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1682 S = MCDisassembler::SoftFail;
1683 if (!type && (Rt == 15 || Rm == 15))
1684 S = MCDisassembler::SoftFail;
1685 if (!type && writeback && (Rn == 15 || Rn == Rt))
1686 S = MCDisassembler::SoftFail;
1692 if (writeback) { // Writeback
1694 U |= ARMII::IndexModePre << 9;
1696 U |= ARMII::IndexModePost << 9;
1698 // On stores, the writeback operand precedes Rt.
1699 switch (Inst.getOpcode()) {
1702 case ARM::STRD_POST:
1705 case ARM::STRH_POST:
1706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1707 return MCDisassembler::Fail;
1714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1715 return MCDisassembler::Fail;
1716 switch (Inst.getOpcode()) {
1719 case ARM::STRD_POST:
1722 case ARM::LDRD_POST:
1723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1724 return MCDisassembler::Fail;
1731 // On loads, the writeback operand comes after Rt.
1732 switch (Inst.getOpcode()) {
1735 case ARM::LDRD_POST:
1738 case ARM::LDRH_POST:
1740 case ARM::LDRSH_PRE:
1741 case ARM::LDRSH_POST:
1743 case ARM::LDRSB_PRE:
1744 case ARM::LDRSB_POST:
1747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1748 return MCDisassembler::Fail;
1755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1756 return MCDisassembler::Fail;
1759 Inst.addOperand(MCOperand::CreateReg(0));
1760 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1763 return MCDisassembler::Fail;
1764 Inst.addOperand(MCOperand::CreateImm(U));
1767 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1768 return MCDisassembler::Fail;
1773 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1774 uint64_t Address, const void *Decoder) {
1775 DecodeStatus S = MCDisassembler::Success;
1777 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1778 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1795 Inst.addOperand(MCOperand::CreateImm(mode));
1796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1797 return MCDisassembler::Fail;
1802 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1804 uint64_t Address, const void *Decoder) {
1805 DecodeStatus S = MCDisassembler::Success;
1807 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1808 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1809 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1812 switch (Inst.getOpcode()) {
1814 Inst.setOpcode(ARM::RFEDA);
1816 case ARM::LDMDA_UPD:
1817 Inst.setOpcode(ARM::RFEDA_UPD);
1820 Inst.setOpcode(ARM::RFEDB);
1822 case ARM::LDMDB_UPD:
1823 Inst.setOpcode(ARM::RFEDB_UPD);
1826 Inst.setOpcode(ARM::RFEIA);
1828 case ARM::LDMIA_UPD:
1829 Inst.setOpcode(ARM::RFEIA_UPD);
1832 Inst.setOpcode(ARM::RFEIB);
1834 case ARM::LDMIB_UPD:
1835 Inst.setOpcode(ARM::RFEIB_UPD);
1838 Inst.setOpcode(ARM::SRSDA);
1840 case ARM::STMDA_UPD:
1841 Inst.setOpcode(ARM::SRSDA_UPD);
1844 Inst.setOpcode(ARM::SRSDB);
1846 case ARM::STMDB_UPD:
1847 Inst.setOpcode(ARM::SRSDB_UPD);
1850 Inst.setOpcode(ARM::SRSIA);
1852 case ARM::STMIA_UPD:
1853 Inst.setOpcode(ARM::SRSIA_UPD);
1856 Inst.setOpcode(ARM::SRSIB);
1858 case ARM::STMIB_UPD:
1859 Inst.setOpcode(ARM::SRSIB_UPD);
1862 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1865 // For stores (which become SRS's, the only operand is the mode.
1866 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1868 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1872 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1876 return MCDisassembler::Fail;
1877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1878 return MCDisassembler::Fail; // Tied
1879 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1880 return MCDisassembler::Fail;
1881 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1882 return MCDisassembler::Fail;
1887 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1888 uint64_t Address, const void *Decoder) {
1889 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1890 unsigned M = fieldFromInstruction(Insn, 17, 1);
1891 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1892 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1894 DecodeStatus S = MCDisassembler::Success;
1896 // imod == '01' --> UNPREDICTABLE
1897 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1898 // return failure here. The '01' imod value is unprintable, so there's
1899 // nothing useful we could do even if we returned UNPREDICTABLE.
1901 if (imod == 1) return MCDisassembler::Fail;
1904 Inst.setOpcode(ARM::CPS3p);
1905 Inst.addOperand(MCOperand::CreateImm(imod));
1906 Inst.addOperand(MCOperand::CreateImm(iflags));
1907 Inst.addOperand(MCOperand::CreateImm(mode));
1908 } else if (imod && !M) {
1909 Inst.setOpcode(ARM::CPS2p);
1910 Inst.addOperand(MCOperand::CreateImm(imod));
1911 Inst.addOperand(MCOperand::CreateImm(iflags));
1912 if (mode) S = MCDisassembler::SoftFail;
1913 } else if (!imod && M) {
1914 Inst.setOpcode(ARM::CPS1p);
1915 Inst.addOperand(MCOperand::CreateImm(mode));
1916 if (iflags) S = MCDisassembler::SoftFail;
1918 // imod == '00' && M == '0' --> UNPREDICTABLE
1919 Inst.setOpcode(ARM::CPS1p);
1920 Inst.addOperand(MCOperand::CreateImm(mode));
1921 S = MCDisassembler::SoftFail;
1927 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1928 uint64_t Address, const void *Decoder) {
1929 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1930 unsigned M = fieldFromInstruction(Insn, 8, 1);
1931 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1932 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1934 DecodeStatus S = MCDisassembler::Success;
1936 // imod == '01' --> UNPREDICTABLE
1937 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1938 // return failure here. The '01' imod value is unprintable, so there's
1939 // nothing useful we could do even if we returned UNPREDICTABLE.
1941 if (imod == 1) return MCDisassembler::Fail;
1944 Inst.setOpcode(ARM::t2CPS3p);
1945 Inst.addOperand(MCOperand::CreateImm(imod));
1946 Inst.addOperand(MCOperand::CreateImm(iflags));
1947 Inst.addOperand(MCOperand::CreateImm(mode));
1948 } else if (imod && !M) {
1949 Inst.setOpcode(ARM::t2CPS2p);
1950 Inst.addOperand(MCOperand::CreateImm(imod));
1951 Inst.addOperand(MCOperand::CreateImm(iflags));
1952 if (mode) S = MCDisassembler::SoftFail;
1953 } else if (!imod && M) {
1954 Inst.setOpcode(ARM::t2CPS1p);
1955 Inst.addOperand(MCOperand::CreateImm(mode));
1956 if (iflags) S = MCDisassembler::SoftFail;
1958 // imod == '00' && M == '0' --> UNPREDICTABLE
1959 Inst.setOpcode(ARM::t2CPS1p);
1960 Inst.addOperand(MCOperand::CreateImm(mode));
1961 S = MCDisassembler::SoftFail;
1967 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1968 uint64_t Address, const void *Decoder) {
1969 DecodeStatus S = MCDisassembler::Success;
1971 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
1974 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1975 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1976 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1977 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
1979 if (Inst.getOpcode() == ARM::t2MOVTi16)
1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1981 return MCDisassembler::Fail;
1982 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1983 return MCDisassembler::Fail;
1985 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1986 Inst.addOperand(MCOperand::CreateImm(imm));
1991 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
1992 uint64_t Address, const void *Decoder) {
1993 DecodeStatus S = MCDisassembler::Success;
1995 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1996 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1999 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2000 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2002 if (Inst.getOpcode() == ARM::MOVTi16)
2003 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2004 return MCDisassembler::Fail;
2005 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2006 return MCDisassembler::Fail;
2008 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2009 Inst.addOperand(MCOperand::CreateImm(imm));
2011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2012 return MCDisassembler::Fail;
2017 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2018 uint64_t Address, const void *Decoder) {
2019 DecodeStatus S = MCDisassembler::Success;
2021 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2022 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2023 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2024 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2025 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2028 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2030 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2031 return MCDisassembler::Fail;
2032 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2033 return MCDisassembler::Fail;
2034 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2035 return MCDisassembler::Fail;
2036 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2037 return MCDisassembler::Fail;
2039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2040 return MCDisassembler::Fail;
2045 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2046 uint64_t Address, const void *Decoder) {
2047 DecodeStatus S = MCDisassembler::Success;
2049 unsigned add = fieldFromInstruction(Val, 12, 1);
2050 unsigned imm = fieldFromInstruction(Val, 0, 12);
2051 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2054 return MCDisassembler::Fail;
2056 if (!add) imm *= -1;
2057 if (imm == 0 && !add) imm = INT32_MIN;
2058 Inst.addOperand(MCOperand::CreateImm(imm));
2060 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2065 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2066 uint64_t Address, const void *Decoder) {
2067 DecodeStatus S = MCDisassembler::Success;
2069 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2070 unsigned U = fieldFromInstruction(Val, 8, 1);
2071 unsigned imm = fieldFromInstruction(Val, 0, 8);
2073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2074 return MCDisassembler::Fail;
2077 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2079 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2084 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2085 uint64_t Address, const void *Decoder) {
2086 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2090 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2091 uint64_t Address, const void *Decoder) {
2092 DecodeStatus S = MCDisassembler::Success;
2093 unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) |
2094 (fieldFromInstruction(Insn, 11, 1) << 18) |
2095 (fieldFromInstruction(Insn, 13, 1) << 17) |
2096 (fieldFromInstruction(Insn, 16, 6) << 11) |
2097 (fieldFromInstruction(Insn, 26, 1) << 19);
2098 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2099 true, 4, Inst, Decoder))
2100 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2105 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2106 uint64_t Address, const void *Decoder) {
2107 DecodeStatus S = MCDisassembler::Success;
2109 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2110 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2113 Inst.setOpcode(ARM::BLXi);
2114 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2115 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2116 true, 4, Inst, Decoder))
2117 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2121 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2122 true, 4, Inst, Decoder))
2123 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2124 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2125 return MCDisassembler::Fail;
2131 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2132 uint64_t Address, const void *Decoder) {
2133 DecodeStatus S = MCDisassembler::Success;
2135 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2136 unsigned align = fieldFromInstruction(Val, 4, 2);
2138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2139 return MCDisassembler::Fail;
2141 Inst.addOperand(MCOperand::CreateImm(0));
2143 Inst.addOperand(MCOperand::CreateImm(4 << align));
2148 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2149 uint64_t Address, const void *Decoder) {
2150 DecodeStatus S = MCDisassembler::Success;
2152 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2153 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2154 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2155 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2156 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2157 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2159 // First output register
2160 switch (Inst.getOpcode()) {
2161 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2162 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2163 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2164 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2165 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2166 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2167 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2168 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2169 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2170 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2171 return MCDisassembler::Fail;
2176 case ARM::VLD2b16wb_fixed:
2177 case ARM::VLD2b16wb_register:
2178 case ARM::VLD2b32wb_fixed:
2179 case ARM::VLD2b32wb_register:
2180 case ARM::VLD2b8wb_fixed:
2181 case ARM::VLD2b8wb_register:
2182 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2183 return MCDisassembler::Fail;
2186 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2187 return MCDisassembler::Fail;
2190 // Second output register
2191 switch (Inst.getOpcode()) {
2195 case ARM::VLD3d8_UPD:
2196 case ARM::VLD3d16_UPD:
2197 case ARM::VLD3d32_UPD:
2201 case ARM::VLD4d8_UPD:
2202 case ARM::VLD4d16_UPD:
2203 case ARM::VLD4d32_UPD:
2204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2205 return MCDisassembler::Fail;
2210 case ARM::VLD3q8_UPD:
2211 case ARM::VLD3q16_UPD:
2212 case ARM::VLD3q32_UPD:
2216 case ARM::VLD4q8_UPD:
2217 case ARM::VLD4q16_UPD:
2218 case ARM::VLD4q32_UPD:
2219 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2220 return MCDisassembler::Fail;
2225 // Third output register
2226 switch(Inst.getOpcode()) {
2230 case ARM::VLD3d8_UPD:
2231 case ARM::VLD3d16_UPD:
2232 case ARM::VLD3d32_UPD:
2236 case ARM::VLD4d8_UPD:
2237 case ARM::VLD4d16_UPD:
2238 case ARM::VLD4d32_UPD:
2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2240 return MCDisassembler::Fail;
2245 case ARM::VLD3q8_UPD:
2246 case ARM::VLD3q16_UPD:
2247 case ARM::VLD3q32_UPD:
2251 case ARM::VLD4q8_UPD:
2252 case ARM::VLD4q16_UPD:
2253 case ARM::VLD4q32_UPD:
2254 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2255 return MCDisassembler::Fail;
2261 // Fourth output register
2262 switch (Inst.getOpcode()) {
2266 case ARM::VLD4d8_UPD:
2267 case ARM::VLD4d16_UPD:
2268 case ARM::VLD4d32_UPD:
2269 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2270 return MCDisassembler::Fail;
2275 case ARM::VLD4q8_UPD:
2276 case ARM::VLD4q16_UPD:
2277 case ARM::VLD4q32_UPD:
2278 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2279 return MCDisassembler::Fail;
2285 // Writeback operand
2286 switch (Inst.getOpcode()) {
2287 case ARM::VLD1d8wb_fixed:
2288 case ARM::VLD1d16wb_fixed:
2289 case ARM::VLD1d32wb_fixed:
2290 case ARM::VLD1d64wb_fixed:
2291 case ARM::VLD1d8wb_register:
2292 case ARM::VLD1d16wb_register:
2293 case ARM::VLD1d32wb_register:
2294 case ARM::VLD1d64wb_register:
2295 case ARM::VLD1q8wb_fixed:
2296 case ARM::VLD1q16wb_fixed:
2297 case ARM::VLD1q32wb_fixed:
2298 case ARM::VLD1q64wb_fixed:
2299 case ARM::VLD1q8wb_register:
2300 case ARM::VLD1q16wb_register:
2301 case ARM::VLD1q32wb_register:
2302 case ARM::VLD1q64wb_register:
2303 case ARM::VLD1d8Twb_fixed:
2304 case ARM::VLD1d8Twb_register:
2305 case ARM::VLD1d16Twb_fixed:
2306 case ARM::VLD1d16Twb_register:
2307 case ARM::VLD1d32Twb_fixed:
2308 case ARM::VLD1d32Twb_register:
2309 case ARM::VLD1d64Twb_fixed:
2310 case ARM::VLD1d64Twb_register:
2311 case ARM::VLD1d8Qwb_fixed:
2312 case ARM::VLD1d8Qwb_register:
2313 case ARM::VLD1d16Qwb_fixed:
2314 case ARM::VLD1d16Qwb_register:
2315 case ARM::VLD1d32Qwb_fixed:
2316 case ARM::VLD1d32Qwb_register:
2317 case ARM::VLD1d64Qwb_fixed:
2318 case ARM::VLD1d64Qwb_register:
2319 case ARM::VLD2d8wb_fixed:
2320 case ARM::VLD2d16wb_fixed:
2321 case ARM::VLD2d32wb_fixed:
2322 case ARM::VLD2q8wb_fixed:
2323 case ARM::VLD2q16wb_fixed:
2324 case ARM::VLD2q32wb_fixed:
2325 case ARM::VLD2d8wb_register:
2326 case ARM::VLD2d16wb_register:
2327 case ARM::VLD2d32wb_register:
2328 case ARM::VLD2q8wb_register:
2329 case ARM::VLD2q16wb_register:
2330 case ARM::VLD2q32wb_register:
2331 case ARM::VLD2b8wb_fixed:
2332 case ARM::VLD2b16wb_fixed:
2333 case ARM::VLD2b32wb_fixed:
2334 case ARM::VLD2b8wb_register:
2335 case ARM::VLD2b16wb_register:
2336 case ARM::VLD2b32wb_register:
2337 Inst.addOperand(MCOperand::CreateImm(0));
2339 case ARM::VLD3d8_UPD:
2340 case ARM::VLD3d16_UPD:
2341 case ARM::VLD3d32_UPD:
2342 case ARM::VLD3q8_UPD:
2343 case ARM::VLD3q16_UPD:
2344 case ARM::VLD3q32_UPD:
2345 case ARM::VLD4d8_UPD:
2346 case ARM::VLD4d16_UPD:
2347 case ARM::VLD4d32_UPD:
2348 case ARM::VLD4q8_UPD:
2349 case ARM::VLD4q16_UPD:
2350 case ARM::VLD4q32_UPD:
2351 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2352 return MCDisassembler::Fail;
2358 // AddrMode6 Base (register+alignment)
2359 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2360 return MCDisassembler::Fail;
2362 // AddrMode6 Offset (register)
2363 switch (Inst.getOpcode()) {
2365 // The below have been updated to have explicit am6offset split
2366 // between fixed and register offset. For those instructions not
2367 // yet updated, we need to add an additional reg0 operand for the
2370 // The fixed offset encodes as Rm == 0xd, so we check for that.
2372 Inst.addOperand(MCOperand::CreateReg(0));
2375 // Fall through to handle the register offset variant.
2376 case ARM::VLD1d8wb_fixed:
2377 case ARM::VLD1d16wb_fixed:
2378 case ARM::VLD1d32wb_fixed:
2379 case ARM::VLD1d64wb_fixed:
2380 case ARM::VLD1d8Twb_fixed:
2381 case ARM::VLD1d16Twb_fixed:
2382 case ARM::VLD1d32Twb_fixed:
2383 case ARM::VLD1d64Twb_fixed:
2384 case ARM::VLD1d8Qwb_fixed:
2385 case ARM::VLD1d16Qwb_fixed:
2386 case ARM::VLD1d32Qwb_fixed:
2387 case ARM::VLD1d64Qwb_fixed:
2388 case ARM::VLD1d8wb_register:
2389 case ARM::VLD1d16wb_register:
2390 case ARM::VLD1d32wb_register:
2391 case ARM::VLD1d64wb_register:
2392 case ARM::VLD1q8wb_fixed:
2393 case ARM::VLD1q16wb_fixed:
2394 case ARM::VLD1q32wb_fixed:
2395 case ARM::VLD1q64wb_fixed:
2396 case ARM::VLD1q8wb_register:
2397 case ARM::VLD1q16wb_register:
2398 case ARM::VLD1q32wb_register:
2399 case ARM::VLD1q64wb_register:
2400 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2401 // variant encodes Rm == 0xf. Anything else is a register offset post-
2402 // increment and we need to add the register operand to the instruction.
2403 if (Rm != 0xD && Rm != 0xF &&
2404 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2405 return MCDisassembler::Fail;
2407 case ARM::VLD2d8wb_fixed:
2408 case ARM::VLD2d16wb_fixed:
2409 case ARM::VLD2d32wb_fixed:
2410 case ARM::VLD2b8wb_fixed:
2411 case ARM::VLD2b16wb_fixed:
2412 case ARM::VLD2b32wb_fixed:
2413 case ARM::VLD2q8wb_fixed:
2414 case ARM::VLD2q16wb_fixed:
2415 case ARM::VLD2q32wb_fixed:
2422 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2423 uint64_t Address, const void *Decoder) {
2424 DecodeStatus S = MCDisassembler::Success;
2426 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2427 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2428 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2429 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2430 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2431 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2433 // Writeback Operand
2434 switch (Inst.getOpcode()) {
2435 case ARM::VST1d8wb_fixed:
2436 case ARM::VST1d16wb_fixed:
2437 case ARM::VST1d32wb_fixed:
2438 case ARM::VST1d64wb_fixed:
2439 case ARM::VST1d8wb_register:
2440 case ARM::VST1d16wb_register:
2441 case ARM::VST1d32wb_register:
2442 case ARM::VST1d64wb_register:
2443 case ARM::VST1q8wb_fixed:
2444 case ARM::VST1q16wb_fixed:
2445 case ARM::VST1q32wb_fixed:
2446 case ARM::VST1q64wb_fixed:
2447 case ARM::VST1q8wb_register:
2448 case ARM::VST1q16wb_register:
2449 case ARM::VST1q32wb_register:
2450 case ARM::VST1q64wb_register:
2451 case ARM::VST1d8Twb_fixed:
2452 case ARM::VST1d16Twb_fixed:
2453 case ARM::VST1d32Twb_fixed:
2454 case ARM::VST1d64Twb_fixed:
2455 case ARM::VST1d8Twb_register:
2456 case ARM::VST1d16Twb_register:
2457 case ARM::VST1d32Twb_register:
2458 case ARM::VST1d64Twb_register:
2459 case ARM::VST1d8Qwb_fixed:
2460 case ARM::VST1d16Qwb_fixed:
2461 case ARM::VST1d32Qwb_fixed:
2462 case ARM::VST1d64Qwb_fixed:
2463 case ARM::VST1d8Qwb_register:
2464 case ARM::VST1d16Qwb_register:
2465 case ARM::VST1d32Qwb_register:
2466 case ARM::VST1d64Qwb_register:
2467 case ARM::VST2d8wb_fixed:
2468 case ARM::VST2d16wb_fixed:
2469 case ARM::VST2d32wb_fixed:
2470 case ARM::VST2d8wb_register:
2471 case ARM::VST2d16wb_register:
2472 case ARM::VST2d32wb_register:
2473 case ARM::VST2q8wb_fixed:
2474 case ARM::VST2q16wb_fixed:
2475 case ARM::VST2q32wb_fixed:
2476 case ARM::VST2q8wb_register:
2477 case ARM::VST2q16wb_register:
2478 case ARM::VST2q32wb_register:
2479 case ARM::VST2b8wb_fixed:
2480 case ARM::VST2b16wb_fixed:
2481 case ARM::VST2b32wb_fixed:
2482 case ARM::VST2b8wb_register:
2483 case ARM::VST2b16wb_register:
2484 case ARM::VST2b32wb_register:
2486 return MCDisassembler::Fail;
2487 Inst.addOperand(MCOperand::CreateImm(0));
2489 case ARM::VST3d8_UPD:
2490 case ARM::VST3d16_UPD:
2491 case ARM::VST3d32_UPD:
2492 case ARM::VST3q8_UPD:
2493 case ARM::VST3q16_UPD:
2494 case ARM::VST3q32_UPD:
2495 case ARM::VST4d8_UPD:
2496 case ARM::VST4d16_UPD:
2497 case ARM::VST4d32_UPD:
2498 case ARM::VST4q8_UPD:
2499 case ARM::VST4q16_UPD:
2500 case ARM::VST4q32_UPD:
2501 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2502 return MCDisassembler::Fail;
2508 // AddrMode6 Base (register+alignment)
2509 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2510 return MCDisassembler::Fail;
2512 // AddrMode6 Offset (register)
2513 switch (Inst.getOpcode()) {
2516 Inst.addOperand(MCOperand::CreateReg(0));
2517 else if (Rm != 0xF) {
2518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2519 return MCDisassembler::Fail;
2522 case ARM::VST1d8wb_fixed:
2523 case ARM::VST1d16wb_fixed:
2524 case ARM::VST1d32wb_fixed:
2525 case ARM::VST1d64wb_fixed:
2526 case ARM::VST1q8wb_fixed:
2527 case ARM::VST1q16wb_fixed:
2528 case ARM::VST1q32wb_fixed:
2529 case ARM::VST1q64wb_fixed:
2530 case ARM::VST1d8Twb_fixed:
2531 case ARM::VST1d16Twb_fixed:
2532 case ARM::VST1d32Twb_fixed:
2533 case ARM::VST1d64Twb_fixed:
2534 case ARM::VST1d8Qwb_fixed:
2535 case ARM::VST1d16Qwb_fixed:
2536 case ARM::VST1d32Qwb_fixed:
2537 case ARM::VST1d64Qwb_fixed:
2538 case ARM::VST2d8wb_fixed:
2539 case ARM::VST2d16wb_fixed:
2540 case ARM::VST2d32wb_fixed:
2541 case ARM::VST2q8wb_fixed:
2542 case ARM::VST2q16wb_fixed:
2543 case ARM::VST2q32wb_fixed:
2544 case ARM::VST2b8wb_fixed:
2545 case ARM::VST2b16wb_fixed:
2546 case ARM::VST2b32wb_fixed:
2551 // First input register
2552 switch (Inst.getOpcode()) {
2557 case ARM::VST1q16wb_fixed:
2558 case ARM::VST1q16wb_register:
2559 case ARM::VST1q32wb_fixed:
2560 case ARM::VST1q32wb_register:
2561 case ARM::VST1q64wb_fixed:
2562 case ARM::VST1q64wb_register:
2563 case ARM::VST1q8wb_fixed:
2564 case ARM::VST1q8wb_register:
2568 case ARM::VST2d16wb_fixed:
2569 case ARM::VST2d16wb_register:
2570 case ARM::VST2d32wb_fixed:
2571 case ARM::VST2d32wb_register:
2572 case ARM::VST2d8wb_fixed:
2573 case ARM::VST2d8wb_register:
2574 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2575 return MCDisassembler::Fail;
2580 case ARM::VST2b16wb_fixed:
2581 case ARM::VST2b16wb_register:
2582 case ARM::VST2b32wb_fixed:
2583 case ARM::VST2b32wb_register:
2584 case ARM::VST2b8wb_fixed:
2585 case ARM::VST2b8wb_register:
2586 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2587 return MCDisassembler::Fail;
2590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2591 return MCDisassembler::Fail;
2594 // Second input register
2595 switch (Inst.getOpcode()) {
2599 case ARM::VST3d8_UPD:
2600 case ARM::VST3d16_UPD:
2601 case ARM::VST3d32_UPD:
2605 case ARM::VST4d8_UPD:
2606 case ARM::VST4d16_UPD:
2607 case ARM::VST4d32_UPD:
2608 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2609 return MCDisassembler::Fail;
2614 case ARM::VST3q8_UPD:
2615 case ARM::VST3q16_UPD:
2616 case ARM::VST3q32_UPD:
2620 case ARM::VST4q8_UPD:
2621 case ARM::VST4q16_UPD:
2622 case ARM::VST4q32_UPD:
2623 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2624 return MCDisassembler::Fail;
2630 // Third input register
2631 switch (Inst.getOpcode()) {
2635 case ARM::VST3d8_UPD:
2636 case ARM::VST3d16_UPD:
2637 case ARM::VST3d32_UPD:
2641 case ARM::VST4d8_UPD:
2642 case ARM::VST4d16_UPD:
2643 case ARM::VST4d32_UPD:
2644 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2645 return MCDisassembler::Fail;
2650 case ARM::VST3q8_UPD:
2651 case ARM::VST3q16_UPD:
2652 case ARM::VST3q32_UPD:
2656 case ARM::VST4q8_UPD:
2657 case ARM::VST4q16_UPD:
2658 case ARM::VST4q32_UPD:
2659 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2660 return MCDisassembler::Fail;
2666 // Fourth input register
2667 switch (Inst.getOpcode()) {
2671 case ARM::VST4d8_UPD:
2672 case ARM::VST4d16_UPD:
2673 case ARM::VST4d32_UPD:
2674 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2675 return MCDisassembler::Fail;
2680 case ARM::VST4q8_UPD:
2681 case ARM::VST4q16_UPD:
2682 case ARM::VST4q32_UPD:
2683 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2684 return MCDisassembler::Fail;
2693 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2694 uint64_t Address, const void *Decoder) {
2695 DecodeStatus S = MCDisassembler::Success;
2697 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2698 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2699 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2700 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2701 unsigned align = fieldFromInstruction(Insn, 4, 1);
2702 unsigned size = fieldFromInstruction(Insn, 6, 2);
2704 if (size == 0 && align == 1)
2705 return MCDisassembler::Fail;
2706 align *= (1 << size);
2708 switch (Inst.getOpcode()) {
2709 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2710 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2711 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2712 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2713 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2714 return MCDisassembler::Fail;
2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2718 return MCDisassembler::Fail;
2722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2723 return MCDisassembler::Fail;
2726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2727 return MCDisassembler::Fail;
2728 Inst.addOperand(MCOperand::CreateImm(align));
2730 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2731 // variant encodes Rm == 0xf. Anything else is a register offset post-
2732 // increment and we need to add the register operand to the instruction.
2733 if (Rm != 0xD && Rm != 0xF &&
2734 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2735 return MCDisassembler::Fail;
2740 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2741 uint64_t Address, const void *Decoder) {
2742 DecodeStatus S = MCDisassembler::Success;
2744 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2745 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2746 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2747 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2748 unsigned align = fieldFromInstruction(Insn, 4, 1);
2749 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2752 switch (Inst.getOpcode()) {
2753 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2754 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2755 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2756 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2757 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2758 return MCDisassembler::Fail;
2760 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2761 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2762 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2763 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2764 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2765 return MCDisassembler::Fail;
2768 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2769 return MCDisassembler::Fail;
2774 Inst.addOperand(MCOperand::CreateImm(0));
2776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2777 return MCDisassembler::Fail;
2778 Inst.addOperand(MCOperand::CreateImm(align));
2780 if (Rm != 0xD && Rm != 0xF) {
2781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2782 return MCDisassembler::Fail;
2788 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2789 uint64_t Address, const void *Decoder) {
2790 DecodeStatus S = MCDisassembler::Success;
2792 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2793 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2794 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2795 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2796 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2799 return MCDisassembler::Fail;
2800 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2801 return MCDisassembler::Fail;
2802 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2803 return MCDisassembler::Fail;
2805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2806 return MCDisassembler::Fail;
2809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2810 return MCDisassembler::Fail;
2811 Inst.addOperand(MCOperand::CreateImm(0));
2814 Inst.addOperand(MCOperand::CreateReg(0));
2815 else if (Rm != 0xF) {
2816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2817 return MCDisassembler::Fail;
2823 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2824 uint64_t Address, const void *Decoder) {
2825 DecodeStatus S = MCDisassembler::Success;
2827 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2828 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2829 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2830 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2831 unsigned size = fieldFromInstruction(Insn, 6, 2);
2832 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2833 unsigned align = fieldFromInstruction(Insn, 4, 1);
2837 return MCDisassembler::Fail;
2850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2851 return MCDisassembler::Fail;
2852 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2853 return MCDisassembler::Fail;
2854 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2855 return MCDisassembler::Fail;
2856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2857 return MCDisassembler::Fail;
2859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2860 return MCDisassembler::Fail;
2863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2864 return MCDisassembler::Fail;
2865 Inst.addOperand(MCOperand::CreateImm(align));
2868 Inst.addOperand(MCOperand::CreateReg(0));
2869 else if (Rm != 0xF) {
2870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2871 return MCDisassembler::Fail;
2878 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2879 uint64_t Address, const void *Decoder) {
2880 DecodeStatus S = MCDisassembler::Success;
2882 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2883 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2884 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2885 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2886 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2887 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2888 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2889 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2892 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2893 return MCDisassembler::Fail;
2895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2896 return MCDisassembler::Fail;
2899 Inst.addOperand(MCOperand::CreateImm(imm));
2901 switch (Inst.getOpcode()) {
2902 case ARM::VORRiv4i16:
2903 case ARM::VORRiv2i32:
2904 case ARM::VBICiv4i16:
2905 case ARM::VBICiv2i32:
2906 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2907 return MCDisassembler::Fail;
2909 case ARM::VORRiv8i16:
2910 case ARM::VORRiv4i32:
2911 case ARM::VBICiv8i16:
2912 case ARM::VBICiv4i32:
2913 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2914 return MCDisassembler::Fail;
2923 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2924 uint64_t Address, const void *Decoder) {
2925 DecodeStatus S = MCDisassembler::Success;
2927 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2928 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2929 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2930 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2931 unsigned size = fieldFromInstruction(Insn, 18, 2);
2933 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2934 return MCDisassembler::Fail;
2935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2936 return MCDisassembler::Fail;
2937 Inst.addOperand(MCOperand::CreateImm(8 << size));
2942 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2943 uint64_t Address, const void *Decoder) {
2944 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2945 return MCDisassembler::Success;
2948 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2949 uint64_t Address, const void *Decoder) {
2950 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2951 return MCDisassembler::Success;
2954 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2955 uint64_t Address, const void *Decoder) {
2956 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2957 return MCDisassembler::Success;
2960 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2961 uint64_t Address, const void *Decoder) {
2962 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2963 return MCDisassembler::Success;
2966 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2967 uint64_t Address, const void *Decoder) {
2968 DecodeStatus S = MCDisassembler::Success;
2970 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2971 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2972 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2973 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2974 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2975 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2976 unsigned op = fieldFromInstruction(Insn, 6, 1);
2978 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2979 return MCDisassembler::Fail;
2981 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2982 return MCDisassembler::Fail; // Writeback
2985 switch (Inst.getOpcode()) {
2988 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2989 return MCDisassembler::Fail;
2992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2993 return MCDisassembler::Fail;
2996 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2997 return MCDisassembler::Fail;
3002 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3003 uint64_t Address, const void *Decoder) {
3004 DecodeStatus S = MCDisassembler::Success;
3006 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3007 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3009 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3010 return MCDisassembler::Fail;
3012 switch(Inst.getOpcode()) {
3014 return MCDisassembler::Fail;
3016 break; // tADR does not explicitly represent the PC as an operand.
3018 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3022 Inst.addOperand(MCOperand::CreateImm(imm));
3026 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3027 uint64_t Address, const void *Decoder) {
3028 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3029 true, 2, Inst, Decoder))
3030 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3031 return MCDisassembler::Success;
3034 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3035 uint64_t Address, const void *Decoder) {
3036 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3037 true, 4, Inst, Decoder))
3038 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3039 return MCDisassembler::Success;
3042 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3043 uint64_t Address, const void *Decoder) {
3044 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3045 true, 2, Inst, Decoder))
3046 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
3047 return MCDisassembler::Success;
3050 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3051 uint64_t Address, const void *Decoder) {
3052 DecodeStatus S = MCDisassembler::Success;
3054 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3055 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3057 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3058 return MCDisassembler::Fail;
3059 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3060 return MCDisassembler::Fail;
3065 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3066 uint64_t Address, const void *Decoder) {
3067 DecodeStatus S = MCDisassembler::Success;
3069 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3070 unsigned imm = fieldFromInstruction(Val, 3, 5);
3072 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3073 return MCDisassembler::Fail;
3074 Inst.addOperand(MCOperand::CreateImm(imm));
3079 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3080 uint64_t Address, const void *Decoder) {
3081 unsigned imm = Val << 2;
3083 Inst.addOperand(MCOperand::CreateImm(imm));
3084 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3086 return MCDisassembler::Success;
3089 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3090 uint64_t Address, const void *Decoder) {
3091 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3092 Inst.addOperand(MCOperand::CreateImm(Val));
3094 return MCDisassembler::Success;
3097 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3098 uint64_t Address, const void *Decoder) {
3099 DecodeStatus S = MCDisassembler::Success;
3101 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3102 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3103 unsigned imm = fieldFromInstruction(Val, 0, 2);
3105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3106 return MCDisassembler::Fail;
3107 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3108 return MCDisassembler::Fail;
3109 Inst.addOperand(MCOperand::CreateImm(imm));
3114 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3115 uint64_t Address, const void *Decoder) {
3116 DecodeStatus S = MCDisassembler::Success;
3118 switch (Inst.getOpcode()) {
3124 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3125 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3126 return MCDisassembler::Fail;
3130 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3132 switch (Inst.getOpcode()) {
3134 Inst.setOpcode(ARM::t2LDRBpci);
3137 Inst.setOpcode(ARM::t2LDRHpci);
3140 Inst.setOpcode(ARM::t2LDRSHpci);
3143 Inst.setOpcode(ARM::t2LDRSBpci);
3146 Inst.setOpcode(ARM::t2PLDi12);
3147 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3150 return MCDisassembler::Fail;
3153 int imm = fieldFromInstruction(Insn, 0, 12);
3154 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
3155 Inst.addOperand(MCOperand::CreateImm(imm));
3160 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3161 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3162 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3163 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3164 return MCDisassembler::Fail;
3169 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3170 uint64_t Address, const void *Decoder) {
3172 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3174 int imm = Val & 0xFF;
3176 if (!(Val & 0x100)) imm *= -1;
3177 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3180 return MCDisassembler::Success;
3183 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3184 uint64_t Address, const void *Decoder) {
3185 DecodeStatus S = MCDisassembler::Success;
3187 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3188 unsigned imm = fieldFromInstruction(Val, 0, 9);
3190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3191 return MCDisassembler::Fail;
3192 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3193 return MCDisassembler::Fail;
3198 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3199 uint64_t Address, const void *Decoder) {
3200 DecodeStatus S = MCDisassembler::Success;
3202 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3203 unsigned imm = fieldFromInstruction(Val, 0, 8);
3205 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3206 return MCDisassembler::Fail;
3208 Inst.addOperand(MCOperand::CreateImm(imm));
3213 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3214 uint64_t Address, const void *Decoder) {
3215 int imm = Val & 0xFF;
3218 else if (!(Val & 0x100))
3220 Inst.addOperand(MCOperand::CreateImm(imm));
3222 return MCDisassembler::Success;
3226 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3227 uint64_t Address, const void *Decoder) {
3228 DecodeStatus S = MCDisassembler::Success;
3230 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3231 unsigned imm = fieldFromInstruction(Val, 0, 9);
3233 // Some instructions always use an additive offset.
3234 switch (Inst.getOpcode()) {
3249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3250 return MCDisassembler::Fail;
3251 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3252 return MCDisassembler::Fail;
3257 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3258 uint64_t Address, const void *Decoder) {
3259 DecodeStatus S = MCDisassembler::Success;
3261 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3262 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3263 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3264 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3266 unsigned load = fieldFromInstruction(Insn, 20, 1);
3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3270 return MCDisassembler::Fail;
3273 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3274 return MCDisassembler::Fail;
3277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3278 return MCDisassembler::Fail;
3281 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3282 return MCDisassembler::Fail;
3287 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3288 uint64_t Address, const void *Decoder) {
3289 DecodeStatus S = MCDisassembler::Success;
3291 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3292 unsigned imm = fieldFromInstruction(Val, 0, 12);
3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3295 return MCDisassembler::Fail;
3296 Inst.addOperand(MCOperand::CreateImm(imm));
3302 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3303 uint64_t Address, const void *Decoder) {
3304 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3306 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3307 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3308 Inst.addOperand(MCOperand::CreateImm(imm));
3310 return MCDisassembler::Success;
3313 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3314 uint64_t Address, const void *Decoder) {
3315 DecodeStatus S = MCDisassembler::Success;
3317 if (Inst.getOpcode() == ARM::tADDrSP) {
3318 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3319 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3322 return MCDisassembler::Fail;
3323 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3325 return MCDisassembler::Fail;
3326 } else if (Inst.getOpcode() == ARM::tADDspr) {
3327 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3329 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3330 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3332 return MCDisassembler::Fail;
3338 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3339 uint64_t Address, const void *Decoder) {
3340 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3341 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3343 Inst.addOperand(MCOperand::CreateImm(imod));
3344 Inst.addOperand(MCOperand::CreateImm(flags));
3346 return MCDisassembler::Success;
3349 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3350 uint64_t Address, const void *Decoder) {
3351 DecodeStatus S = MCDisassembler::Success;
3352 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3353 unsigned add = fieldFromInstruction(Insn, 4, 1);
3355 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3356 return MCDisassembler::Fail;
3357 Inst.addOperand(MCOperand::CreateImm(add));
3362 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3363 uint64_t Address, const void *Decoder) {
3364 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3365 // Note only one trailing zero not two. Also the J1 and J2 values are from
3366 // the encoded instruction. So here change to I1 and I2 values via:
3367 // I1 = NOT(J1 EOR S);
3368 // I2 = NOT(J2 EOR S);
3369 // and build the imm32 with two trailing zeros as documented:
3370 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3371 unsigned S = (Val >> 23) & 1;
3372 unsigned J1 = (Val >> 22) & 1;
3373 unsigned J2 = (Val >> 21) & 1;
3374 unsigned I1 = !(J1 ^ S);
3375 unsigned I2 = !(J2 ^ S);
3376 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3377 int imm32 = SignExtend32<25>(tmp << 1);
3379 if (!tryAddingSymbolicOperand(Address,
3380 (Address & ~2u) + imm32 + 4,
3381 true, 4, Inst, Decoder))
3382 Inst.addOperand(MCOperand::CreateImm(imm32));
3383 return MCDisassembler::Success;
3386 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3387 uint64_t Address, const void *Decoder) {
3388 if (Val == 0xA || Val == 0xB)
3389 return MCDisassembler::Fail;
3391 Inst.addOperand(MCOperand::CreateImm(Val));
3392 return MCDisassembler::Success;
3396 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3397 uint64_t Address, const void *Decoder) {
3398 DecodeStatus S = MCDisassembler::Success;
3400 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3401 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3403 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3405 return MCDisassembler::Fail;
3406 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3407 return MCDisassembler::Fail;
3412 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3413 uint64_t Address, const void *Decoder) {
3414 DecodeStatus S = MCDisassembler::Success;
3416 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3417 if (pred == 0xE || pred == 0xF) {
3418 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3421 return MCDisassembler::Fail;
3423 Inst.setOpcode(ARM::t2DSB);
3426 Inst.setOpcode(ARM::t2DMB);
3429 Inst.setOpcode(ARM::t2ISB);
3433 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3434 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3437 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3438 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3439 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3440 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3441 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3443 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3444 return MCDisassembler::Fail;
3445 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3446 return MCDisassembler::Fail;
3451 // Decode a shifted immediate operand. These basically consist
3452 // of an 8-bit value, and a 4-bit directive that specifies either
3453 // a splat operation or a rotation.
3454 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3455 uint64_t Address, const void *Decoder) {
3456 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3458 unsigned byte = fieldFromInstruction(Val, 8, 2);
3459 unsigned imm = fieldFromInstruction(Val, 0, 8);
3462 Inst.addOperand(MCOperand::CreateImm(imm));
3465 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3468 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3471 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3476 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3477 unsigned rot = fieldFromInstruction(Val, 7, 5);
3478 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3479 Inst.addOperand(MCOperand::CreateImm(imm));
3482 return MCDisassembler::Success;
3486 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3487 uint64_t Address, const void *Decoder){
3488 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3489 true, 2, Inst, Decoder))
3490 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3491 return MCDisassembler::Success;
3494 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3495 uint64_t Address, const void *Decoder){
3496 // Val is passed in as S:J1:J2:imm10:imm11
3497 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3498 // the encoded instruction. So here change to I1 and I2 values via:
3499 // I1 = NOT(J1 EOR S);
3500 // I2 = NOT(J2 EOR S);
3501 // and build the imm32 with one trailing zero as documented:
3502 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3503 unsigned S = (Val >> 23) & 1;
3504 unsigned J1 = (Val >> 22) & 1;
3505 unsigned J2 = (Val >> 21) & 1;
3506 unsigned I1 = !(J1 ^ S);
3507 unsigned I2 = !(J2 ^ S);
3508 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3509 int imm32 = SignExtend32<25>(tmp << 1);
3511 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3512 true, 4, Inst, Decoder))
3513 Inst.addOperand(MCOperand::CreateImm(imm32));
3514 return MCDisassembler::Success;
3517 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3518 uint64_t Address, const void *Decoder) {
3520 return MCDisassembler::Fail;
3522 Inst.addOperand(MCOperand::CreateImm(Val));
3523 return MCDisassembler::Success;
3526 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3527 uint64_t Address, const void *Decoder) {
3528 if (!Val) return MCDisassembler::Fail;
3529 Inst.addOperand(MCOperand::CreateImm(Val));
3530 return MCDisassembler::Success;
3533 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3534 uint64_t Address, const void *Decoder) {
3535 DecodeStatus S = MCDisassembler::Success;
3537 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3538 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3539 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3541 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3544 return MCDisassembler::Fail;
3545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3546 return MCDisassembler::Fail;
3547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3548 return MCDisassembler::Fail;
3549 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3550 return MCDisassembler::Fail;
3556 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3557 uint64_t Address, const void *Decoder){
3558 DecodeStatus S = MCDisassembler::Success;
3560 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3561 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3562 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3563 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3565 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3566 return MCDisassembler::Fail;
3568 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3569 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3572 return MCDisassembler::Fail;
3573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3574 return MCDisassembler::Fail;
3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3578 return MCDisassembler::Fail;
3583 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3584 uint64_t Address, const void *Decoder) {
3585 DecodeStatus S = MCDisassembler::Success;
3587 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3588 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3589 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3590 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3591 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3592 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3594 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3597 return MCDisassembler::Fail;
3598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3599 return MCDisassembler::Fail;
3600 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3601 return MCDisassembler::Fail;
3602 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3603 return MCDisassembler::Fail;
3608 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3609 uint64_t Address, const void *Decoder) {
3610 DecodeStatus S = MCDisassembler::Success;
3612 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3613 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3614 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3615 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3616 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3617 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3618 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3620 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3621 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3624 return MCDisassembler::Fail;
3625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3626 return MCDisassembler::Fail;
3627 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3628 return MCDisassembler::Fail;
3629 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3630 return MCDisassembler::Fail;
3636 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3637 uint64_t Address, const void *Decoder) {
3638 DecodeStatus S = MCDisassembler::Success;
3640 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3641 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3642 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3643 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3644 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3645 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3647 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3650 return MCDisassembler::Fail;
3651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3652 return MCDisassembler::Fail;
3653 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3654 return MCDisassembler::Fail;
3655 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3656 return MCDisassembler::Fail;
3661 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3662 uint64_t Address, const void *Decoder) {
3663 DecodeStatus S = MCDisassembler::Success;
3665 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3666 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3667 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3668 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3669 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3670 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3672 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3675 return MCDisassembler::Fail;
3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3677 return MCDisassembler::Fail;
3678 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3681 return MCDisassembler::Fail;
3686 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3687 uint64_t Address, const void *Decoder) {
3688 DecodeStatus S = MCDisassembler::Success;
3690 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3691 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3692 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3693 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3694 unsigned size = fieldFromInstruction(Insn, 10, 2);
3700 return MCDisassembler::Fail;
3702 if (fieldFromInstruction(Insn, 4, 1))
3703 return MCDisassembler::Fail; // UNDEFINED
3704 index = fieldFromInstruction(Insn, 5, 3);
3707 if (fieldFromInstruction(Insn, 5, 1))
3708 return MCDisassembler::Fail; // UNDEFINED
3709 index = fieldFromInstruction(Insn, 6, 2);
3710 if (fieldFromInstruction(Insn, 4, 1))
3714 if (fieldFromInstruction(Insn, 6, 1))
3715 return MCDisassembler::Fail; // UNDEFINED
3716 index = fieldFromInstruction(Insn, 7, 1);
3718 switch (fieldFromInstruction(Insn, 4, 2)) {
3724 return MCDisassembler::Fail;
3729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 if (Rm != 0xF) { // Writeback
3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3733 return MCDisassembler::Fail;
3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3736 return MCDisassembler::Fail;
3737 Inst.addOperand(MCOperand::CreateImm(align));
3740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3741 return MCDisassembler::Fail;
3743 Inst.addOperand(MCOperand::CreateReg(0));
3746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3747 return MCDisassembler::Fail;
3748 Inst.addOperand(MCOperand::CreateImm(index));
3753 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3754 uint64_t Address, const void *Decoder) {
3755 DecodeStatus S = MCDisassembler::Success;
3757 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3758 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3759 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3760 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3761 unsigned size = fieldFromInstruction(Insn, 10, 2);
3767 return MCDisassembler::Fail;
3769 if (fieldFromInstruction(Insn, 4, 1))
3770 return MCDisassembler::Fail; // UNDEFINED
3771 index = fieldFromInstruction(Insn, 5, 3);
3774 if (fieldFromInstruction(Insn, 5, 1))
3775 return MCDisassembler::Fail; // UNDEFINED
3776 index = fieldFromInstruction(Insn, 6, 2);
3777 if (fieldFromInstruction(Insn, 4, 1))
3781 if (fieldFromInstruction(Insn, 6, 1))
3782 return MCDisassembler::Fail; // UNDEFINED
3783 index = fieldFromInstruction(Insn, 7, 1);
3785 switch (fieldFromInstruction(Insn, 4, 2)) {
3791 return MCDisassembler::Fail;
3796 if (Rm != 0xF) { // Writeback
3797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3798 return MCDisassembler::Fail;
3800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3801 return MCDisassembler::Fail;
3802 Inst.addOperand(MCOperand::CreateImm(align));
3805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3806 return MCDisassembler::Fail;
3808 Inst.addOperand(MCOperand::CreateReg(0));
3811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3812 return MCDisassembler::Fail;
3813 Inst.addOperand(MCOperand::CreateImm(index));
3819 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3820 uint64_t Address, const void *Decoder) {
3821 DecodeStatus S = MCDisassembler::Success;
3823 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3824 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3825 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3826 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3827 unsigned size = fieldFromInstruction(Insn, 10, 2);
3834 return MCDisassembler::Fail;
3836 index = fieldFromInstruction(Insn, 5, 3);
3837 if (fieldFromInstruction(Insn, 4, 1))
3841 index = fieldFromInstruction(Insn, 6, 2);
3842 if (fieldFromInstruction(Insn, 4, 1))
3844 if (fieldFromInstruction(Insn, 5, 1))
3848 if (fieldFromInstruction(Insn, 5, 1))
3849 return MCDisassembler::Fail; // UNDEFINED
3850 index = fieldFromInstruction(Insn, 7, 1);
3851 if (fieldFromInstruction(Insn, 4, 1) != 0)
3853 if (fieldFromInstruction(Insn, 6, 1))
3858 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3859 return MCDisassembler::Fail;
3860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3861 return MCDisassembler::Fail;
3862 if (Rm != 0xF) { // Writeback
3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3864 return MCDisassembler::Fail;
3866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3867 return MCDisassembler::Fail;
3868 Inst.addOperand(MCOperand::CreateImm(align));
3871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3872 return MCDisassembler::Fail;
3874 Inst.addOperand(MCOperand::CreateReg(0));
3877 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3878 return MCDisassembler::Fail;
3879 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3880 return MCDisassembler::Fail;
3881 Inst.addOperand(MCOperand::CreateImm(index));
3886 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3887 uint64_t Address, const void *Decoder) {
3888 DecodeStatus S = MCDisassembler::Success;
3890 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3891 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3892 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3893 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3894 unsigned size = fieldFromInstruction(Insn, 10, 2);
3901 return MCDisassembler::Fail;
3903 index = fieldFromInstruction(Insn, 5, 3);
3904 if (fieldFromInstruction(Insn, 4, 1))
3908 index = fieldFromInstruction(Insn, 6, 2);
3909 if (fieldFromInstruction(Insn, 4, 1))
3911 if (fieldFromInstruction(Insn, 5, 1))
3915 if (fieldFromInstruction(Insn, 5, 1))
3916 return MCDisassembler::Fail; // UNDEFINED
3917 index = fieldFromInstruction(Insn, 7, 1);
3918 if (fieldFromInstruction(Insn, 4, 1) != 0)
3920 if (fieldFromInstruction(Insn, 6, 1))
3925 if (Rm != 0xF) { // Writeback
3926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3927 return MCDisassembler::Fail;
3929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3930 return MCDisassembler::Fail;
3931 Inst.addOperand(MCOperand::CreateImm(align));
3934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3935 return MCDisassembler::Fail;
3937 Inst.addOperand(MCOperand::CreateReg(0));
3940 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3941 return MCDisassembler::Fail;
3942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3943 return MCDisassembler::Fail;
3944 Inst.addOperand(MCOperand::CreateImm(index));
3950 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
3951 uint64_t Address, const void *Decoder) {
3952 DecodeStatus S = MCDisassembler::Success;
3954 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3955 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3956 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3957 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3958 unsigned size = fieldFromInstruction(Insn, 10, 2);
3965 return MCDisassembler::Fail;
3967 if (fieldFromInstruction(Insn, 4, 1))
3968 return MCDisassembler::Fail; // UNDEFINED
3969 index = fieldFromInstruction(Insn, 5, 3);
3972 if (fieldFromInstruction(Insn, 4, 1))
3973 return MCDisassembler::Fail; // UNDEFINED
3974 index = fieldFromInstruction(Insn, 6, 2);
3975 if (fieldFromInstruction(Insn, 5, 1))
3979 if (fieldFromInstruction(Insn, 4, 2))
3980 return MCDisassembler::Fail; // UNDEFINED
3981 index = fieldFromInstruction(Insn, 7, 1);
3982 if (fieldFromInstruction(Insn, 6, 1))
3987 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3988 return MCDisassembler::Fail;
3989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3990 return MCDisassembler::Fail;
3991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3992 return MCDisassembler::Fail;
3994 if (Rm != 0xF) { // Writeback
3995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3996 return MCDisassembler::Fail;
3998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3999 return MCDisassembler::Fail;
4000 Inst.addOperand(MCOperand::CreateImm(align));
4003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4004 return MCDisassembler::Fail;
4006 Inst.addOperand(MCOperand::CreateReg(0));
4009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4010 return MCDisassembler::Fail;
4011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4012 return MCDisassembler::Fail;
4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4014 return MCDisassembler::Fail;
4015 Inst.addOperand(MCOperand::CreateImm(index));
4020 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4021 uint64_t Address, const void *Decoder) {
4022 DecodeStatus S = MCDisassembler::Success;
4024 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4025 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4026 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4027 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4028 unsigned size = fieldFromInstruction(Insn, 10, 2);
4035 return MCDisassembler::Fail;
4037 if (fieldFromInstruction(Insn, 4, 1))
4038 return MCDisassembler::Fail; // UNDEFINED
4039 index = fieldFromInstruction(Insn, 5, 3);
4042 if (fieldFromInstruction(Insn, 4, 1))
4043 return MCDisassembler::Fail; // UNDEFINED
4044 index = fieldFromInstruction(Insn, 6, 2);
4045 if (fieldFromInstruction(Insn, 5, 1))
4049 if (fieldFromInstruction(Insn, 4, 2))
4050 return MCDisassembler::Fail; // UNDEFINED
4051 index = fieldFromInstruction(Insn, 7, 1);
4052 if (fieldFromInstruction(Insn, 6, 1))
4057 if (Rm != 0xF) { // Writeback
4058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4059 return MCDisassembler::Fail;
4061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4062 return MCDisassembler::Fail;
4063 Inst.addOperand(MCOperand::CreateImm(align));
4066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4067 return MCDisassembler::Fail;
4069 Inst.addOperand(MCOperand::CreateReg(0));
4072 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4073 return MCDisassembler::Fail;
4074 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4075 return MCDisassembler::Fail;
4076 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4077 return MCDisassembler::Fail;
4078 Inst.addOperand(MCOperand::CreateImm(index));
4084 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4085 uint64_t Address, const void *Decoder) {
4086 DecodeStatus S = MCDisassembler::Success;
4088 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4089 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4090 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4091 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4092 unsigned size = fieldFromInstruction(Insn, 10, 2);
4099 return MCDisassembler::Fail;
4101 if (fieldFromInstruction(Insn, 4, 1))
4103 index = fieldFromInstruction(Insn, 5, 3);
4106 if (fieldFromInstruction(Insn, 4, 1))
4108 index = fieldFromInstruction(Insn, 6, 2);
4109 if (fieldFromInstruction(Insn, 5, 1))
4113 switch (fieldFromInstruction(Insn, 4, 2)) {
4117 return MCDisassembler::Fail;
4119 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4122 index = fieldFromInstruction(Insn, 7, 1);
4123 if (fieldFromInstruction(Insn, 6, 1))
4128 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4129 return MCDisassembler::Fail;
4130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4131 return MCDisassembler::Fail;
4132 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4133 return MCDisassembler::Fail;
4134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4135 return MCDisassembler::Fail;
4137 if (Rm != 0xF) { // Writeback
4138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4139 return MCDisassembler::Fail;
4141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4142 return MCDisassembler::Fail;
4143 Inst.addOperand(MCOperand::CreateImm(align));
4146 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4147 return MCDisassembler::Fail;
4149 Inst.addOperand(MCOperand::CreateReg(0));
4152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4153 return MCDisassembler::Fail;
4154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4155 return MCDisassembler::Fail;
4156 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4157 return MCDisassembler::Fail;
4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4159 return MCDisassembler::Fail;
4160 Inst.addOperand(MCOperand::CreateImm(index));
4165 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4166 uint64_t Address, const void *Decoder) {
4167 DecodeStatus S = MCDisassembler::Success;
4169 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4170 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4171 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4172 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4173 unsigned size = fieldFromInstruction(Insn, 10, 2);
4180 return MCDisassembler::Fail;
4182 if (fieldFromInstruction(Insn, 4, 1))
4184 index = fieldFromInstruction(Insn, 5, 3);
4187 if (fieldFromInstruction(Insn, 4, 1))
4189 index = fieldFromInstruction(Insn, 6, 2);
4190 if (fieldFromInstruction(Insn, 5, 1))
4194 switch (fieldFromInstruction(Insn, 4, 2)) {
4198 return MCDisassembler::Fail;
4200 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4203 index = fieldFromInstruction(Insn, 7, 1);
4204 if (fieldFromInstruction(Insn, 6, 1))
4209 if (Rm != 0xF) { // Writeback
4210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4211 return MCDisassembler::Fail;
4213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4214 return MCDisassembler::Fail;
4215 Inst.addOperand(MCOperand::CreateImm(align));
4218 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4219 return MCDisassembler::Fail;
4221 Inst.addOperand(MCOperand::CreateReg(0));
4224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4225 return MCDisassembler::Fail;
4226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4227 return MCDisassembler::Fail;
4228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 Inst.addOperand(MCOperand::CreateImm(index));
4237 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4238 uint64_t Address, const void *Decoder) {
4239 DecodeStatus S = MCDisassembler::Success;
4240 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4241 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4242 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4243 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4244 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4246 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4247 S = MCDisassembler::SoftFail;
4249 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4250 return MCDisassembler::Fail;
4251 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4252 return MCDisassembler::Fail;
4253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4254 return MCDisassembler::Fail;
4255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4256 return MCDisassembler::Fail;
4257 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4258 return MCDisassembler::Fail;
4263 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4264 uint64_t Address, const void *Decoder) {
4265 DecodeStatus S = MCDisassembler::Success;
4266 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4267 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4268 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4269 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4270 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4272 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4273 S = MCDisassembler::SoftFail;
4275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4276 return MCDisassembler::Fail;
4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4278 return MCDisassembler::Fail;
4279 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4280 return MCDisassembler::Fail;
4281 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4282 return MCDisassembler::Fail;
4283 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4284 return MCDisassembler::Fail;
4289 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4290 uint64_t Address, const void *Decoder) {
4291 DecodeStatus S = MCDisassembler::Success;
4292 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4293 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4297 S = MCDisassembler::SoftFail;
4302 S = MCDisassembler::SoftFail;
4305 Inst.addOperand(MCOperand::CreateImm(pred));
4306 Inst.addOperand(MCOperand::CreateImm(mask));
4311 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4312 uint64_t Address, const void *Decoder) {
4313 DecodeStatus S = MCDisassembler::Success;
4315 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4316 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4317 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4318 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4319 unsigned W = fieldFromInstruction(Insn, 21, 1);
4320 unsigned U = fieldFromInstruction(Insn, 23, 1);
4321 unsigned P = fieldFromInstruction(Insn, 24, 1);
4322 bool writeback = (W == 1) | (P == 0);
4324 addr |= (U << 8) | (Rn << 9);
4326 if (writeback && (Rn == Rt || Rn == Rt2))
4327 Check(S, MCDisassembler::SoftFail);
4329 Check(S, MCDisassembler::SoftFail);
4332 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4333 return MCDisassembler::Fail;
4335 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4336 return MCDisassembler::Fail;
4337 // Writeback operand
4338 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4339 return MCDisassembler::Fail;
4341 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4342 return MCDisassembler::Fail;
4348 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4349 uint64_t Address, const void *Decoder) {
4350 DecodeStatus S = MCDisassembler::Success;
4352 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4353 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4354 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4355 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4356 unsigned W = fieldFromInstruction(Insn, 21, 1);
4357 unsigned U = fieldFromInstruction(Insn, 23, 1);
4358 unsigned P = fieldFromInstruction(Insn, 24, 1);
4359 bool writeback = (W == 1) | (P == 0);
4361 addr |= (U << 8) | (Rn << 9);
4363 if (writeback && (Rn == Rt || Rn == Rt2))
4364 Check(S, MCDisassembler::SoftFail);
4366 // Writeback operand
4367 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4368 return MCDisassembler::Fail;
4370 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4371 return MCDisassembler::Fail;
4373 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4374 return MCDisassembler::Fail;
4376 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4377 return MCDisassembler::Fail;
4382 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4383 uint64_t Address, const void *Decoder) {
4384 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4385 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4386 if (sign1 != sign2) return MCDisassembler::Fail;
4388 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4389 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4390 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4392 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4394 return MCDisassembler::Success;
4397 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4399 const void *Decoder) {
4400 DecodeStatus S = MCDisassembler::Success;
4402 // Shift of "asr #32" is not allowed in Thumb2 mode.
4403 if (Val == 0x20) S = MCDisassembler::SoftFail;
4404 Inst.addOperand(MCOperand::CreateImm(Val));
4408 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4409 uint64_t Address, const void *Decoder) {
4410 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4411 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4412 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4413 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4416 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4418 DecodeStatus S = MCDisassembler::Success;
4420 if (Rt == Rn || Rn == Rt2)
4421 S = MCDisassembler::SoftFail;
4423 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4424 return MCDisassembler::Fail;
4425 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4426 return MCDisassembler::Fail;
4427 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4428 return MCDisassembler::Fail;
4429 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4430 return MCDisassembler::Fail;
4435 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4436 uint64_t Address, const void *Decoder) {
4437 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4438 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4439 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4440 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4441 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4442 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4444 DecodeStatus S = MCDisassembler::Success;
4446 // VMOVv2f32 is ambiguous with these decodings.
4447 if (!(imm & 0x38) && cmode == 0xF) {
4448 Inst.setOpcode(ARM::VMOVv2f32);
4449 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4452 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4454 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4455 return MCDisassembler::Fail;
4456 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4457 return MCDisassembler::Fail;
4458 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4463 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4464 uint64_t Address, const void *Decoder) {
4465 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4466 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4467 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4468 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4469 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4470 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4472 DecodeStatus S = MCDisassembler::Success;
4474 // VMOVv4f32 is ambiguous with these decodings.
4475 if (!(imm & 0x38) && cmode == 0xF) {
4476 Inst.setOpcode(ARM::VMOVv4f32);
4477 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4480 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4482 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4483 return MCDisassembler::Fail;
4484 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4485 return MCDisassembler::Fail;
4486 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4491 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4492 uint64_t Address, const void *Decoder) {
4493 DecodeStatus S = MCDisassembler::Success;
4495 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4496 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4497 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4498 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4499 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4501 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4502 S = MCDisassembler::SoftFail;
4504 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4505 return MCDisassembler::Fail;
4506 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4507 return MCDisassembler::Fail;
4508 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4509 return MCDisassembler::Fail;
4510 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4511 return MCDisassembler::Fail;
4512 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4513 return MCDisassembler::Fail;
4518 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4519 uint64_t Address, const void *Decoder) {
4521 DecodeStatus S = MCDisassembler::Success;
4523 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4524 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4525 unsigned cop = fieldFromInstruction(Val, 8, 4);
4526 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4527 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4529 if ((cop & ~0x1) == 0xa)
4530 return MCDisassembler::Fail;
4533 S = MCDisassembler::SoftFail;
4535 Inst.addOperand(MCOperand::CreateImm(cop));
4536 Inst.addOperand(MCOperand::CreateImm(opc1));
4537 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4538 return MCDisassembler::Fail;
4539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4540 return MCDisassembler::Fail;
4541 Inst.addOperand(MCOperand::CreateImm(CRm));