1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/EDInstInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/LEB128.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
33 typedef MCDisassembler::DecodeStatus DecodeStatus;
36 // Handles the condition code status of instructions in IT blocks
40 // Returns the condition code for instruction in IT block
42 unsigned CC = ARMCC::AL;
48 // Advances the IT block state to the next T or E
49 void advanceITState() {
53 // Returns true if the current instruction is in an IT block
54 bool instrInITBlock() {
55 return !ITStates.empty();
58 // Returns true if current instruction is the last instruction in an IT block
59 bool instrLastInITBlock() {
60 return ITStates.size() == 1;
63 // Called when decoding an IT instruction. Sets the IT state for the following
64 // instructions that for the IT block. Firstcond and Mask correspond to the
65 // fields in the IT instruction encoding.
66 void setITState(char Firstcond, char Mask) {
67 // (3 - the number of trailing zeros) is the number of then / else.
68 unsigned CondBit0 = Firstcond & 1;
69 unsigned NumTZ = CountTrailingZeros_32(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
74 bool T = ((Mask >> Pos) & 1) == CondBit0;
76 ITStates.push_back(CCBits);
78 ITStates.push_back(CCBits ^ 1);
80 ITStates.push_back(CCBits);
84 std::vector<unsigned char> ITStates;
89 /// ARMDisassembler - ARM disassembler for all ARM platforms.
90 class ARMDisassembler : public MCDisassembler {
92 /// Constructor - Initializes the disassembler.
94 ARMDisassembler(const MCSubtargetInfo &STI) :
101 /// getInstruction - See MCDisassembler.
102 DecodeStatus getInstruction(MCInst &instr,
104 const MemoryObject ®ion,
106 raw_ostream &vStream,
107 raw_ostream &cStream) const;
109 /// getEDInfo - See MCDisassembler.
110 const EDInstInfo *getEDInfo() const;
114 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
115 class ThumbDisassembler : public MCDisassembler {
117 /// Constructor - Initializes the disassembler.
119 ThumbDisassembler(const MCSubtargetInfo &STI) :
120 MCDisassembler(STI) {
123 ~ThumbDisassembler() {
126 /// getInstruction - See MCDisassembler.
127 DecodeStatus getInstruction(MCInst &instr,
129 const MemoryObject ®ion,
131 raw_ostream &vStream,
132 raw_ostream &cStream) const;
134 /// getEDInfo - See MCDisassembler.
135 const EDInstInfo *getEDInfo() const;
137 mutable ITStatus ITBlock;
138 DecodeStatus AddThumbPredicate(MCInst&) const;
139 void UpdateThumbVFPPredicate(MCInst&) const;
143 static bool Check(DecodeStatus &Out, DecodeStatus In) {
145 case MCDisassembler::Success:
146 // Out stays the same.
148 case MCDisassembler::SoftFail:
151 case MCDisassembler::Fail:
155 llvm_unreachable("Invalid DecodeStatus!");
159 // Forward declare these because the autogenerated code will reference them.
160 // Definitions are further down.
161 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
164 unsigned RegNo, uint64_t Address,
165 const void *Decoder);
166 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
181 const void *Decoder);
182 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
187 unsigned RegNo, uint64_t Address,
188 const void *Decoder);
190 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
210 const void *Decoder);
211 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
223 const void *Decoder);
224 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
387 #include "ARMGenDisassemblerTables.inc"
388 #include "ARMGenEDInfo.inc"
390 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
391 return new ARMDisassembler(STI);
394 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
395 return new ThumbDisassembler(STI);
398 const EDInstInfo *ARMDisassembler::getEDInfo() const {
402 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
406 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
407 const MemoryObject &Region,
410 raw_ostream &cs) const {
415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
418 // We want to read exactly 4 bytes of data.
419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
421 return MCDisassembler::Fail;
424 // Encoded as a small-endian 32-bit word in the stream.
425 uint32_t insn = (bytes[3] << 24) |
430 // Calling the auto-generated decoder function.
431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
433 if (result != MCDisassembler::Fail) {
438 // VFP and NEON instructions, similarly, are shared between ARM
441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
442 if (result != MCDisassembler::Fail) {
448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
450 if (result != MCDisassembler::Fail) {
452 // Add a fake predicate operand, because we share these instruction
453 // definitions with Thumb2 where these instructions are predicable.
454 if (!DecodePredicateOperand(MI, 0xE, Address, this))
455 return MCDisassembler::Fail;
460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
462 if (result != MCDisassembler::Fail) {
464 // Add a fake predicate operand, because we share these instruction
465 // definitions with Thumb2 where these instructions are predicable.
466 if (!DecodePredicateOperand(MI, 0xE, Address, this))
467 return MCDisassembler::Fail;
472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
474 if (result != MCDisassembler::Fail) {
476 // Add a fake predicate operand, because we share these instruction
477 // definitions with Thumb2 where these instructions are predicable.
478 if (!DecodePredicateOperand(MI, 0xE, Address, this))
479 return MCDisassembler::Fail;
486 return MCDisassembler::Fail;
490 extern const MCInstrDesc ARMInsts[];
493 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
494 /// immediate Value in the MCInst. The immediate Value has had any PC
495 /// adjustment made by the caller. If the instruction is a branch instruction
496 /// then isBranch is true, else false. If the getOpInfo() function was set as
497 /// part of the setupForSymbolicDisassembly() call then that function is called
498 /// to get any symbolic information at the Address for this instruction. If
499 /// that returns non-zero then the symbolic information it returns is used to
500 /// create an MCExpr and that is added as an operand to the MCInst. If
501 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
502 /// Value is done and if a symbol is found an MCExpr is created with that, else
503 /// an MCExpr with Value is created. This function returns true if it adds an
504 /// operand to the MCInst and false otherwise.
505 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
506 bool isBranch, uint64_t InstSize,
507 MCInst &MI, const void *Decoder) {
508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
510 struct LLVMOpInfo1 SymbolicOp;
511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
512 SymbolicOp.Value = Value;
513 void *DisInfo = Dis->getDisInfoBlock();
516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
517 // Clear SymbolicOp.Value from above and also all other fields.
518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
522 uint64_t ReferenceType;
524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
527 const char *ReferenceName;
528 uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
529 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
530 Address, &ReferenceName);
532 SymbolicOp.AddSymbol.Name = Name;
533 SymbolicOp.AddSymbol.Present = true;
535 // For branches always create an MCExpr so it gets printed as hex address.
537 SymbolicOp.Value = Value;
539 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
540 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
541 if (!Name && !isBranch)
545 MCContext *Ctx = Dis->getMCContext();
546 const MCExpr *Add = NULL;
547 if (SymbolicOp.AddSymbol.Present) {
548 if (SymbolicOp.AddSymbol.Name) {
549 StringRef Name(SymbolicOp.AddSymbol.Name);
550 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
551 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
553 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
557 const MCExpr *Sub = NULL;
558 if (SymbolicOp.SubtractSymbol.Present) {
559 if (SymbolicOp.SubtractSymbol.Name) {
560 StringRef Name(SymbolicOp.SubtractSymbol.Name);
561 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
562 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
564 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
568 const MCExpr *Off = NULL;
569 if (SymbolicOp.Value != 0)
570 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
576 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
578 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
580 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
585 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
592 Expr = MCConstantExpr::Create(0, *Ctx);
595 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
596 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
597 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
598 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
599 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
600 MI.addOperand(MCOperand::CreateExpr(Expr));
602 llvm_unreachable("bad SymbolicOp.VariantKind");
607 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
608 /// referenced by a load instruction with the base register that is the Pc.
609 /// These can often be values in a literal pool near the Address of the
610 /// instruction. The Address of the instruction and its immediate Value are
611 /// used as a possible literal pool entry. The SymbolLookUp call back will
612 /// return the name of a symbol referenced by the literal pool's entry if
613 /// the referenced address is that of a symbol. Or it will return a pointer to
614 /// a literal 'C' string if the referenced address of the literal pool's entry
615 /// is an address into a section with 'C' string literals.
616 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
617 const void *Decoder) {
618 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
619 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
621 void *DisInfo = Dis->getDisInfoBlock();
622 uint64_t ReferenceType;
623 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
624 const char *ReferenceName;
625 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
626 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
627 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
628 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
632 // Thumb1 instructions don't have explicit S bits. Rather, they
633 // implicitly set CPSR. Since it's not represented in the encoding, the
634 // auto-generated decoder won't inject the CPSR operand. We need to fix
635 // that as a post-pass.
636 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
639 MCInst::iterator I = MI.begin();
640 for (unsigned i = 0; i < NumOps; ++i, ++I) {
641 if (I == MI.end()) break;
642 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
643 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
644 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
649 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
652 // Most Thumb instructions don't have explicit predicates in the
653 // encoding, but rather get their predicates from IT context. We need
654 // to fix up the predicate operands using this context information as a
656 MCDisassembler::DecodeStatus
657 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
658 MCDisassembler::DecodeStatus S = Success;
660 // A few instructions actually have predicates encoded in them. Don't
661 // try to overwrite it if we're seeing one of those.
662 switch (MI.getOpcode()) {
673 // Some instructions (mostly conditional branches) are not
674 // allowed in IT blocks.
675 if (ITBlock.instrInITBlock())
684 // Some instructions (mostly unconditional branches) can
685 // only appears at the end of, or outside of, an IT.
686 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
693 // If we're in an IT block, base the predicate on that. Otherwise,
694 // assume a predicate of AL.
696 CC = ITBlock.getITCC();
699 if (ITBlock.instrInITBlock())
700 ITBlock.advanceITState();
702 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
703 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
704 MCInst::iterator I = MI.begin();
705 for (unsigned i = 0; i < NumOps; ++i, ++I) {
706 if (I == MI.end()) break;
707 if (OpInfo[i].isPredicate()) {
708 I = MI.insert(I, MCOperand::CreateImm(CC));
711 MI.insert(I, MCOperand::CreateReg(0));
713 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
718 I = MI.insert(I, MCOperand::CreateImm(CC));
721 MI.insert(I, MCOperand::CreateReg(0));
723 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
728 // Thumb VFP instructions are a special case. Because we share their
729 // encodings between ARM and Thumb modes, and they are predicable in ARM
730 // mode, the auto-generated decoder will give them an (incorrect)
731 // predicate operand. We need to rewrite these operands based on the IT
732 // context as a post-pass.
733 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
735 CC = ITBlock.getITCC();
736 if (ITBlock.instrInITBlock())
737 ITBlock.advanceITState();
739 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
740 MCInst::iterator I = MI.begin();
741 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
742 for (unsigned i = 0; i < NumOps; ++i, ++I) {
743 if (OpInfo[i].isPredicate() ) {
749 I->setReg(ARM::CPSR);
755 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
756 const MemoryObject &Region,
759 raw_ostream &cs) const {
764 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
765 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
767 // We want to read exactly 2 bytes of data.
768 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
770 return MCDisassembler::Fail;
773 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
774 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
776 if (result != MCDisassembler::Fail) {
778 Check(result, AddThumbPredicate(MI));
783 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
787 bool InITBlock = ITBlock.instrInITBlock();
788 Check(result, AddThumbPredicate(MI));
789 AddThumb1SBit(MI, InITBlock);
794 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
796 if (result != MCDisassembler::Fail) {
799 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
800 // the Thumb predicate.
801 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
802 result = MCDisassembler::SoftFail;
804 Check(result, AddThumbPredicate(MI));
806 // If we find an IT instruction, we need to parse its condition
807 // code and mask operands so that we can apply them correctly
808 // to the subsequent instructions.
809 if (MI.getOpcode() == ARM::t2IT) {
811 unsigned Firstcond = MI.getOperand(0).getImm();
812 unsigned Mask = MI.getOperand(1).getImm();
813 ITBlock.setITState(Firstcond, Mask);
819 // We want to read exactly 4 bytes of data.
820 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
822 return MCDisassembler::Fail;
825 uint32_t insn32 = (bytes[3] << 8) |
830 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
832 if (result != MCDisassembler::Fail) {
834 bool InITBlock = ITBlock.instrInITBlock();
835 Check(result, AddThumbPredicate(MI));
836 AddThumb1SBit(MI, InITBlock);
841 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
843 if (result != MCDisassembler::Fail) {
845 Check(result, AddThumbPredicate(MI));
850 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
851 if (result != MCDisassembler::Fail) {
853 UpdateThumbVFPPredicate(MI);
858 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
860 if (result != MCDisassembler::Fail) {
862 Check(result, AddThumbPredicate(MI));
866 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
868 uint32_t NEONLdStInsn = insn32;
869 NEONLdStInsn &= 0xF0FFFFFF;
870 NEONLdStInsn |= 0x04000000;
871 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
873 if (result != MCDisassembler::Fail) {
875 Check(result, AddThumbPredicate(MI));
880 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
882 uint32_t NEONDataInsn = insn32;
883 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
884 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
885 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
886 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
888 if (result != MCDisassembler::Fail) {
890 Check(result, AddThumbPredicate(MI));
896 return MCDisassembler::Fail;
900 extern "C" void LLVMInitializeARMDisassembler() {
901 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
902 createARMDisassembler);
903 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
904 createThumbDisassembler);
907 static const uint16_t GPRDecoderTable[] = {
908 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
909 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
910 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
911 ARM::R12, ARM::SP, ARM::LR, ARM::PC
914 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
915 uint64_t Address, const void *Decoder) {
917 return MCDisassembler::Fail;
919 unsigned Register = GPRDecoderTable[RegNo];
920 Inst.addOperand(MCOperand::CreateReg(Register));
921 return MCDisassembler::Success;
925 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
926 uint64_t Address, const void *Decoder) {
927 DecodeStatus S = MCDisassembler::Success;
930 S = MCDisassembler::SoftFail;
932 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
937 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
938 uint64_t Address, const void *Decoder) {
940 return MCDisassembler::Fail;
941 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
944 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
945 uint64_t Address, const void *Decoder) {
946 unsigned Register = 0;
967 return MCDisassembler::Fail;
970 Inst.addOperand(MCOperand::CreateReg(Register));
971 return MCDisassembler::Success;
974 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
975 uint64_t Address, const void *Decoder) {
976 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
977 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
980 static const uint16_t SPRDecoderTable[] = {
981 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
982 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
983 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
984 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988 ARM::S28, ARM::S29, ARM::S30, ARM::S31
991 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
992 uint64_t Address, const void *Decoder) {
994 return MCDisassembler::Fail;
996 unsigned Register = SPRDecoderTable[RegNo];
997 Inst.addOperand(MCOperand::CreateReg(Register));
998 return MCDisassembler::Success;
1001 static const uint16_t DPRDecoderTable[] = {
1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1012 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1013 uint64_t Address, const void *Decoder) {
1015 return MCDisassembler::Fail;
1017 unsigned Register = DPRDecoderTable[RegNo];
1018 Inst.addOperand(MCOperand::CreateReg(Register));
1019 return MCDisassembler::Success;
1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1023 uint64_t Address, const void *Decoder) {
1025 return MCDisassembler::Fail;
1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1031 uint64_t Address, const void *Decoder) {
1033 return MCDisassembler::Fail;
1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1037 static const uint16_t QPRDecoderTable[] = {
1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1046 uint64_t Address, const void *Decoder) {
1048 return MCDisassembler::Fail;
1051 unsigned Register = QPRDecoderTable[RegNo];
1052 Inst.addOperand(MCOperand::CreateReg(Register));
1053 return MCDisassembler::Success;
1056 static const uint16_t DPairDecoderTable[] = {
1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1066 uint64_t Address, const void *Decoder) {
1068 return MCDisassembler::Fail;
1070 unsigned Register = DPairDecoderTable[RegNo];
1071 Inst.addOperand(MCOperand::CreateReg(Register));
1072 return MCDisassembler::Success;
1075 static const uint16_t DPairSpacedDecoderTable[] = {
1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1089 const void *Decoder) {
1091 return MCDisassembler::Fail;
1093 unsigned Register = DPairSpacedDecoderTable[RegNo];
1094 Inst.addOperand(MCOperand::CreateReg(Register));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1099 uint64_t Address, const void *Decoder) {
1100 if (Val == 0xF) return MCDisassembler::Fail;
1101 // AL predicate is not allowed on Thumb1 branches.
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1103 return MCDisassembler::Fail;
1104 Inst.addOperand(MCOperand::CreateImm(Val));
1105 if (Val == ARMCC::AL) {
1106 Inst.addOperand(MCOperand::CreateReg(0));
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1109 return MCDisassembler::Success;
1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1113 uint64_t Address, const void *Decoder) {
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1117 Inst.addOperand(MCOperand::CreateReg(0));
1118 return MCDisassembler::Success;
1121 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1122 uint64_t Address, const void *Decoder) {
1123 uint32_t imm = Val & 0xFF;
1124 uint32_t rot = (Val & 0xF00) >> 7;
1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1126 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1127 return MCDisassembler::Success;
1130 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1131 uint64_t Address, const void *Decoder) {
1132 DecodeStatus S = MCDisassembler::Success;
1134 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1135 unsigned type = fieldFromInstruction(Val, 5, 2);
1136 unsigned imm = fieldFromInstruction(Val, 7, 5);
1138 // Register-immediate
1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1140 return MCDisassembler::Fail;
1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1145 Shift = ARM_AM::lsl;
1148 Shift = ARM_AM::lsr;
1151 Shift = ARM_AM::asr;
1154 Shift = ARM_AM::ror;
1158 if (Shift == ARM_AM::ror && imm == 0)
1159 Shift = ARM_AM::rrx;
1161 unsigned Op = Shift | (imm << 3);
1162 Inst.addOperand(MCOperand::CreateImm(Op));
1167 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1168 uint64_t Address, const void *Decoder) {
1169 DecodeStatus S = MCDisassembler::Success;
1171 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1172 unsigned type = fieldFromInstruction(Val, 5, 2);
1173 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1175 // Register-register
1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1177 return MCDisassembler::Fail;
1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1179 return MCDisassembler::Fail;
1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1184 Shift = ARM_AM::lsl;
1187 Shift = ARM_AM::lsr;
1190 Shift = ARM_AM::asr;
1193 Shift = ARM_AM::ror;
1197 Inst.addOperand(MCOperand::CreateImm(Shift));
1202 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1203 uint64_t Address, const void *Decoder) {
1204 DecodeStatus S = MCDisassembler::Success;
1206 bool writebackLoad = false;
1207 unsigned writebackReg = 0;
1208 switch (Inst.getOpcode()) {
1211 case ARM::LDMIA_UPD:
1212 case ARM::LDMDB_UPD:
1213 case ARM::LDMIB_UPD:
1214 case ARM::LDMDA_UPD:
1215 case ARM::t2LDMIA_UPD:
1216 case ARM::t2LDMDB_UPD:
1217 writebackLoad = true;
1218 writebackReg = Inst.getOperand(0).getReg();
1222 // Empty register lists are not allowed.
1223 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1224 for (unsigned i = 0; i < 16; ++i) {
1225 if (Val & (1 << i)) {
1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1227 return MCDisassembler::Fail;
1228 // Writeback not allowed if Rn is in the target list.
1229 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1230 Check(S, MCDisassembler::SoftFail);
1237 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1238 uint64_t Address, const void *Decoder) {
1239 DecodeStatus S = MCDisassembler::Success;
1241 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1242 unsigned regs = fieldFromInstruction(Val, 0, 8);
1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1245 return MCDisassembler::Fail;
1246 for (unsigned i = 0; i < (regs - 1); ++i) {
1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1248 return MCDisassembler::Fail;
1254 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1255 uint64_t Address, const void *Decoder) {
1256 DecodeStatus S = MCDisassembler::Success;
1258 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1259 unsigned regs = fieldFromInstruction(Val, 0, 8);
1263 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1264 return MCDisassembler::Fail;
1265 for (unsigned i = 0; i < (regs - 1); ++i) {
1266 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1267 return MCDisassembler::Fail;
1273 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1274 uint64_t Address, const void *Decoder) {
1275 // This operand encodes a mask of contiguous zeros between a specified MSB
1276 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1277 // the mask of all bits LSB-and-lower, and then xor them to create
1278 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1279 // create the final mask.
1280 unsigned msb = fieldFromInstruction(Val, 5, 5);
1281 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1283 DecodeStatus S = MCDisassembler::Success;
1285 Check(S, MCDisassembler::SoftFail);
1286 // The check above will cause the warning for the "potentially undefined
1287 // instruction encoding" but we can't build a bad MCOperand value here
1288 // with a lsb > msb or else printing the MCInst will cause a crash.
1292 uint32_t msb_mask = 0xFFFFFFFF;
1293 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1294 uint32_t lsb_mask = (1U << lsb) - 1;
1296 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1300 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1301 uint64_t Address, const void *Decoder) {
1302 DecodeStatus S = MCDisassembler::Success;
1304 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1305 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1306 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1307 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1308 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1309 unsigned U = fieldFromInstruction(Insn, 23, 1);
1311 switch (Inst.getOpcode()) {
1312 case ARM::LDC_OFFSET:
1315 case ARM::LDC_OPTION:
1316 case ARM::LDCL_OFFSET:
1318 case ARM::LDCL_POST:
1319 case ARM::LDCL_OPTION:
1320 case ARM::STC_OFFSET:
1323 case ARM::STC_OPTION:
1324 case ARM::STCL_OFFSET:
1326 case ARM::STCL_POST:
1327 case ARM::STCL_OPTION:
1328 case ARM::t2LDC_OFFSET:
1329 case ARM::t2LDC_PRE:
1330 case ARM::t2LDC_POST:
1331 case ARM::t2LDC_OPTION:
1332 case ARM::t2LDCL_OFFSET:
1333 case ARM::t2LDCL_PRE:
1334 case ARM::t2LDCL_POST:
1335 case ARM::t2LDCL_OPTION:
1336 case ARM::t2STC_OFFSET:
1337 case ARM::t2STC_PRE:
1338 case ARM::t2STC_POST:
1339 case ARM::t2STC_OPTION:
1340 case ARM::t2STCL_OFFSET:
1341 case ARM::t2STCL_PRE:
1342 case ARM::t2STCL_POST:
1343 case ARM::t2STCL_OPTION:
1344 if (coproc == 0xA || coproc == 0xB)
1345 return MCDisassembler::Fail;
1351 Inst.addOperand(MCOperand::CreateImm(coproc));
1352 Inst.addOperand(MCOperand::CreateImm(CRd));
1353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1354 return MCDisassembler::Fail;
1356 switch (Inst.getOpcode()) {
1357 case ARM::t2LDC2_OFFSET:
1358 case ARM::t2LDC2L_OFFSET:
1359 case ARM::t2LDC2_PRE:
1360 case ARM::t2LDC2L_PRE:
1361 case ARM::t2STC2_OFFSET:
1362 case ARM::t2STC2L_OFFSET:
1363 case ARM::t2STC2_PRE:
1364 case ARM::t2STC2L_PRE:
1365 case ARM::LDC2_OFFSET:
1366 case ARM::LDC2L_OFFSET:
1368 case ARM::LDC2L_PRE:
1369 case ARM::STC2_OFFSET:
1370 case ARM::STC2L_OFFSET:
1372 case ARM::STC2L_PRE:
1373 case ARM::t2LDC_OFFSET:
1374 case ARM::t2LDCL_OFFSET:
1375 case ARM::t2LDC_PRE:
1376 case ARM::t2LDCL_PRE:
1377 case ARM::t2STC_OFFSET:
1378 case ARM::t2STCL_OFFSET:
1379 case ARM::t2STC_PRE:
1380 case ARM::t2STCL_PRE:
1381 case ARM::LDC_OFFSET:
1382 case ARM::LDCL_OFFSET:
1385 case ARM::STC_OFFSET:
1386 case ARM::STCL_OFFSET:
1389 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1390 Inst.addOperand(MCOperand::CreateImm(imm));
1392 case ARM::t2LDC2_POST:
1393 case ARM::t2LDC2L_POST:
1394 case ARM::t2STC2_POST:
1395 case ARM::t2STC2L_POST:
1396 case ARM::LDC2_POST:
1397 case ARM::LDC2L_POST:
1398 case ARM::STC2_POST:
1399 case ARM::STC2L_POST:
1400 case ARM::t2LDC_POST:
1401 case ARM::t2LDCL_POST:
1402 case ARM::t2STC_POST:
1403 case ARM::t2STCL_POST:
1405 case ARM::LDCL_POST:
1407 case ARM::STCL_POST:
1411 // The 'option' variant doesn't encode 'U' in the immediate since
1412 // the immediate is unsigned [0,255].
1413 Inst.addOperand(MCOperand::CreateImm(imm));
1417 switch (Inst.getOpcode()) {
1418 case ARM::LDC_OFFSET:
1421 case ARM::LDC_OPTION:
1422 case ARM::LDCL_OFFSET:
1424 case ARM::LDCL_POST:
1425 case ARM::LDCL_OPTION:
1426 case ARM::STC_OFFSET:
1429 case ARM::STC_OPTION:
1430 case ARM::STCL_OFFSET:
1432 case ARM::STCL_POST:
1433 case ARM::STCL_OPTION:
1434 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1435 return MCDisassembler::Fail;
1445 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1446 uint64_t Address, const void *Decoder) {
1447 DecodeStatus S = MCDisassembler::Success;
1449 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1450 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1451 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1452 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1453 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1454 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1455 unsigned P = fieldFromInstruction(Insn, 24, 1);
1456 unsigned W = fieldFromInstruction(Insn, 21, 1);
1458 // On stores, the writeback operand precedes Rt.
1459 switch (Inst.getOpcode()) {
1460 case ARM::STR_POST_IMM:
1461 case ARM::STR_POST_REG:
1462 case ARM::STRB_POST_IMM:
1463 case ARM::STRB_POST_REG:
1464 case ARM::STRT_POST_REG:
1465 case ARM::STRT_POST_IMM:
1466 case ARM::STRBT_POST_REG:
1467 case ARM::STRBT_POST_IMM:
1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1469 return MCDisassembler::Fail;
1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1476 return MCDisassembler::Fail;
1478 // On loads, the writeback operand comes after Rt.
1479 switch (Inst.getOpcode()) {
1480 case ARM::LDR_POST_IMM:
1481 case ARM::LDR_POST_REG:
1482 case ARM::LDRB_POST_IMM:
1483 case ARM::LDRB_POST_REG:
1484 case ARM::LDRBT_POST_REG:
1485 case ARM::LDRBT_POST_IMM:
1486 case ARM::LDRT_POST_REG:
1487 case ARM::LDRT_POST_IMM:
1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1489 return MCDisassembler::Fail;
1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1496 return MCDisassembler::Fail;
1498 ARM_AM::AddrOpc Op = ARM_AM::add;
1499 if (!fieldFromInstruction(Insn, 23, 1))
1502 bool writeback = (P == 0) || (W == 1);
1503 unsigned idx_mode = 0;
1505 idx_mode = ARMII::IndexModePre;
1506 else if (!P && writeback)
1507 idx_mode = ARMII::IndexModePost;
1509 if (writeback && (Rn == 15 || Rn == Rt))
1510 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1513 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1514 return MCDisassembler::Fail;
1515 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1516 switch( fieldFromInstruction(Insn, 5, 2)) {
1530 return MCDisassembler::Fail;
1532 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1533 if (Opc == ARM_AM::ror && amt == 0)
1535 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1537 Inst.addOperand(MCOperand::CreateImm(imm));
1539 Inst.addOperand(MCOperand::CreateReg(0));
1540 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1541 Inst.addOperand(MCOperand::CreateImm(tmp));
1544 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1545 return MCDisassembler::Fail;
1550 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1551 uint64_t Address, const void *Decoder) {
1552 DecodeStatus S = MCDisassembler::Success;
1554 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1555 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1556 unsigned type = fieldFromInstruction(Val, 5, 2);
1557 unsigned imm = fieldFromInstruction(Val, 7, 5);
1558 unsigned U = fieldFromInstruction(Val, 12, 1);
1560 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1576 if (ShOp == ARM_AM::ror && imm == 0)
1579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1580 return MCDisassembler::Fail;
1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1582 return MCDisassembler::Fail;
1585 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1587 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1588 Inst.addOperand(MCOperand::CreateImm(shift));
1594 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1595 uint64_t Address, const void *Decoder) {
1596 DecodeStatus S = MCDisassembler::Success;
1598 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1599 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1600 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1601 unsigned type = fieldFromInstruction(Insn, 22, 1);
1602 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1603 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1604 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1605 unsigned W = fieldFromInstruction(Insn, 21, 1);
1606 unsigned P = fieldFromInstruction(Insn, 24, 1);
1607 unsigned Rt2 = Rt + 1;
1609 bool writeback = (W == 1) | (P == 0);
1611 // For {LD,ST}RD, Rt must be even, else undefined.
1612 switch (Inst.getOpcode()) {
1615 case ARM::STRD_POST:
1618 case ARM::LDRD_POST:
1619 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1624 switch (Inst.getOpcode()) {
1627 case ARM::STRD_POST:
1628 if (P == 0 && W == 1)
1629 S = MCDisassembler::SoftFail;
1631 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1632 S = MCDisassembler::SoftFail;
1633 if (type && Rm == 15)
1634 S = MCDisassembler::SoftFail;
1636 S = MCDisassembler::SoftFail;
1637 if (!type && fieldFromInstruction(Insn, 8, 4))
1638 S = MCDisassembler::SoftFail;
1642 case ARM::STRH_POST:
1644 S = MCDisassembler::SoftFail;
1645 if (writeback && (Rn == 15 || Rn == Rt))
1646 S = MCDisassembler::SoftFail;
1647 if (!type && Rm == 15)
1648 S = MCDisassembler::SoftFail;
1652 case ARM::LDRD_POST:
1653 if (type && Rn == 15){
1655 S = MCDisassembler::SoftFail;
1658 if (P == 0 && W == 1)
1659 S = MCDisassembler::SoftFail;
1660 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1661 S = MCDisassembler::SoftFail;
1662 if (!type && writeback && Rn == 15)
1663 S = MCDisassembler::SoftFail;
1664 if (writeback && (Rn == Rt || Rn == Rt2))
1665 S = MCDisassembler::SoftFail;
1669 case ARM::LDRH_POST:
1670 if (type && Rn == 15){
1672 S = MCDisassembler::SoftFail;
1676 S = MCDisassembler::SoftFail;
1677 if (!type && Rm == 15)
1678 S = MCDisassembler::SoftFail;
1679 if (!type && writeback && (Rn == 15 || Rn == Rt))
1680 S = MCDisassembler::SoftFail;
1683 case ARM::LDRSH_PRE:
1684 case ARM::LDRSH_POST:
1686 case ARM::LDRSB_PRE:
1687 case ARM::LDRSB_POST:
1688 if (type && Rn == 15){
1690 S = MCDisassembler::SoftFail;
1693 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1694 S = MCDisassembler::SoftFail;
1695 if (!type && (Rt == 15 || Rm == 15))
1696 S = MCDisassembler::SoftFail;
1697 if (!type && writeback && (Rn == 15 || Rn == Rt))
1698 S = MCDisassembler::SoftFail;
1704 if (writeback) { // Writeback
1706 U |= ARMII::IndexModePre << 9;
1708 U |= ARMII::IndexModePost << 9;
1710 // On stores, the writeback operand precedes Rt.
1711 switch (Inst.getOpcode()) {
1714 case ARM::STRD_POST:
1717 case ARM::STRH_POST:
1718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1719 return MCDisassembler::Fail;
1726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1727 return MCDisassembler::Fail;
1728 switch (Inst.getOpcode()) {
1731 case ARM::STRD_POST:
1734 case ARM::LDRD_POST:
1735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1736 return MCDisassembler::Fail;
1743 // On loads, the writeback operand comes after Rt.
1744 switch (Inst.getOpcode()) {
1747 case ARM::LDRD_POST:
1750 case ARM::LDRH_POST:
1752 case ARM::LDRSH_PRE:
1753 case ARM::LDRSH_POST:
1755 case ARM::LDRSB_PRE:
1756 case ARM::LDRSB_POST:
1759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1760 return MCDisassembler::Fail;
1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1768 return MCDisassembler::Fail;
1771 Inst.addOperand(MCOperand::CreateReg(0));
1772 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1775 return MCDisassembler::Fail;
1776 Inst.addOperand(MCOperand::CreateImm(U));
1779 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1780 return MCDisassembler::Fail;
1785 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1786 uint64_t Address, const void *Decoder) {
1787 DecodeStatus S = MCDisassembler::Success;
1789 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1790 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1807 Inst.addOperand(MCOperand::CreateImm(mode));
1808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1809 return MCDisassembler::Fail;
1814 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1816 uint64_t Address, const void *Decoder) {
1817 DecodeStatus S = MCDisassembler::Success;
1819 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1820 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1821 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1824 switch (Inst.getOpcode()) {
1826 Inst.setOpcode(ARM::RFEDA);
1828 case ARM::LDMDA_UPD:
1829 Inst.setOpcode(ARM::RFEDA_UPD);
1832 Inst.setOpcode(ARM::RFEDB);
1834 case ARM::LDMDB_UPD:
1835 Inst.setOpcode(ARM::RFEDB_UPD);
1838 Inst.setOpcode(ARM::RFEIA);
1840 case ARM::LDMIA_UPD:
1841 Inst.setOpcode(ARM::RFEIA_UPD);
1844 Inst.setOpcode(ARM::RFEIB);
1846 case ARM::LDMIB_UPD:
1847 Inst.setOpcode(ARM::RFEIB_UPD);
1850 Inst.setOpcode(ARM::SRSDA);
1852 case ARM::STMDA_UPD:
1853 Inst.setOpcode(ARM::SRSDA_UPD);
1856 Inst.setOpcode(ARM::SRSDB);
1858 case ARM::STMDB_UPD:
1859 Inst.setOpcode(ARM::SRSDB_UPD);
1862 Inst.setOpcode(ARM::SRSIA);
1864 case ARM::STMIA_UPD:
1865 Inst.setOpcode(ARM::SRSIA_UPD);
1868 Inst.setOpcode(ARM::SRSIB);
1870 case ARM::STMIB_UPD:
1871 Inst.setOpcode(ARM::SRSIB_UPD);
1874 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1877 // For stores (which become SRS's, the only operand is the mode.
1878 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1880 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1884 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1888 return MCDisassembler::Fail;
1889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1890 return MCDisassembler::Fail; // Tied
1891 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1892 return MCDisassembler::Fail;
1893 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1894 return MCDisassembler::Fail;
1899 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1900 uint64_t Address, const void *Decoder) {
1901 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1902 unsigned M = fieldFromInstruction(Insn, 17, 1);
1903 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1904 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1906 DecodeStatus S = MCDisassembler::Success;
1908 // imod == '01' --> UNPREDICTABLE
1909 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1910 // return failure here. The '01' imod value is unprintable, so there's
1911 // nothing useful we could do even if we returned UNPREDICTABLE.
1913 if (imod == 1) return MCDisassembler::Fail;
1916 Inst.setOpcode(ARM::CPS3p);
1917 Inst.addOperand(MCOperand::CreateImm(imod));
1918 Inst.addOperand(MCOperand::CreateImm(iflags));
1919 Inst.addOperand(MCOperand::CreateImm(mode));
1920 } else if (imod && !M) {
1921 Inst.setOpcode(ARM::CPS2p);
1922 Inst.addOperand(MCOperand::CreateImm(imod));
1923 Inst.addOperand(MCOperand::CreateImm(iflags));
1924 if (mode) S = MCDisassembler::SoftFail;
1925 } else if (!imod && M) {
1926 Inst.setOpcode(ARM::CPS1p);
1927 Inst.addOperand(MCOperand::CreateImm(mode));
1928 if (iflags) S = MCDisassembler::SoftFail;
1930 // imod == '00' && M == '0' --> UNPREDICTABLE
1931 Inst.setOpcode(ARM::CPS1p);
1932 Inst.addOperand(MCOperand::CreateImm(mode));
1933 S = MCDisassembler::SoftFail;
1939 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1940 uint64_t Address, const void *Decoder) {
1941 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1942 unsigned M = fieldFromInstruction(Insn, 8, 1);
1943 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1944 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1946 DecodeStatus S = MCDisassembler::Success;
1948 // imod == '01' --> UNPREDICTABLE
1949 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1950 // return failure here. The '01' imod value is unprintable, so there's
1951 // nothing useful we could do even if we returned UNPREDICTABLE.
1953 if (imod == 1) return MCDisassembler::Fail;
1956 Inst.setOpcode(ARM::t2CPS3p);
1957 Inst.addOperand(MCOperand::CreateImm(imod));
1958 Inst.addOperand(MCOperand::CreateImm(iflags));
1959 Inst.addOperand(MCOperand::CreateImm(mode));
1960 } else if (imod && !M) {
1961 Inst.setOpcode(ARM::t2CPS2p);
1962 Inst.addOperand(MCOperand::CreateImm(imod));
1963 Inst.addOperand(MCOperand::CreateImm(iflags));
1964 if (mode) S = MCDisassembler::SoftFail;
1965 } else if (!imod && M) {
1966 Inst.setOpcode(ARM::t2CPS1p);
1967 Inst.addOperand(MCOperand::CreateImm(mode));
1968 if (iflags) S = MCDisassembler::SoftFail;
1970 // imod == '00' && M == '0' --> UNPREDICTABLE
1971 Inst.setOpcode(ARM::t2CPS1p);
1972 Inst.addOperand(MCOperand::CreateImm(mode));
1973 S = MCDisassembler::SoftFail;
1979 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1980 uint64_t Address, const void *Decoder) {
1981 DecodeStatus S = MCDisassembler::Success;
1983 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
1986 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1987 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1988 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1989 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
1991 if (Inst.getOpcode() == ARM::t2MOVTi16)
1992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1993 return MCDisassembler::Fail;
1994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1995 return MCDisassembler::Fail;
1997 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1998 Inst.addOperand(MCOperand::CreateImm(imm));
2003 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2004 uint64_t Address, const void *Decoder) {
2005 DecodeStatus S = MCDisassembler::Success;
2007 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2008 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2011 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2012 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2014 if (Inst.getOpcode() == ARM::MOVTi16)
2015 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2016 return MCDisassembler::Fail;
2017 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2018 return MCDisassembler::Fail;
2020 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2021 Inst.addOperand(MCOperand::CreateImm(imm));
2023 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2024 return MCDisassembler::Fail;
2029 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2030 uint64_t Address, const void *Decoder) {
2031 DecodeStatus S = MCDisassembler::Success;
2033 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2034 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2035 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2036 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2037 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2040 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2043 return MCDisassembler::Fail;
2044 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2045 return MCDisassembler::Fail;
2046 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2047 return MCDisassembler::Fail;
2048 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2049 return MCDisassembler::Fail;
2051 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2052 return MCDisassembler::Fail;
2057 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2058 uint64_t Address, const void *Decoder) {
2059 DecodeStatus S = MCDisassembler::Success;
2061 unsigned add = fieldFromInstruction(Val, 12, 1);
2062 unsigned imm = fieldFromInstruction(Val, 0, 12);
2063 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2066 return MCDisassembler::Fail;
2068 if (!add) imm *= -1;
2069 if (imm == 0 && !add) imm = INT32_MIN;
2070 Inst.addOperand(MCOperand::CreateImm(imm));
2072 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2077 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2078 uint64_t Address, const void *Decoder) {
2079 DecodeStatus S = MCDisassembler::Success;
2081 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2082 unsigned U = fieldFromInstruction(Val, 8, 1);
2083 unsigned imm = fieldFromInstruction(Val, 0, 8);
2085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2086 return MCDisassembler::Fail;
2089 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2091 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2096 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2097 uint64_t Address, const void *Decoder) {
2098 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2102 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2103 uint64_t Address, const void *Decoder) {
2104 DecodeStatus Status = MCDisassembler::Success;
2106 // Note the J1 and J2 values are from the encoded instruction. So here
2107 // change them to I1 and I2 values via as documented:
2108 // I1 = NOT(J1 EOR S);
2109 // I2 = NOT(J2 EOR S);
2110 // and build the imm32 with one trailing zero as documented:
2111 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2112 unsigned S = fieldFromInstruction(Insn, 26, 1);
2113 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2114 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2115 unsigned I1 = !(J1 ^ S);
2116 unsigned I2 = !(J2 ^ S);
2117 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2118 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2119 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2120 int imm32 = SignExtend32<24>(tmp << 1);
2121 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2122 true, 4, Inst, Decoder))
2123 Inst.addOperand(MCOperand::CreateImm(imm32));
2129 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2130 uint64_t Address, const void *Decoder) {
2131 DecodeStatus S = MCDisassembler::Success;
2133 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2134 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2137 Inst.setOpcode(ARM::BLXi);
2138 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2139 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2140 true, 4, Inst, Decoder))
2141 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2145 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2146 true, 4, Inst, Decoder))
2147 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2148 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2149 return MCDisassembler::Fail;
2155 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2156 uint64_t Address, const void *Decoder) {
2157 DecodeStatus S = MCDisassembler::Success;
2159 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2160 unsigned align = fieldFromInstruction(Val, 4, 2);
2162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2163 return MCDisassembler::Fail;
2165 Inst.addOperand(MCOperand::CreateImm(0));
2167 Inst.addOperand(MCOperand::CreateImm(4 << align));
2172 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2173 uint64_t Address, const void *Decoder) {
2174 DecodeStatus S = MCDisassembler::Success;
2176 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2177 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2178 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2179 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2180 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2181 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2183 // First output register
2184 switch (Inst.getOpcode()) {
2185 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2186 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2187 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2188 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2189 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2190 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2191 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2192 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2193 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2194 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2195 return MCDisassembler::Fail;
2200 case ARM::VLD2b16wb_fixed:
2201 case ARM::VLD2b16wb_register:
2202 case ARM::VLD2b32wb_fixed:
2203 case ARM::VLD2b32wb_register:
2204 case ARM::VLD2b8wb_fixed:
2205 case ARM::VLD2b8wb_register:
2206 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2207 return MCDisassembler::Fail;
2210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2211 return MCDisassembler::Fail;
2214 // Second output register
2215 switch (Inst.getOpcode()) {
2219 case ARM::VLD3d8_UPD:
2220 case ARM::VLD3d16_UPD:
2221 case ARM::VLD3d32_UPD:
2225 case ARM::VLD4d8_UPD:
2226 case ARM::VLD4d16_UPD:
2227 case ARM::VLD4d32_UPD:
2228 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2229 return MCDisassembler::Fail;
2234 case ARM::VLD3q8_UPD:
2235 case ARM::VLD3q16_UPD:
2236 case ARM::VLD3q32_UPD:
2240 case ARM::VLD4q8_UPD:
2241 case ARM::VLD4q16_UPD:
2242 case ARM::VLD4q32_UPD:
2243 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2244 return MCDisassembler::Fail;
2249 // Third output register
2250 switch(Inst.getOpcode()) {
2254 case ARM::VLD3d8_UPD:
2255 case ARM::VLD3d16_UPD:
2256 case ARM::VLD3d32_UPD:
2260 case ARM::VLD4d8_UPD:
2261 case ARM::VLD4d16_UPD:
2262 case ARM::VLD4d32_UPD:
2263 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2264 return MCDisassembler::Fail;
2269 case ARM::VLD3q8_UPD:
2270 case ARM::VLD3q16_UPD:
2271 case ARM::VLD3q32_UPD:
2275 case ARM::VLD4q8_UPD:
2276 case ARM::VLD4q16_UPD:
2277 case ARM::VLD4q32_UPD:
2278 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2279 return MCDisassembler::Fail;
2285 // Fourth output register
2286 switch (Inst.getOpcode()) {
2290 case ARM::VLD4d8_UPD:
2291 case ARM::VLD4d16_UPD:
2292 case ARM::VLD4d32_UPD:
2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2294 return MCDisassembler::Fail;
2299 case ARM::VLD4q8_UPD:
2300 case ARM::VLD4q16_UPD:
2301 case ARM::VLD4q32_UPD:
2302 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2303 return MCDisassembler::Fail;
2309 // Writeback operand
2310 switch (Inst.getOpcode()) {
2311 case ARM::VLD1d8wb_fixed:
2312 case ARM::VLD1d16wb_fixed:
2313 case ARM::VLD1d32wb_fixed:
2314 case ARM::VLD1d64wb_fixed:
2315 case ARM::VLD1d8wb_register:
2316 case ARM::VLD1d16wb_register:
2317 case ARM::VLD1d32wb_register:
2318 case ARM::VLD1d64wb_register:
2319 case ARM::VLD1q8wb_fixed:
2320 case ARM::VLD1q16wb_fixed:
2321 case ARM::VLD1q32wb_fixed:
2322 case ARM::VLD1q64wb_fixed:
2323 case ARM::VLD1q8wb_register:
2324 case ARM::VLD1q16wb_register:
2325 case ARM::VLD1q32wb_register:
2326 case ARM::VLD1q64wb_register:
2327 case ARM::VLD1d8Twb_fixed:
2328 case ARM::VLD1d8Twb_register:
2329 case ARM::VLD1d16Twb_fixed:
2330 case ARM::VLD1d16Twb_register:
2331 case ARM::VLD1d32Twb_fixed:
2332 case ARM::VLD1d32Twb_register:
2333 case ARM::VLD1d64Twb_fixed:
2334 case ARM::VLD1d64Twb_register:
2335 case ARM::VLD1d8Qwb_fixed:
2336 case ARM::VLD1d8Qwb_register:
2337 case ARM::VLD1d16Qwb_fixed:
2338 case ARM::VLD1d16Qwb_register:
2339 case ARM::VLD1d32Qwb_fixed:
2340 case ARM::VLD1d32Qwb_register:
2341 case ARM::VLD1d64Qwb_fixed:
2342 case ARM::VLD1d64Qwb_register:
2343 case ARM::VLD2d8wb_fixed:
2344 case ARM::VLD2d16wb_fixed:
2345 case ARM::VLD2d32wb_fixed:
2346 case ARM::VLD2q8wb_fixed:
2347 case ARM::VLD2q16wb_fixed:
2348 case ARM::VLD2q32wb_fixed:
2349 case ARM::VLD2d8wb_register:
2350 case ARM::VLD2d16wb_register:
2351 case ARM::VLD2d32wb_register:
2352 case ARM::VLD2q8wb_register:
2353 case ARM::VLD2q16wb_register:
2354 case ARM::VLD2q32wb_register:
2355 case ARM::VLD2b8wb_fixed:
2356 case ARM::VLD2b16wb_fixed:
2357 case ARM::VLD2b32wb_fixed:
2358 case ARM::VLD2b8wb_register:
2359 case ARM::VLD2b16wb_register:
2360 case ARM::VLD2b32wb_register:
2361 Inst.addOperand(MCOperand::CreateImm(0));
2363 case ARM::VLD3d8_UPD:
2364 case ARM::VLD3d16_UPD:
2365 case ARM::VLD3d32_UPD:
2366 case ARM::VLD3q8_UPD:
2367 case ARM::VLD3q16_UPD:
2368 case ARM::VLD3q32_UPD:
2369 case ARM::VLD4d8_UPD:
2370 case ARM::VLD4d16_UPD:
2371 case ARM::VLD4d32_UPD:
2372 case ARM::VLD4q8_UPD:
2373 case ARM::VLD4q16_UPD:
2374 case ARM::VLD4q32_UPD:
2375 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2376 return MCDisassembler::Fail;
2382 // AddrMode6 Base (register+alignment)
2383 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2384 return MCDisassembler::Fail;
2386 // AddrMode6 Offset (register)
2387 switch (Inst.getOpcode()) {
2389 // The below have been updated to have explicit am6offset split
2390 // between fixed and register offset. For those instructions not
2391 // yet updated, we need to add an additional reg0 operand for the
2394 // The fixed offset encodes as Rm == 0xd, so we check for that.
2396 Inst.addOperand(MCOperand::CreateReg(0));
2399 // Fall through to handle the register offset variant.
2400 case ARM::VLD1d8wb_fixed:
2401 case ARM::VLD1d16wb_fixed:
2402 case ARM::VLD1d32wb_fixed:
2403 case ARM::VLD1d64wb_fixed:
2404 case ARM::VLD1d8Twb_fixed:
2405 case ARM::VLD1d16Twb_fixed:
2406 case ARM::VLD1d32Twb_fixed:
2407 case ARM::VLD1d64Twb_fixed:
2408 case ARM::VLD1d8Qwb_fixed:
2409 case ARM::VLD1d16Qwb_fixed:
2410 case ARM::VLD1d32Qwb_fixed:
2411 case ARM::VLD1d64Qwb_fixed:
2412 case ARM::VLD1d8wb_register:
2413 case ARM::VLD1d16wb_register:
2414 case ARM::VLD1d32wb_register:
2415 case ARM::VLD1d64wb_register:
2416 case ARM::VLD1q8wb_fixed:
2417 case ARM::VLD1q16wb_fixed:
2418 case ARM::VLD1q32wb_fixed:
2419 case ARM::VLD1q64wb_fixed:
2420 case ARM::VLD1q8wb_register:
2421 case ARM::VLD1q16wb_register:
2422 case ARM::VLD1q32wb_register:
2423 case ARM::VLD1q64wb_register:
2424 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2425 // variant encodes Rm == 0xf. Anything else is a register offset post-
2426 // increment and we need to add the register operand to the instruction.
2427 if (Rm != 0xD && Rm != 0xF &&
2428 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2429 return MCDisassembler::Fail;
2431 case ARM::VLD2d8wb_fixed:
2432 case ARM::VLD2d16wb_fixed:
2433 case ARM::VLD2d32wb_fixed:
2434 case ARM::VLD2b8wb_fixed:
2435 case ARM::VLD2b16wb_fixed:
2436 case ARM::VLD2b32wb_fixed:
2437 case ARM::VLD2q8wb_fixed:
2438 case ARM::VLD2q16wb_fixed:
2439 case ARM::VLD2q32wb_fixed:
2446 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2447 uint64_t Address, const void *Decoder) {
2448 DecodeStatus S = MCDisassembler::Success;
2450 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2452 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2453 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2454 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2455 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2457 // Writeback Operand
2458 switch (Inst.getOpcode()) {
2459 case ARM::VST1d8wb_fixed:
2460 case ARM::VST1d16wb_fixed:
2461 case ARM::VST1d32wb_fixed:
2462 case ARM::VST1d64wb_fixed:
2463 case ARM::VST1d8wb_register:
2464 case ARM::VST1d16wb_register:
2465 case ARM::VST1d32wb_register:
2466 case ARM::VST1d64wb_register:
2467 case ARM::VST1q8wb_fixed:
2468 case ARM::VST1q16wb_fixed:
2469 case ARM::VST1q32wb_fixed:
2470 case ARM::VST1q64wb_fixed:
2471 case ARM::VST1q8wb_register:
2472 case ARM::VST1q16wb_register:
2473 case ARM::VST1q32wb_register:
2474 case ARM::VST1q64wb_register:
2475 case ARM::VST1d8Twb_fixed:
2476 case ARM::VST1d16Twb_fixed:
2477 case ARM::VST1d32Twb_fixed:
2478 case ARM::VST1d64Twb_fixed:
2479 case ARM::VST1d8Twb_register:
2480 case ARM::VST1d16Twb_register:
2481 case ARM::VST1d32Twb_register:
2482 case ARM::VST1d64Twb_register:
2483 case ARM::VST1d8Qwb_fixed:
2484 case ARM::VST1d16Qwb_fixed:
2485 case ARM::VST1d32Qwb_fixed:
2486 case ARM::VST1d64Qwb_fixed:
2487 case ARM::VST1d8Qwb_register:
2488 case ARM::VST1d16Qwb_register:
2489 case ARM::VST1d32Qwb_register:
2490 case ARM::VST1d64Qwb_register:
2491 case ARM::VST2d8wb_fixed:
2492 case ARM::VST2d16wb_fixed:
2493 case ARM::VST2d32wb_fixed:
2494 case ARM::VST2d8wb_register:
2495 case ARM::VST2d16wb_register:
2496 case ARM::VST2d32wb_register:
2497 case ARM::VST2q8wb_fixed:
2498 case ARM::VST2q16wb_fixed:
2499 case ARM::VST2q32wb_fixed:
2500 case ARM::VST2q8wb_register:
2501 case ARM::VST2q16wb_register:
2502 case ARM::VST2q32wb_register:
2503 case ARM::VST2b8wb_fixed:
2504 case ARM::VST2b16wb_fixed:
2505 case ARM::VST2b32wb_fixed:
2506 case ARM::VST2b8wb_register:
2507 case ARM::VST2b16wb_register:
2508 case ARM::VST2b32wb_register:
2510 return MCDisassembler::Fail;
2511 Inst.addOperand(MCOperand::CreateImm(0));
2513 case ARM::VST3d8_UPD:
2514 case ARM::VST3d16_UPD:
2515 case ARM::VST3d32_UPD:
2516 case ARM::VST3q8_UPD:
2517 case ARM::VST3q16_UPD:
2518 case ARM::VST3q32_UPD:
2519 case ARM::VST4d8_UPD:
2520 case ARM::VST4d16_UPD:
2521 case ARM::VST4d32_UPD:
2522 case ARM::VST4q8_UPD:
2523 case ARM::VST4q16_UPD:
2524 case ARM::VST4q32_UPD:
2525 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2526 return MCDisassembler::Fail;
2532 // AddrMode6 Base (register+alignment)
2533 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2534 return MCDisassembler::Fail;
2536 // AddrMode6 Offset (register)
2537 switch (Inst.getOpcode()) {
2540 Inst.addOperand(MCOperand::CreateReg(0));
2541 else if (Rm != 0xF) {
2542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2543 return MCDisassembler::Fail;
2546 case ARM::VST1d8wb_fixed:
2547 case ARM::VST1d16wb_fixed:
2548 case ARM::VST1d32wb_fixed:
2549 case ARM::VST1d64wb_fixed:
2550 case ARM::VST1q8wb_fixed:
2551 case ARM::VST1q16wb_fixed:
2552 case ARM::VST1q32wb_fixed:
2553 case ARM::VST1q64wb_fixed:
2554 case ARM::VST1d8Twb_fixed:
2555 case ARM::VST1d16Twb_fixed:
2556 case ARM::VST1d32Twb_fixed:
2557 case ARM::VST1d64Twb_fixed:
2558 case ARM::VST1d8Qwb_fixed:
2559 case ARM::VST1d16Qwb_fixed:
2560 case ARM::VST1d32Qwb_fixed:
2561 case ARM::VST1d64Qwb_fixed:
2562 case ARM::VST2d8wb_fixed:
2563 case ARM::VST2d16wb_fixed:
2564 case ARM::VST2d32wb_fixed:
2565 case ARM::VST2q8wb_fixed:
2566 case ARM::VST2q16wb_fixed:
2567 case ARM::VST2q32wb_fixed:
2568 case ARM::VST2b8wb_fixed:
2569 case ARM::VST2b16wb_fixed:
2570 case ARM::VST2b32wb_fixed:
2575 // First input register
2576 switch (Inst.getOpcode()) {
2581 case ARM::VST1q16wb_fixed:
2582 case ARM::VST1q16wb_register:
2583 case ARM::VST1q32wb_fixed:
2584 case ARM::VST1q32wb_register:
2585 case ARM::VST1q64wb_fixed:
2586 case ARM::VST1q64wb_register:
2587 case ARM::VST1q8wb_fixed:
2588 case ARM::VST1q8wb_register:
2592 case ARM::VST2d16wb_fixed:
2593 case ARM::VST2d16wb_register:
2594 case ARM::VST2d32wb_fixed:
2595 case ARM::VST2d32wb_register:
2596 case ARM::VST2d8wb_fixed:
2597 case ARM::VST2d8wb_register:
2598 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2599 return MCDisassembler::Fail;
2604 case ARM::VST2b16wb_fixed:
2605 case ARM::VST2b16wb_register:
2606 case ARM::VST2b32wb_fixed:
2607 case ARM::VST2b32wb_register:
2608 case ARM::VST2b8wb_fixed:
2609 case ARM::VST2b8wb_register:
2610 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2611 return MCDisassembler::Fail;
2614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2615 return MCDisassembler::Fail;
2618 // Second input register
2619 switch (Inst.getOpcode()) {
2623 case ARM::VST3d8_UPD:
2624 case ARM::VST3d16_UPD:
2625 case ARM::VST3d32_UPD:
2629 case ARM::VST4d8_UPD:
2630 case ARM::VST4d16_UPD:
2631 case ARM::VST4d32_UPD:
2632 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2633 return MCDisassembler::Fail;
2638 case ARM::VST3q8_UPD:
2639 case ARM::VST3q16_UPD:
2640 case ARM::VST3q32_UPD:
2644 case ARM::VST4q8_UPD:
2645 case ARM::VST4q16_UPD:
2646 case ARM::VST4q32_UPD:
2647 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2648 return MCDisassembler::Fail;
2654 // Third input register
2655 switch (Inst.getOpcode()) {
2659 case ARM::VST3d8_UPD:
2660 case ARM::VST3d16_UPD:
2661 case ARM::VST3d32_UPD:
2665 case ARM::VST4d8_UPD:
2666 case ARM::VST4d16_UPD:
2667 case ARM::VST4d32_UPD:
2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2669 return MCDisassembler::Fail;
2674 case ARM::VST3q8_UPD:
2675 case ARM::VST3q16_UPD:
2676 case ARM::VST3q32_UPD:
2680 case ARM::VST4q8_UPD:
2681 case ARM::VST4q16_UPD:
2682 case ARM::VST4q32_UPD:
2683 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2684 return MCDisassembler::Fail;
2690 // Fourth input register
2691 switch (Inst.getOpcode()) {
2695 case ARM::VST4d8_UPD:
2696 case ARM::VST4d16_UPD:
2697 case ARM::VST4d32_UPD:
2698 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2699 return MCDisassembler::Fail;
2704 case ARM::VST4q8_UPD:
2705 case ARM::VST4q16_UPD:
2706 case ARM::VST4q32_UPD:
2707 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2708 return MCDisassembler::Fail;
2717 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2718 uint64_t Address, const void *Decoder) {
2719 DecodeStatus S = MCDisassembler::Success;
2721 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2722 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2723 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2724 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2725 unsigned align = fieldFromInstruction(Insn, 4, 1);
2726 unsigned size = fieldFromInstruction(Insn, 6, 2);
2728 if (size == 0 && align == 1)
2729 return MCDisassembler::Fail;
2730 align *= (1 << size);
2732 switch (Inst.getOpcode()) {
2733 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2734 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2735 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2736 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2737 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2738 return MCDisassembler::Fail;
2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2742 return MCDisassembler::Fail;
2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2747 return MCDisassembler::Fail;
2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2751 return MCDisassembler::Fail;
2752 Inst.addOperand(MCOperand::CreateImm(align));
2754 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2755 // variant encodes Rm == 0xf. Anything else is a register offset post-
2756 // increment and we need to add the register operand to the instruction.
2757 if (Rm != 0xD && Rm != 0xF &&
2758 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2759 return MCDisassembler::Fail;
2764 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2765 uint64_t Address, const void *Decoder) {
2766 DecodeStatus S = MCDisassembler::Success;
2768 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2769 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2770 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2771 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2772 unsigned align = fieldFromInstruction(Insn, 4, 1);
2773 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2776 switch (Inst.getOpcode()) {
2777 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2778 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2779 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2780 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2781 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2782 return MCDisassembler::Fail;
2784 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2785 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2786 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2787 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2788 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2789 return MCDisassembler::Fail;
2792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2793 return MCDisassembler::Fail;
2798 Inst.addOperand(MCOperand::CreateImm(0));
2800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2801 return MCDisassembler::Fail;
2802 Inst.addOperand(MCOperand::CreateImm(align));
2804 if (Rm != 0xD && Rm != 0xF) {
2805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2806 return MCDisassembler::Fail;
2812 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2813 uint64_t Address, const void *Decoder) {
2814 DecodeStatus S = MCDisassembler::Success;
2816 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2817 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2818 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2819 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2820 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2823 return MCDisassembler::Fail;
2824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2825 return MCDisassembler::Fail;
2826 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2827 return MCDisassembler::Fail;
2829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2830 return MCDisassembler::Fail;
2833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 Inst.addOperand(MCOperand::CreateImm(0));
2838 Inst.addOperand(MCOperand::CreateReg(0));
2839 else if (Rm != 0xF) {
2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2841 return MCDisassembler::Fail;
2847 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2848 uint64_t Address, const void *Decoder) {
2849 DecodeStatus S = MCDisassembler::Success;
2851 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2852 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2853 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2854 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2855 unsigned size = fieldFromInstruction(Insn, 6, 2);
2856 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2857 unsigned align = fieldFromInstruction(Insn, 4, 1);
2861 return MCDisassembler::Fail;
2874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2875 return MCDisassembler::Fail;
2876 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2877 return MCDisassembler::Fail;
2878 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2879 return MCDisassembler::Fail;
2880 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2881 return MCDisassembler::Fail;
2883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2884 return MCDisassembler::Fail;
2887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2888 return MCDisassembler::Fail;
2889 Inst.addOperand(MCOperand::CreateImm(align));
2892 Inst.addOperand(MCOperand::CreateReg(0));
2893 else if (Rm != 0xF) {
2894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2895 return MCDisassembler::Fail;
2902 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2903 uint64_t Address, const void *Decoder) {
2904 DecodeStatus S = MCDisassembler::Success;
2906 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2907 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2908 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2909 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2910 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2911 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2912 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2913 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2916 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2917 return MCDisassembler::Fail;
2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2920 return MCDisassembler::Fail;
2923 Inst.addOperand(MCOperand::CreateImm(imm));
2925 switch (Inst.getOpcode()) {
2926 case ARM::VORRiv4i16:
2927 case ARM::VORRiv2i32:
2928 case ARM::VBICiv4i16:
2929 case ARM::VBICiv2i32:
2930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2931 return MCDisassembler::Fail;
2933 case ARM::VORRiv8i16:
2934 case ARM::VORRiv4i32:
2935 case ARM::VBICiv8i16:
2936 case ARM::VBICiv4i32:
2937 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2938 return MCDisassembler::Fail;
2947 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2948 uint64_t Address, const void *Decoder) {
2949 DecodeStatus S = MCDisassembler::Success;
2951 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2952 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2953 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2954 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2955 unsigned size = fieldFromInstruction(Insn, 18, 2);
2957 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2958 return MCDisassembler::Fail;
2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2960 return MCDisassembler::Fail;
2961 Inst.addOperand(MCOperand::CreateImm(8 << size));
2966 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2967 uint64_t Address, const void *Decoder) {
2968 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2969 return MCDisassembler::Success;
2972 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2973 uint64_t Address, const void *Decoder) {
2974 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2975 return MCDisassembler::Success;
2978 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2979 uint64_t Address, const void *Decoder) {
2980 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2981 return MCDisassembler::Success;
2984 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2985 uint64_t Address, const void *Decoder) {
2986 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2987 return MCDisassembler::Success;
2990 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2991 uint64_t Address, const void *Decoder) {
2992 DecodeStatus S = MCDisassembler::Success;
2994 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2995 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2996 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2997 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2998 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2999 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3000 unsigned op = fieldFromInstruction(Insn, 6, 1);
3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3003 return MCDisassembler::Fail;
3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3006 return MCDisassembler::Fail; // Writeback
3009 switch (Inst.getOpcode()) {
3012 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3013 return MCDisassembler::Fail;
3016 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3017 return MCDisassembler::Fail;
3020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3021 return MCDisassembler::Fail;
3026 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3027 uint64_t Address, const void *Decoder) {
3028 DecodeStatus S = MCDisassembler::Success;
3030 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3031 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3033 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3034 return MCDisassembler::Fail;
3036 switch(Inst.getOpcode()) {
3038 return MCDisassembler::Fail;
3040 break; // tADR does not explicitly represent the PC as an operand.
3042 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3046 Inst.addOperand(MCOperand::CreateImm(imm));
3050 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3051 uint64_t Address, const void *Decoder) {
3052 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3053 true, 2, Inst, Decoder))
3054 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3055 return MCDisassembler::Success;
3058 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3059 uint64_t Address, const void *Decoder) {
3060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3061 true, 4, Inst, Decoder))
3062 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3063 return MCDisassembler::Success;
3066 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3067 uint64_t Address, const void *Decoder) {
3068 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3069 true, 2, Inst, Decoder))
3070 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
3071 return MCDisassembler::Success;
3074 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3075 uint64_t Address, const void *Decoder) {
3076 DecodeStatus S = MCDisassembler::Success;
3078 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3079 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3081 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3084 return MCDisassembler::Fail;
3089 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3090 uint64_t Address, const void *Decoder) {
3091 DecodeStatus S = MCDisassembler::Success;
3093 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3094 unsigned imm = fieldFromInstruction(Val, 3, 5);
3096 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3097 return MCDisassembler::Fail;
3098 Inst.addOperand(MCOperand::CreateImm(imm));
3103 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3104 uint64_t Address, const void *Decoder) {
3105 unsigned imm = Val << 2;
3107 Inst.addOperand(MCOperand::CreateImm(imm));
3108 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3110 return MCDisassembler::Success;
3113 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3114 uint64_t Address, const void *Decoder) {
3115 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3116 Inst.addOperand(MCOperand::CreateImm(Val));
3118 return MCDisassembler::Success;
3121 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3122 uint64_t Address, const void *Decoder) {
3123 DecodeStatus S = MCDisassembler::Success;
3125 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3126 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3127 unsigned imm = fieldFromInstruction(Val, 0, 2);
3129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3130 return MCDisassembler::Fail;
3131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3132 return MCDisassembler::Fail;
3133 Inst.addOperand(MCOperand::CreateImm(imm));
3138 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3139 uint64_t Address, const void *Decoder) {
3140 DecodeStatus S = MCDisassembler::Success;
3142 switch (Inst.getOpcode()) {
3148 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3149 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3150 return MCDisassembler::Fail;
3154 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3156 switch (Inst.getOpcode()) {
3158 Inst.setOpcode(ARM::t2LDRBpci);
3161 Inst.setOpcode(ARM::t2LDRHpci);
3164 Inst.setOpcode(ARM::t2LDRSHpci);
3167 Inst.setOpcode(ARM::t2LDRSBpci);
3170 Inst.setOpcode(ARM::t2PLDi12);
3171 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3174 return MCDisassembler::Fail;
3177 int imm = fieldFromInstruction(Insn, 0, 12);
3178 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
3179 Inst.addOperand(MCOperand::CreateImm(imm));
3184 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3185 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3186 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3187 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3188 return MCDisassembler::Fail;
3193 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3194 uint64_t Address, const void *Decoder) {
3196 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3198 int imm = Val & 0xFF;
3200 if (!(Val & 0x100)) imm *= -1;
3201 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3204 return MCDisassembler::Success;
3207 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3208 uint64_t Address, const void *Decoder) {
3209 DecodeStatus S = MCDisassembler::Success;
3211 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3212 unsigned imm = fieldFromInstruction(Val, 0, 9);
3214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3215 return MCDisassembler::Fail;
3216 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3217 return MCDisassembler::Fail;
3222 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3223 uint64_t Address, const void *Decoder) {
3224 DecodeStatus S = MCDisassembler::Success;
3226 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3227 unsigned imm = fieldFromInstruction(Val, 0, 8);
3229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3230 return MCDisassembler::Fail;
3232 Inst.addOperand(MCOperand::CreateImm(imm));
3237 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3238 uint64_t Address, const void *Decoder) {
3239 int imm = Val & 0xFF;
3242 else if (!(Val & 0x100))
3244 Inst.addOperand(MCOperand::CreateImm(imm));
3246 return MCDisassembler::Success;
3250 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3251 uint64_t Address, const void *Decoder) {
3252 DecodeStatus S = MCDisassembler::Success;
3254 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3255 unsigned imm = fieldFromInstruction(Val, 0, 9);
3257 // Some instructions always use an additive offset.
3258 switch (Inst.getOpcode()) {
3273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3274 return MCDisassembler::Fail;
3275 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3276 return MCDisassembler::Fail;
3281 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3282 uint64_t Address, const void *Decoder) {
3283 DecodeStatus S = MCDisassembler::Success;
3285 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3286 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3287 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3288 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3290 unsigned load = fieldFromInstruction(Insn, 20, 1);
3293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3294 return MCDisassembler::Fail;
3297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3298 return MCDisassembler::Fail;
3301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3302 return MCDisassembler::Fail;
3305 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3306 return MCDisassembler::Fail;
3311 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3312 uint64_t Address, const void *Decoder) {
3313 DecodeStatus S = MCDisassembler::Success;
3315 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3316 unsigned imm = fieldFromInstruction(Val, 0, 12);
3318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3319 return MCDisassembler::Fail;
3320 Inst.addOperand(MCOperand::CreateImm(imm));
3326 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3327 uint64_t Address, const void *Decoder) {
3328 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3330 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3331 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3332 Inst.addOperand(MCOperand::CreateImm(imm));
3334 return MCDisassembler::Success;
3337 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3338 uint64_t Address, const void *Decoder) {
3339 DecodeStatus S = MCDisassembler::Success;
3341 if (Inst.getOpcode() == ARM::tADDrSP) {
3342 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3343 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3346 return MCDisassembler::Fail;
3347 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3349 return MCDisassembler::Fail;
3350 } else if (Inst.getOpcode() == ARM::tADDspr) {
3351 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3353 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3354 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3356 return MCDisassembler::Fail;
3362 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3363 uint64_t Address, const void *Decoder) {
3364 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3365 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3367 Inst.addOperand(MCOperand::CreateImm(imod));
3368 Inst.addOperand(MCOperand::CreateImm(flags));
3370 return MCDisassembler::Success;
3373 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3374 uint64_t Address, const void *Decoder) {
3375 DecodeStatus S = MCDisassembler::Success;
3376 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3377 unsigned add = fieldFromInstruction(Insn, 4, 1);
3379 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3380 return MCDisassembler::Fail;
3381 Inst.addOperand(MCOperand::CreateImm(add));
3386 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3387 uint64_t Address, const void *Decoder) {
3388 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3389 // Note only one trailing zero not two. Also the J1 and J2 values are from
3390 // the encoded instruction. So here change to I1 and I2 values via:
3391 // I1 = NOT(J1 EOR S);
3392 // I2 = NOT(J2 EOR S);
3393 // and build the imm32 with two trailing zeros as documented:
3394 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3395 unsigned S = (Val >> 23) & 1;
3396 unsigned J1 = (Val >> 22) & 1;
3397 unsigned J2 = (Val >> 21) & 1;
3398 unsigned I1 = !(J1 ^ S);
3399 unsigned I2 = !(J2 ^ S);
3400 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3401 int imm32 = SignExtend32<25>(tmp << 1);
3403 if (!tryAddingSymbolicOperand(Address,
3404 (Address & ~2u) + imm32 + 4,
3405 true, 4, Inst, Decoder))
3406 Inst.addOperand(MCOperand::CreateImm(imm32));
3407 return MCDisassembler::Success;
3410 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3411 uint64_t Address, const void *Decoder) {
3412 if (Val == 0xA || Val == 0xB)
3413 return MCDisassembler::Fail;
3415 Inst.addOperand(MCOperand::CreateImm(Val));
3416 return MCDisassembler::Success;
3420 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3421 uint64_t Address, const void *Decoder) {
3422 DecodeStatus S = MCDisassembler::Success;
3424 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3425 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3427 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3429 return MCDisassembler::Fail;
3430 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3431 return MCDisassembler::Fail;
3436 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3437 uint64_t Address, const void *Decoder) {
3438 DecodeStatus S = MCDisassembler::Success;
3440 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3441 if (pred == 0xE || pred == 0xF) {
3442 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3445 return MCDisassembler::Fail;
3447 Inst.setOpcode(ARM::t2DSB);
3450 Inst.setOpcode(ARM::t2DMB);
3453 Inst.setOpcode(ARM::t2ISB);
3457 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3458 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3461 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3462 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3463 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3464 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3465 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3467 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3468 return MCDisassembler::Fail;
3469 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3470 return MCDisassembler::Fail;
3475 // Decode a shifted immediate operand. These basically consist
3476 // of an 8-bit value, and a 4-bit directive that specifies either
3477 // a splat operation or a rotation.
3478 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3479 uint64_t Address, const void *Decoder) {
3480 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3482 unsigned byte = fieldFromInstruction(Val, 8, 2);
3483 unsigned imm = fieldFromInstruction(Val, 0, 8);
3486 Inst.addOperand(MCOperand::CreateImm(imm));
3489 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3492 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3495 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3500 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3501 unsigned rot = fieldFromInstruction(Val, 7, 5);
3502 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3503 Inst.addOperand(MCOperand::CreateImm(imm));
3506 return MCDisassembler::Success;
3510 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3511 uint64_t Address, const void *Decoder){
3512 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3513 true, 2, Inst, Decoder))
3514 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3515 return MCDisassembler::Success;
3518 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3519 uint64_t Address, const void *Decoder){
3520 // Val is passed in as S:J1:J2:imm10:imm11
3521 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3522 // the encoded instruction. So here change to I1 and I2 values via:
3523 // I1 = NOT(J1 EOR S);
3524 // I2 = NOT(J2 EOR S);
3525 // and build the imm32 with one trailing zero as documented:
3526 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3527 unsigned S = (Val >> 23) & 1;
3528 unsigned J1 = (Val >> 22) & 1;
3529 unsigned J2 = (Val >> 21) & 1;
3530 unsigned I1 = !(J1 ^ S);
3531 unsigned I2 = !(J2 ^ S);
3532 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3533 int imm32 = SignExtend32<25>(tmp << 1);
3535 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3536 true, 4, Inst, Decoder))
3537 Inst.addOperand(MCOperand::CreateImm(imm32));
3538 return MCDisassembler::Success;
3541 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3542 uint64_t Address, const void *Decoder) {
3544 return MCDisassembler::Fail;
3546 Inst.addOperand(MCOperand::CreateImm(Val));
3547 return MCDisassembler::Success;
3550 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3551 uint64_t Address, const void *Decoder) {
3552 if (!Val) return MCDisassembler::Fail;
3553 Inst.addOperand(MCOperand::CreateImm(Val));
3554 return MCDisassembler::Success;
3557 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3558 uint64_t Address, const void *Decoder) {
3559 DecodeStatus S = MCDisassembler::Success;
3561 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3562 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3563 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3565 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3568 return MCDisassembler::Fail;
3569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3570 return MCDisassembler::Fail;
3571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3572 return MCDisassembler::Fail;
3573 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3574 return MCDisassembler::Fail;
3580 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3581 uint64_t Address, const void *Decoder){
3582 DecodeStatus S = MCDisassembler::Success;
3584 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3585 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3586 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3587 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3589 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3590 return MCDisassembler::Fail;
3592 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3593 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3600 return MCDisassembler::Fail;
3601 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3602 return MCDisassembler::Fail;
3607 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3608 uint64_t Address, const void *Decoder) {
3609 DecodeStatus S = MCDisassembler::Success;
3611 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3612 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3613 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3614 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3615 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3616 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3618 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3621 return MCDisassembler::Fail;
3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3623 return MCDisassembler::Fail;
3624 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3625 return MCDisassembler::Fail;
3626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3627 return MCDisassembler::Fail;
3632 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3633 uint64_t Address, const void *Decoder) {
3634 DecodeStatus S = MCDisassembler::Success;
3636 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3637 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3638 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3639 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3640 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3641 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3642 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3644 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3645 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3648 return MCDisassembler::Fail;
3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3650 return MCDisassembler::Fail;
3651 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3652 return MCDisassembler::Fail;
3653 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3654 return MCDisassembler::Fail;
3660 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3661 uint64_t Address, const void *Decoder) {
3662 DecodeStatus S = MCDisassembler::Success;
3664 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3665 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3666 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3667 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3668 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3669 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3671 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3674 return MCDisassembler::Fail;
3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3676 return MCDisassembler::Fail;
3677 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3678 return MCDisassembler::Fail;
3679 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3680 return MCDisassembler::Fail;
3685 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3686 uint64_t Address, const void *Decoder) {
3687 DecodeStatus S = MCDisassembler::Success;
3689 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3690 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3691 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3692 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3693 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3694 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3696 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3699 return MCDisassembler::Fail;
3700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3701 return MCDisassembler::Fail;
3702 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3703 return MCDisassembler::Fail;
3704 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3705 return MCDisassembler::Fail;
3710 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3711 uint64_t Address, const void *Decoder) {
3712 DecodeStatus S = MCDisassembler::Success;
3714 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3715 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3716 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3717 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3718 unsigned size = fieldFromInstruction(Insn, 10, 2);
3724 return MCDisassembler::Fail;
3726 if (fieldFromInstruction(Insn, 4, 1))
3727 return MCDisassembler::Fail; // UNDEFINED
3728 index = fieldFromInstruction(Insn, 5, 3);
3731 if (fieldFromInstruction(Insn, 5, 1))
3732 return MCDisassembler::Fail; // UNDEFINED
3733 index = fieldFromInstruction(Insn, 6, 2);
3734 if (fieldFromInstruction(Insn, 4, 1))
3738 if (fieldFromInstruction(Insn, 6, 1))
3739 return MCDisassembler::Fail; // UNDEFINED
3740 index = fieldFromInstruction(Insn, 7, 1);
3742 switch (fieldFromInstruction(Insn, 4, 2)) {
3748 return MCDisassembler::Fail;
3753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3754 return MCDisassembler::Fail;
3755 if (Rm != 0xF) { // Writeback
3756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3757 return MCDisassembler::Fail;
3759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3760 return MCDisassembler::Fail;
3761 Inst.addOperand(MCOperand::CreateImm(align));
3764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3765 return MCDisassembler::Fail;
3767 Inst.addOperand(MCOperand::CreateReg(0));
3770 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3771 return MCDisassembler::Fail;
3772 Inst.addOperand(MCOperand::CreateImm(index));
3777 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3778 uint64_t Address, const void *Decoder) {
3779 DecodeStatus S = MCDisassembler::Success;
3781 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3782 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3783 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3784 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3785 unsigned size = fieldFromInstruction(Insn, 10, 2);
3791 return MCDisassembler::Fail;
3793 if (fieldFromInstruction(Insn, 4, 1))
3794 return MCDisassembler::Fail; // UNDEFINED
3795 index = fieldFromInstruction(Insn, 5, 3);
3798 if (fieldFromInstruction(Insn, 5, 1))
3799 return MCDisassembler::Fail; // UNDEFINED
3800 index = fieldFromInstruction(Insn, 6, 2);
3801 if (fieldFromInstruction(Insn, 4, 1))
3805 if (fieldFromInstruction(Insn, 6, 1))
3806 return MCDisassembler::Fail; // UNDEFINED
3807 index = fieldFromInstruction(Insn, 7, 1);
3809 switch (fieldFromInstruction(Insn, 4, 2)) {
3815 return MCDisassembler::Fail;
3820 if (Rm != 0xF) { // Writeback
3821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3822 return MCDisassembler::Fail;
3824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3825 return MCDisassembler::Fail;
3826 Inst.addOperand(MCOperand::CreateImm(align));
3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3830 return MCDisassembler::Fail;
3832 Inst.addOperand(MCOperand::CreateReg(0));
3835 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3836 return MCDisassembler::Fail;
3837 Inst.addOperand(MCOperand::CreateImm(index));
3843 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3844 uint64_t Address, const void *Decoder) {
3845 DecodeStatus S = MCDisassembler::Success;
3847 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3848 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3849 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3850 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3851 unsigned size = fieldFromInstruction(Insn, 10, 2);
3858 return MCDisassembler::Fail;
3860 index = fieldFromInstruction(Insn, 5, 3);
3861 if (fieldFromInstruction(Insn, 4, 1))
3865 index = fieldFromInstruction(Insn, 6, 2);
3866 if (fieldFromInstruction(Insn, 4, 1))
3868 if (fieldFromInstruction(Insn, 5, 1))
3872 if (fieldFromInstruction(Insn, 5, 1))
3873 return MCDisassembler::Fail; // UNDEFINED
3874 index = fieldFromInstruction(Insn, 7, 1);
3875 if (fieldFromInstruction(Insn, 4, 1) != 0)
3877 if (fieldFromInstruction(Insn, 6, 1))
3882 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3883 return MCDisassembler::Fail;
3884 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3885 return MCDisassembler::Fail;
3886 if (Rm != 0xF) { // Writeback
3887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3888 return MCDisassembler::Fail;
3890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 Inst.addOperand(MCOperand::CreateImm(align));
3895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3896 return MCDisassembler::Fail;
3898 Inst.addOperand(MCOperand::CreateReg(0));
3901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3902 return MCDisassembler::Fail;
3903 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3904 return MCDisassembler::Fail;
3905 Inst.addOperand(MCOperand::CreateImm(index));
3910 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3911 uint64_t Address, const void *Decoder) {
3912 DecodeStatus S = MCDisassembler::Success;
3914 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3915 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3916 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3917 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3918 unsigned size = fieldFromInstruction(Insn, 10, 2);
3925 return MCDisassembler::Fail;
3927 index = fieldFromInstruction(Insn, 5, 3);
3928 if (fieldFromInstruction(Insn, 4, 1))
3932 index = fieldFromInstruction(Insn, 6, 2);
3933 if (fieldFromInstruction(Insn, 4, 1))
3935 if (fieldFromInstruction(Insn, 5, 1))
3939 if (fieldFromInstruction(Insn, 5, 1))
3940 return MCDisassembler::Fail; // UNDEFINED
3941 index = fieldFromInstruction(Insn, 7, 1);
3942 if (fieldFromInstruction(Insn, 4, 1) != 0)
3944 if (fieldFromInstruction(Insn, 6, 1))
3949 if (Rm != 0xF) { // Writeback
3950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3951 return MCDisassembler::Fail;
3953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3954 return MCDisassembler::Fail;
3955 Inst.addOperand(MCOperand::CreateImm(align));
3958 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3959 return MCDisassembler::Fail;
3961 Inst.addOperand(MCOperand::CreateReg(0));
3964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3965 return MCDisassembler::Fail;
3966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3967 return MCDisassembler::Fail;
3968 Inst.addOperand(MCOperand::CreateImm(index));
3974 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
3975 uint64_t Address, const void *Decoder) {
3976 DecodeStatus S = MCDisassembler::Success;
3978 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3979 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3980 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3981 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3982 unsigned size = fieldFromInstruction(Insn, 10, 2);
3989 return MCDisassembler::Fail;
3991 if (fieldFromInstruction(Insn, 4, 1))
3992 return MCDisassembler::Fail; // UNDEFINED
3993 index = fieldFromInstruction(Insn, 5, 3);
3996 if (fieldFromInstruction(Insn, 4, 1))
3997 return MCDisassembler::Fail; // UNDEFINED
3998 index = fieldFromInstruction(Insn, 6, 2);
3999 if (fieldFromInstruction(Insn, 5, 1))
4003 if (fieldFromInstruction(Insn, 4, 2))
4004 return MCDisassembler::Fail; // UNDEFINED
4005 index = fieldFromInstruction(Insn, 7, 1);
4006 if (fieldFromInstruction(Insn, 6, 1))
4011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4012 return MCDisassembler::Fail;
4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4014 return MCDisassembler::Fail;
4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4016 return MCDisassembler::Fail;
4018 if (Rm != 0xF) { // Writeback
4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4020 return MCDisassembler::Fail;
4022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4023 return MCDisassembler::Fail;
4024 Inst.addOperand(MCOperand::CreateImm(align));
4027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4028 return MCDisassembler::Fail;
4030 Inst.addOperand(MCOperand::CreateReg(0));
4033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4034 return MCDisassembler::Fail;
4035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4036 return MCDisassembler::Fail;
4037 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4038 return MCDisassembler::Fail;
4039 Inst.addOperand(MCOperand::CreateImm(index));
4044 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4045 uint64_t Address, const void *Decoder) {
4046 DecodeStatus S = MCDisassembler::Success;
4048 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4049 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4050 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4051 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4052 unsigned size = fieldFromInstruction(Insn, 10, 2);
4059 return MCDisassembler::Fail;
4061 if (fieldFromInstruction(Insn, 4, 1))
4062 return MCDisassembler::Fail; // UNDEFINED
4063 index = fieldFromInstruction(Insn, 5, 3);
4066 if (fieldFromInstruction(Insn, 4, 1))
4067 return MCDisassembler::Fail; // UNDEFINED
4068 index = fieldFromInstruction(Insn, 6, 2);
4069 if (fieldFromInstruction(Insn, 5, 1))
4073 if (fieldFromInstruction(Insn, 4, 2))
4074 return MCDisassembler::Fail; // UNDEFINED
4075 index = fieldFromInstruction(Insn, 7, 1);
4076 if (fieldFromInstruction(Insn, 6, 1))
4081 if (Rm != 0xF) { // Writeback
4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4083 return MCDisassembler::Fail;
4085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4086 return MCDisassembler::Fail;
4087 Inst.addOperand(MCOperand::CreateImm(align));
4090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4091 return MCDisassembler::Fail;
4093 Inst.addOperand(MCOperand::CreateReg(0));
4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4099 return MCDisassembler::Fail;
4100 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4101 return MCDisassembler::Fail;
4102 Inst.addOperand(MCOperand::CreateImm(index));
4108 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4109 uint64_t Address, const void *Decoder) {
4110 DecodeStatus S = MCDisassembler::Success;
4112 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4113 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4114 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4116 unsigned size = fieldFromInstruction(Insn, 10, 2);
4123 return MCDisassembler::Fail;
4125 if (fieldFromInstruction(Insn, 4, 1))
4127 index = fieldFromInstruction(Insn, 5, 3);
4130 if (fieldFromInstruction(Insn, 4, 1))
4132 index = fieldFromInstruction(Insn, 6, 2);
4133 if (fieldFromInstruction(Insn, 5, 1))
4137 switch (fieldFromInstruction(Insn, 4, 2)) {
4141 return MCDisassembler::Fail;
4143 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4146 index = fieldFromInstruction(Insn, 7, 1);
4147 if (fieldFromInstruction(Insn, 6, 1))
4152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4153 return MCDisassembler::Fail;
4154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4155 return MCDisassembler::Fail;
4156 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4157 return MCDisassembler::Fail;
4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4159 return MCDisassembler::Fail;
4161 if (Rm != 0xF) { // Writeback
4162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4163 return MCDisassembler::Fail;
4165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4166 return MCDisassembler::Fail;
4167 Inst.addOperand(MCOperand::CreateImm(align));
4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4171 return MCDisassembler::Fail;
4173 Inst.addOperand(MCOperand::CreateReg(0));
4176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4179 return MCDisassembler::Fail;
4180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4183 return MCDisassembler::Fail;
4184 Inst.addOperand(MCOperand::CreateImm(index));
4189 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4190 uint64_t Address, const void *Decoder) {
4191 DecodeStatus S = MCDisassembler::Success;
4193 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4194 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4196 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4197 unsigned size = fieldFromInstruction(Insn, 10, 2);
4204 return MCDisassembler::Fail;
4206 if (fieldFromInstruction(Insn, 4, 1))
4208 index = fieldFromInstruction(Insn, 5, 3);
4211 if (fieldFromInstruction(Insn, 4, 1))
4213 index = fieldFromInstruction(Insn, 6, 2);
4214 if (fieldFromInstruction(Insn, 5, 1))
4218 switch (fieldFromInstruction(Insn, 4, 2)) {
4222 return MCDisassembler::Fail;
4224 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4227 index = fieldFromInstruction(Insn, 7, 1);
4228 if (fieldFromInstruction(Insn, 6, 1))
4233 if (Rm != 0xF) { // Writeback
4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4235 return MCDisassembler::Fail;
4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4238 return MCDisassembler::Fail;
4239 Inst.addOperand(MCOperand::CreateImm(align));
4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4243 return MCDisassembler::Fail;
4245 Inst.addOperand(MCOperand::CreateReg(0));
4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4249 return MCDisassembler::Fail;
4250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4251 return MCDisassembler::Fail;
4252 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4253 return MCDisassembler::Fail;
4254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4255 return MCDisassembler::Fail;
4256 Inst.addOperand(MCOperand::CreateImm(index));
4261 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4262 uint64_t Address, const void *Decoder) {
4263 DecodeStatus S = MCDisassembler::Success;
4264 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4265 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4266 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4267 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4268 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4270 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4271 S = MCDisassembler::SoftFail;
4273 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4274 return MCDisassembler::Fail;
4275 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4276 return MCDisassembler::Fail;
4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4278 return MCDisassembler::Fail;
4279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4280 return MCDisassembler::Fail;
4281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4282 return MCDisassembler::Fail;
4287 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4288 uint64_t Address, const void *Decoder) {
4289 DecodeStatus S = MCDisassembler::Success;
4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4291 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4292 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4293 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4294 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4296 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4297 S = MCDisassembler::SoftFail;
4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4300 return MCDisassembler::Fail;
4301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4302 return MCDisassembler::Fail;
4303 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4304 return MCDisassembler::Fail;
4305 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4306 return MCDisassembler::Fail;
4307 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4308 return MCDisassembler::Fail;
4313 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4314 uint64_t Address, const void *Decoder) {
4315 DecodeStatus S = MCDisassembler::Success;
4316 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4317 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4321 S = MCDisassembler::SoftFail;
4326 S = MCDisassembler::SoftFail;
4329 Inst.addOperand(MCOperand::CreateImm(pred));
4330 Inst.addOperand(MCOperand::CreateImm(mask));
4335 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4336 uint64_t Address, const void *Decoder) {
4337 DecodeStatus S = MCDisassembler::Success;
4339 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4340 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4341 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4342 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4343 unsigned W = fieldFromInstruction(Insn, 21, 1);
4344 unsigned U = fieldFromInstruction(Insn, 23, 1);
4345 unsigned P = fieldFromInstruction(Insn, 24, 1);
4346 bool writeback = (W == 1) | (P == 0);
4348 addr |= (U << 8) | (Rn << 9);
4350 if (writeback && (Rn == Rt || Rn == Rt2))
4351 Check(S, MCDisassembler::SoftFail);
4353 Check(S, MCDisassembler::SoftFail);
4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4357 return MCDisassembler::Fail;
4359 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 // Writeback operand
4362 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4363 return MCDisassembler::Fail;
4365 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4366 return MCDisassembler::Fail;
4372 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4373 uint64_t Address, const void *Decoder) {
4374 DecodeStatus S = MCDisassembler::Success;
4376 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4377 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4378 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4379 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4380 unsigned W = fieldFromInstruction(Insn, 21, 1);
4381 unsigned U = fieldFromInstruction(Insn, 23, 1);
4382 unsigned P = fieldFromInstruction(Insn, 24, 1);
4383 bool writeback = (W == 1) | (P == 0);
4385 addr |= (U << 8) | (Rn << 9);
4387 if (writeback && (Rn == Rt || Rn == Rt2))
4388 Check(S, MCDisassembler::SoftFail);
4390 // Writeback operand
4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4392 return MCDisassembler::Fail;
4394 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4395 return MCDisassembler::Fail;
4397 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4398 return MCDisassembler::Fail;
4400 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4401 return MCDisassembler::Fail;
4406 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4407 uint64_t Address, const void *Decoder) {
4408 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4409 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4410 if (sign1 != sign2) return MCDisassembler::Fail;
4412 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4413 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4414 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4416 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4418 return MCDisassembler::Success;
4421 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4423 const void *Decoder) {
4424 DecodeStatus S = MCDisassembler::Success;
4426 // Shift of "asr #32" is not allowed in Thumb2 mode.
4427 if (Val == 0x20) S = MCDisassembler::SoftFail;
4428 Inst.addOperand(MCOperand::CreateImm(Val));
4432 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4433 uint64_t Address, const void *Decoder) {
4434 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4435 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4436 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4437 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4440 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4442 DecodeStatus S = MCDisassembler::Success;
4444 if (Rt == Rn || Rn == Rt2)
4445 S = MCDisassembler::SoftFail;
4447 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4448 return MCDisassembler::Fail;
4449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4450 return MCDisassembler::Fail;
4451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4452 return MCDisassembler::Fail;
4453 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4454 return MCDisassembler::Fail;
4459 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4460 uint64_t Address, const void *Decoder) {
4461 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4462 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4463 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4464 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4465 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4466 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4468 DecodeStatus S = MCDisassembler::Success;
4470 // VMOVv2f32 is ambiguous with these decodings.
4471 if (!(imm & 0x38) && cmode == 0xF) {
4472 Inst.setOpcode(ARM::VMOVv2f32);
4473 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4476 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4478 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4479 return MCDisassembler::Fail;
4480 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4481 return MCDisassembler::Fail;
4482 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4487 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4488 uint64_t Address, const void *Decoder) {
4489 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4490 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4491 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4492 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4493 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4494 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4496 DecodeStatus S = MCDisassembler::Success;
4498 // VMOVv4f32 is ambiguous with these decodings.
4499 if (!(imm & 0x38) && cmode == 0xF) {
4500 Inst.setOpcode(ARM::VMOVv4f32);
4501 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4504 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4506 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4507 return MCDisassembler::Fail;
4508 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4509 return MCDisassembler::Fail;
4510 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4515 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4516 uint64_t Address, const void *Decoder) {
4517 DecodeStatus S = MCDisassembler::Success;
4519 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4520 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4521 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4522 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4523 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4525 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4526 S = MCDisassembler::SoftFail;
4528 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4529 return MCDisassembler::Fail;
4530 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4531 return MCDisassembler::Fail;
4532 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4533 return MCDisassembler::Fail;
4534 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4535 return MCDisassembler::Fail;
4536 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4537 return MCDisassembler::Fail;
4542 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4543 uint64_t Address, const void *Decoder) {
4545 DecodeStatus S = MCDisassembler::Success;
4547 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4548 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4549 unsigned cop = fieldFromInstruction(Val, 8, 4);
4550 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4551 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4553 if ((cop & ~0x1) == 0xa)
4554 return MCDisassembler::Fail;
4557 S = MCDisassembler::SoftFail;
4559 Inst.addOperand(MCOperand::CreateImm(cop));
4560 Inst.addOperand(MCOperand::CreateImm(opc1));
4561 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4562 return MCDisassembler::Fail;
4563 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4564 return MCDisassembler::Fail;
4565 Inst.addOperand(MCOperand::CreateImm(CRm));