1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "ARMDisassembler.h"
14 #include "ARMRegisterInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
27 // Forward declare these because the autogenerated code will reference them.
28 // Definitions are further down.
29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
30 uint64_t Address, const void *Decoder);
31 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
32 uint64_t Address, const void *Decoder);
33 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
34 uint64_t Address, const void *Decoder);
35 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
36 uint64_t Address, const void *Decoder);
37 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
38 uint64_t Address, const void *Decoder);
39 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
40 uint64_t Address, const void *Decoder);
41 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
42 uint64_t Address, const void *Decoder);
43 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
44 uint64_t Address, const void *Decoder);
45 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 uint64_t Address, const void *Decoder);
48 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
49 uint64_t Address, const void *Decoder);
50 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
51 uint64_t Address, const void *Decoder);
52 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
53 uint64_t Address, const void *Decoder);
54 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
55 uint64_t Address, const void *Decoder);
56 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
57 uint64_t Address, const void *Decoder);
58 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
59 uint64_t Address, const void *Decoder);
60 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
61 uint64_t Address, const void *Decoder);
63 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
64 uint64_t Address, const void *Decoder);
65 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
66 uint64_t Address, const void *Decoder);
67 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
68 uint64_t Address, const void *Decoder);
69 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
70 uint64_t Address, const void *Decoder);
71 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
72 uint64_t Address, const void *Decoder);
73 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
74 uint64_t Address, const void *Decoder);
75 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
76 uint64_t Address, const void *Decoder);
78 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
82 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
83 uint64_t Address, const void *Decoder);
84 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
85 uint64_t Address, const void *Decoder);
86 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
87 uint64_t Address, const void *Decoder);
88 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
89 uint64_t Address, const void *Decoder);
90 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
91 uint64_t Address, const void *Decoder);
92 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
93 uint64_t Address, const void *Decoder);
94 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
95 uint64_t Address, const void *Decoder);
96 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
97 uint64_t Address, const void *Decoder);
98 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
99 uint64_t Address, const void *Decoder);
100 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
101 uint64_t Address, const void *Decoder);
102 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
103 uint64_t Address, const void *Decoder);
104 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
105 uint64_t Address, const void *Decoder);
106 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
107 uint64_t Address, const void *Decoder);
108 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
109 uint64_t Address, const void *Decoder);
110 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
111 uint64_t Address, const void *Decoder);
112 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
113 uint64_t Address, const void *Decoder);
114 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
115 uint64_t Address, const void *Decoder);
116 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
117 uint64_t Address, const void *Decoder);
118 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
119 uint64_t Address, const void *Decoder);
120 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
121 uint64_t Address, const void *Decoder);
122 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
123 uint64_t Address, const void *Decoder);
124 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
125 uint64_t Address, const void *Decoder);
126 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
127 uint64_t Address, const void *Decoder);
128 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
129 uint64_t Address, const void *Decoder);
132 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
133 uint64_t Address, const void *Decoder);
134 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
142 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
143 uint64_t Address, const void *Decoder);
144 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
145 uint64_t Address, const void *Decoder);
146 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
147 uint64_t Address, const void *Decoder);
148 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
149 uint64_t Address, const void *Decoder);
150 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
151 uint64_t Address, const void *Decoder);
152 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
153 uint64_t Address, const void *Decoder);
154 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
155 uint64_t Address, const void *Decoder);
156 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
157 uint64_t Address, const void *Decoder);
158 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
159 uint64_t Address, const void *Decoder);
160 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
161 uint64_t Address, const void *Decoder);
162 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
163 uint64_t Address, const void *Decoder);
164 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
165 uint64_t Address, const void *Decoder);
166 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
169 uint64_t Address, const void *Decoder);
170 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
171 uint64_t Address, const void *Decoder);
172 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
173 uint64_t Address, const void *Decoder);
174 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
175 uint64_t Address, const void *Decoder);
176 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
177 uint64_t Address, const void *Decoder);
178 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
179 uint64_t Address, const void *Decoder);
181 #include "ARMGenDisassemblerTables.inc"
182 #include "ARMGenInstrInfo.inc"
183 #include "ARMGenEDInfo.inc"
185 using namespace llvm;
187 static MCDisassembler *createARMDisassembler(const Target &T) {
188 return new ARMDisassembler;
191 static MCDisassembler *createThumbDisassembler(const Target &T) {
192 return new ThumbDisassembler;
195 EDInstInfo *ARMDisassembler::getEDInfo() const {
199 EDInstInfo *ThumbDisassembler::getEDInfo() const {
204 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
205 const MemoryObject &Region,
206 uint64_t Address,raw_ostream &os) const {
209 // We want to read exactly 4 bytes of data.
210 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
213 // Encoded as a small-endian 32-bit word in the stream.
214 uint32_t insn = (bytes[3] << 24) |
219 // Calling the auto-generated decoder function.
220 bool result = decodeARMInstruction32(MI, insn, Address, this);
226 // Instructions that are shared between ARM and Thumb modes.
227 // FIXME: This shouldn't really exist. It's an artifact of the
228 // fact that we fail to encode a few instructions properly for Thumb.
230 result = decodeCommonInstruction32(MI, insn, Address, this);
236 // VFP and NEON instructions, similarly, are shared between ARM
239 result = decodeVFPInstruction32(MI, insn, Address, this);
246 result = decodeNEONInstruction32(MI, insn, Address, this);
248 // Add a fake predicate operand, because we share these instruction
249 // definitions with Thumb2 where these instructions are predicable.
250 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
261 extern MCInstrDesc ARMInsts[];
264 // Thumb1 instructions don't have explicit S bits. Rather, they
265 // implicitly set CPSR. Since it's not represented in the encoding, the
266 // auto-generated decoder won't inject the CPSR operand. We need to fix
267 // that as a post-pass.
268 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
269 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
270 MCInst::iterator I = MI.begin();
271 for (unsigned i = 0; i < MI.size(); ++i, ++I) {
272 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
273 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
278 if (OpInfo[MI.size()].isOptionalDef() &&
279 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID)
280 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
283 // Most Thumb instructions don't have explicit predicates in the
284 // encoding, but rather get their predicates from IT context. We need
285 // to fix up the predicate operands using this context information as a
287 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
288 // A few instructions actually have predicates encoded in them. Don't
289 // try to overwrite it if we're seeing one of those.
290 switch (MI.getOpcode()) {
298 // If we're in an IT block, base the predicate on that. Otherwise,
299 // assume a predicate of AL.
301 if (ITBlock.size()) {
307 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
308 MCInst::iterator I = MI.begin();
309 for (unsigned i = 0; i < MI.size(); ++i, ++I) {
310 if (OpInfo[i].isPredicate()) {
311 I = MI.insert(I, MCOperand::CreateImm(CC));
314 MI.insert(I, MCOperand::CreateReg(0));
316 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
321 MI.insert(MI.end(), MCOperand::CreateImm(CC));
323 MI.insert(MI.end(), MCOperand::CreateReg(0));
325 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR));
328 // Thumb VFP instructions are a special case. Because we share their
329 // encodings between ARM and Thumb modes, and they are predicable in ARM
330 // mode, the auto-generated decoder will give them an (incorrect)
331 // predicate operand. We need to rewrite these operands based on the IT
332 // context as a post-pass.
333 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
335 if (ITBlock.size()) {
341 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
342 MCInst::iterator I = MI.begin();
343 for (unsigned i = 0; i < MI.size(); ++i, ++I) {
344 if (OpInfo[i].isPredicate() ) {
350 I->setReg(ARM::CPSR);
357 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
358 const MemoryObject &Region,
359 uint64_t Address,raw_ostream &os) const {
362 // We want to read exactly 2 bytes of data.
363 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
366 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
367 bool result = decodeThumbInstruction16(MI, insn16, Address, this);
370 bool InITBlock = ITBlock.size();
371 AddThumbPredicate(MI);
372 AddThumb1SBit(MI, InITBlock);
377 result = decodeThumb2Instruction16(MI, insn16, Address, this);
380 AddThumbPredicate(MI);
382 // If we find an IT instruction, we need to parse its condition
383 // code and mask operands so that we can apply them correctly
384 // to the subsequent instructions.
385 if (MI.getOpcode() == ARM::t2IT) {
386 unsigned firstcond = MI.getOperand(0).getImm();
387 uint32_t mask = MI.getOperand(1).getImm();
388 unsigned zeros = CountTrailingZeros_32(mask);
391 for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
392 if (firstcond ^ (mask & 1))
393 ITBlock.push_back(firstcond ^ 1);
395 ITBlock.push_back(firstcond);
398 ITBlock.push_back(firstcond);
404 // We want to read exactly 4 bytes of data.
405 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
408 uint32_t insn32 = (bytes[3] << 8) |
413 result = decodeThumbInstruction32(MI, insn32, Address, this);
416 bool InITBlock = ITBlock.size();
417 AddThumbPredicate(MI);
418 AddThumb1SBit(MI, InITBlock);
423 result = decodeThumb2Instruction32(MI, insn32, Address, this);
426 AddThumbPredicate(MI);
431 result = decodeVFPInstruction32(MI, insn32, Address, this);
434 UpdateThumbVFPPredicate(MI);
439 result = decodeCommonInstruction32(MI, insn32, Address, this);
442 AddThumbPredicate(MI);
450 extern "C" void LLVMInitializeARMDisassembler() {
451 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
452 createARMDisassembler);
453 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
454 createThumbDisassembler);
457 static const unsigned GPRDecoderTable[] = {
458 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
459 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
460 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
461 ARM::R12, ARM::SP, ARM::LR, ARM::PC
464 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
465 uint64_t Address, const void *Decoder) {
469 unsigned Register = GPRDecoderTable[RegNo];
470 Inst.addOperand(MCOperand::CreateReg(Register));
474 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
475 uint64_t Address, const void *Decoder) {
478 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
481 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
482 uint64_t Address, const void *Decoder) {
483 unsigned Register = 0;
507 Inst.addOperand(MCOperand::CreateReg(Register));
511 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
512 uint64_t Address, const void *Decoder) {
513 if (RegNo == 13 || RegNo == 15) return false;
514 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
517 static const unsigned SPRDecoderTable[] = {
518 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
519 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
520 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
521 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
522 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
523 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
524 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
525 ARM::S28, ARM::S29, ARM::S30, ARM::S31
528 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
529 uint64_t Address, const void *Decoder) {
533 unsigned Register = SPRDecoderTable[RegNo];
534 Inst.addOperand(MCOperand::CreateReg(Register));
538 static const unsigned DPRDecoderTable[] = {
539 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
540 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
541 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
542 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
543 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
544 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
545 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
546 ARM::D28, ARM::D29, ARM::D30, ARM::D31
549 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
550 uint64_t Address, const void *Decoder) {
554 unsigned Register = DPRDecoderTable[RegNo];
555 Inst.addOperand(MCOperand::CreateReg(Register));
559 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
560 uint64_t Address, const void *Decoder) {
563 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
566 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
567 uint64_t Address, const void *Decoder) {
570 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
573 static const unsigned QPRDecoderTable[] = {
574 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
575 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
576 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
577 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
581 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
582 uint64_t Address, const void *Decoder) {
587 unsigned Register = QPRDecoderTable[RegNo];
588 Inst.addOperand(MCOperand::CreateReg(Register));
592 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
593 uint64_t Address, const void *Decoder) {
594 if (Val == 0xF) return false;
595 // AL predicate is not allowed on Thumb1 branches.
596 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
598 Inst.addOperand(MCOperand::CreateImm(Val));
599 if (Val == ARMCC::AL) {
600 Inst.addOperand(MCOperand::CreateReg(0));
602 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
606 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
607 uint64_t Address, const void *Decoder) {
609 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
611 Inst.addOperand(MCOperand::CreateReg(0));
615 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
616 uint64_t Address, const void *Decoder) {
617 uint32_t imm = Val & 0xFF;
618 uint32_t rot = (Val & 0xF00) >> 7;
619 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
620 Inst.addOperand(MCOperand::CreateImm(rot_imm));
624 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
625 uint64_t Address, const void *Decoder) {
627 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
631 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
632 uint64_t Address, const void *Decoder) {
634 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
635 unsigned type = fieldFromInstruction32(Val, 5, 2);
636 unsigned imm = fieldFromInstruction32(Val, 7, 5);
638 // Register-immediate
639 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
641 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
657 if (Shift == ARM_AM::ror && imm == 0)
660 unsigned Op = Shift | (imm << 3);
661 Inst.addOperand(MCOperand::CreateImm(Op));
666 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
667 uint64_t Address, const void *Decoder) {
669 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
670 unsigned type = fieldFromInstruction32(Val, 5, 2);
671 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
674 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
675 DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
677 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
693 Inst.addOperand(MCOperand::CreateImm(Shift));
698 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
699 uint64_t Address, const void *Decoder) {
700 for (unsigned i = 0; i < 16; ++i) {
702 DecodeGPRRegisterClass(Inst, i, Address, Decoder);
708 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
709 uint64_t Address, const void *Decoder) {
710 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
711 unsigned regs = Val & 0xFF;
713 DecodeSPRRegisterClass(Inst, Vd, Address, Decoder);
714 for (unsigned i = 0; i < (regs - 1); ++i)
715 DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder);
720 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
721 uint64_t Address, const void *Decoder) {
722 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
723 unsigned regs = (Val & 0xFF) / 2;
725 DecodeDPRRegisterClass(Inst, Vd, Address, Decoder);
726 for (unsigned i = 0; i < (regs - 1); ++i)
727 DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder);
732 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
733 uint64_t Address, const void *Decoder) {
734 unsigned msb = fieldFromInstruction32(Val, 5, 5);
735 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
736 uint32_t msb_mask = (1 << (msb+1)) - 1;
737 uint32_t lsb_mask = (1 << lsb) - 1;
738 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
742 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
743 uint64_t Address, const void *Decoder) {
744 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
745 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
746 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
747 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
748 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
749 unsigned U = fieldFromInstruction32(Insn, 23, 1);
751 switch (Inst.getOpcode()) {
752 case ARM::LDC_OFFSET:
755 case ARM::LDC_OPTION:
756 case ARM::LDCL_OFFSET:
759 case ARM::LDCL_OPTION:
760 case ARM::STC_OFFSET:
763 case ARM::STC_OPTION:
764 case ARM::STCL_OFFSET:
767 case ARM::STCL_OPTION:
768 if (coproc == 0xA || coproc == 0xB)
775 Inst.addOperand(MCOperand::CreateImm(coproc));
776 Inst.addOperand(MCOperand::CreateImm(CRd));
777 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
778 switch (Inst.getOpcode()) {
779 case ARM::LDC_OPTION:
780 case ARM::LDCL_OPTION:
781 case ARM::LDC2_OPTION:
782 case ARM::LDC2L_OPTION:
783 case ARM::STC_OPTION:
784 case ARM::STCL_OPTION:
785 case ARM::STC2_OPTION:
786 case ARM::STC2L_OPTION:
791 Inst.addOperand(MCOperand::CreateReg(0));
795 unsigned P = fieldFromInstruction32(Insn, 24, 1);
796 unsigned W = fieldFromInstruction32(Insn, 21, 1);
798 bool writeback = (P == 0) || (W == 1);
799 unsigned idx_mode = 0;
801 idx_mode = ARMII::IndexModePre;
802 else if (!P && writeback)
803 idx_mode = ARMII::IndexModePost;
805 switch (Inst.getOpcode()) {
809 case ARM::LDC_OPTION:
810 case ARM::LDCL_OPTION:
811 case ARM::LDC2_OPTION:
812 case ARM::LDC2L_OPTION:
813 case ARM::STC_OPTION:
814 case ARM::STCL_OPTION:
815 case ARM::STC2_OPTION:
816 case ARM::STC2L_OPTION:
817 Inst.addOperand(MCOperand::CreateImm(imm));
821 Inst.addOperand(MCOperand::CreateImm(
822 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
824 Inst.addOperand(MCOperand::CreateImm(
825 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
829 switch (Inst.getOpcode()) {
830 case ARM::LDC_OFFSET:
833 case ARM::LDC_OPTION:
834 case ARM::LDCL_OFFSET:
837 case ARM::LDCL_OPTION:
838 case ARM::STC_OFFSET:
841 case ARM::STC_OPTION:
842 case ARM::STCL_OFFSET:
845 case ARM::STCL_OPTION:
846 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
855 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
856 uint64_t Address, const void *Decoder) {
857 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
858 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
859 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
860 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
861 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
862 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
863 unsigned P = fieldFromInstruction32(Insn, 24, 1);
864 unsigned W = fieldFromInstruction32(Insn, 21, 1);
866 // On stores, the writeback operand precedes Rt.
867 switch (Inst.getOpcode()) {
868 case ARM::STR_POST_IMM:
869 case ARM::STR_POST_REG:
874 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
880 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder);
882 // On loads, the writeback operand comes after Rt.
883 switch (Inst.getOpcode()) {
884 case ARM::LDR_POST_IMM:
885 case ARM::LDR_POST_REG:
887 case ARM::LDRBT_POST_REG:
888 case ARM::LDRBT_POST_IMM:
891 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
897 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
899 ARM_AM::AddrOpc Op = ARM_AM::add;
900 if (!fieldFromInstruction32(Insn, 23, 1))
903 bool writeback = (P == 0) || (W == 1);
904 unsigned idx_mode = 0;
906 idx_mode = ARMII::IndexModePre;
907 else if (!P && writeback)
908 idx_mode = ARMII::IndexModePost;
911 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
912 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
913 switch( fieldFromInstruction32(Insn, 5, 2)) {
929 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
930 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
932 Inst.addOperand(MCOperand::CreateImm(imm));
934 Inst.addOperand(MCOperand::CreateReg(0));
935 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
936 Inst.addOperand(MCOperand::CreateImm(tmp));
939 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
944 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
945 uint64_t Address, const void *Decoder) {
946 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
947 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
948 unsigned type = fieldFromInstruction32(Val, 5, 2);
949 unsigned imm = fieldFromInstruction32(Val, 7, 5);
950 unsigned U = fieldFromInstruction32(Val, 12, 1);
952 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
968 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
969 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
972 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
974 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
975 Inst.addOperand(MCOperand::CreateImm(shift));
980 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
981 uint64_t Address, const void *Decoder) {
982 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
983 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
984 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
985 unsigned type = fieldFromInstruction32(Insn, 22, 1);
986 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
987 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
988 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
989 unsigned W = fieldFromInstruction32(Insn, 21, 1);
990 unsigned P = fieldFromInstruction32(Insn, 24, 1);
992 bool writeback = (W == 1) | (P == 0);
993 if (writeback) { // Writeback
995 U |= ARMII::IndexModePre << 9;
997 U |= ARMII::IndexModePost << 9;
999 // On stores, the writeback operand precedes Rt.
1000 switch (Inst.getOpcode()) {
1003 case ARM::STRD_POST:
1004 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1011 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder);
1012 switch (Inst.getOpcode()) {
1015 case ARM::STRD_POST:
1018 case ARM::LDRD_POST:
1019 DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder);
1026 // On loads, the writeback operand comes after Rt.
1027 switch (Inst.getOpcode()) {
1030 case ARM::LDRD_POST:
1033 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1040 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1043 Inst.addOperand(MCOperand::CreateReg(0));
1044 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1046 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1047 Inst.addOperand(MCOperand::CreateImm(U));
1050 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
1055 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1056 uint64_t Address, const void *Decoder) {
1057 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1058 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1075 Inst.addOperand(MCOperand::CreateImm(mode));
1076 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1081 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1083 uint64_t Address, const void *Decoder) {
1084 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1085 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1086 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1089 switch (Inst.getOpcode()) {
1091 Inst.setOpcode(ARM::RFEDA);
1093 case ARM::STMDA_UPD:
1094 Inst.setOpcode(ARM::RFEDA_UPD);
1097 Inst.setOpcode(ARM::RFEDB);
1099 case ARM::STMDB_UPD:
1100 Inst.setOpcode(ARM::RFEDB_UPD);
1103 Inst.setOpcode(ARM::RFEIA);
1105 case ARM::STMIA_UPD:
1106 Inst.setOpcode(ARM::RFEIA_UPD);
1109 Inst.setOpcode(ARM::RFEIB);
1111 case ARM::STMIB_UPD:
1112 Inst.setOpcode(ARM::RFEIB_UPD);
1116 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1119 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1120 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); // Tied
1121 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
1122 DecodeRegListOperand(Inst, reglist, Address, Decoder);
1127 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1128 uint64_t Address, const void *Decoder) {
1129 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1130 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1131 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1132 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1134 if (M && mode && imod && iflags) {
1135 Inst.setOpcode(ARM::CPS3p);
1136 Inst.addOperand(MCOperand::CreateImm(imod));
1137 Inst.addOperand(MCOperand::CreateImm(iflags));
1138 Inst.addOperand(MCOperand::CreateImm(mode));
1140 } else if (!mode && !M) {
1141 Inst.setOpcode(ARM::CPS2p);
1142 Inst.addOperand(MCOperand::CreateImm(imod));
1143 Inst.addOperand(MCOperand::CreateImm(iflags));
1145 } else if (!imod && !iflags && M) {
1146 Inst.setOpcode(ARM::CPS1p);
1147 Inst.addOperand(MCOperand::CreateImm(mode));
1154 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1155 uint64_t Address, const void *Decoder) {
1156 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1157 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1158 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1159 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1160 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1163 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1165 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
1166 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1167 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1168 DecodeGPRRegisterClass(Inst, Ra, Address, Decoder);
1173 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1174 uint64_t Address, const void *Decoder) {
1175 unsigned add = fieldFromInstruction32(Val, 12, 1);
1176 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1177 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1179 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1181 if (!add) imm *= -1;
1182 if (imm == 0 && !add) imm = INT32_MIN;
1183 Inst.addOperand(MCOperand::CreateImm(imm));
1188 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1189 uint64_t Address, const void *Decoder) {
1190 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1191 unsigned U = fieldFromInstruction32(Val, 8, 1);
1192 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1194 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1197 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1199 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1204 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1205 uint64_t Address, const void *Decoder) {
1206 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1209 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1210 uint64_t Address, const void *Decoder) {
1211 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1212 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1215 Inst.setOpcode(ARM::BLXi);
1216 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1217 Inst.addOperand(MCOperand::CreateImm(imm));
1221 Inst.addOperand(MCOperand::CreateImm(imm));
1222 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
1228 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1229 uint64_t Address, const void *Decoder) {
1230 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1234 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1235 uint64_t Address, const void *Decoder) {
1236 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1237 unsigned align = fieldFromInstruction32(Val, 4, 2);
1239 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1241 Inst.addOperand(MCOperand::CreateImm(0));
1243 Inst.addOperand(MCOperand::CreateImm(4 << align));
1248 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1249 uint64_t Address, const void *Decoder) {
1250 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1251 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1252 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1254 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1255 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1257 // First output register
1258 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1260 // Second output register
1261 switch (Inst.getOpcode()) {
1266 case ARM::VLD1q8_UPD:
1267 case ARM::VLD1q16_UPD:
1268 case ARM::VLD1q32_UPD:
1269 case ARM::VLD1q64_UPD:
1274 case ARM::VLD1d8T_UPD:
1275 case ARM::VLD1d16T_UPD:
1276 case ARM::VLD1d32T_UPD:
1277 case ARM::VLD1d64T_UPD:
1282 case ARM::VLD1d8Q_UPD:
1283 case ARM::VLD1d16Q_UPD:
1284 case ARM::VLD1d32Q_UPD:
1285 case ARM::VLD1d64Q_UPD:
1289 case ARM::VLD2d8_UPD:
1290 case ARM::VLD2d16_UPD:
1291 case ARM::VLD2d32_UPD:
1295 case ARM::VLD2q8_UPD:
1296 case ARM::VLD2q16_UPD:
1297 case ARM::VLD2q32_UPD:
1301 case ARM::VLD3d8_UPD:
1302 case ARM::VLD3d16_UPD:
1303 case ARM::VLD3d32_UPD:
1307 case ARM::VLD4d8_UPD:
1308 case ARM::VLD4d16_UPD:
1309 case ARM::VLD4d32_UPD:
1310 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder);
1315 case ARM::VLD2b8_UPD:
1316 case ARM::VLD2b16_UPD:
1317 case ARM::VLD2b32_UPD:
1321 case ARM::VLD3q8_UPD:
1322 case ARM::VLD3q16_UPD:
1323 case ARM::VLD3q32_UPD:
1327 case ARM::VLD4q8_UPD:
1328 case ARM::VLD4q16_UPD:
1329 case ARM::VLD4q32_UPD:
1330 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
1335 // Third output register
1336 switch(Inst.getOpcode()) {
1341 case ARM::VLD1d8T_UPD:
1342 case ARM::VLD1d16T_UPD:
1343 case ARM::VLD1d32T_UPD:
1344 case ARM::VLD1d64T_UPD:
1349 case ARM::VLD1d8Q_UPD:
1350 case ARM::VLD1d16Q_UPD:
1351 case ARM::VLD1d32Q_UPD:
1352 case ARM::VLD1d64Q_UPD:
1356 case ARM::VLD2q8_UPD:
1357 case ARM::VLD2q16_UPD:
1358 case ARM::VLD2q32_UPD:
1362 case ARM::VLD3d8_UPD:
1363 case ARM::VLD3d16_UPD:
1364 case ARM::VLD3d32_UPD:
1368 case ARM::VLD4d8_UPD:
1369 case ARM::VLD4d16_UPD:
1370 case ARM::VLD4d32_UPD:
1371 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
1376 case ARM::VLD3q8_UPD:
1377 case ARM::VLD3q16_UPD:
1378 case ARM::VLD3q32_UPD:
1382 case ARM::VLD4q8_UPD:
1383 case ARM::VLD4q16_UPD:
1384 case ARM::VLD4q32_UPD:
1385 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder);
1391 // Fourth output register
1392 switch (Inst.getOpcode()) {
1397 case ARM::VLD1d8Q_UPD:
1398 case ARM::VLD1d16Q_UPD:
1399 case ARM::VLD1d32Q_UPD:
1400 case ARM::VLD1d64Q_UPD:
1404 case ARM::VLD2q8_UPD:
1405 case ARM::VLD2q16_UPD:
1406 case ARM::VLD2q32_UPD:
1410 case ARM::VLD4d8_UPD:
1411 case ARM::VLD4d16_UPD:
1412 case ARM::VLD4d32_UPD:
1413 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder);
1418 case ARM::VLD4q8_UPD:
1419 case ARM::VLD4q16_UPD:
1420 case ARM::VLD4q32_UPD:
1421 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder);
1427 // Writeback operand
1428 switch (Inst.getOpcode()) {
1429 case ARM::VLD1d8_UPD:
1430 case ARM::VLD1d16_UPD:
1431 case ARM::VLD1d32_UPD:
1432 case ARM::VLD1d64_UPD:
1433 case ARM::VLD1q8_UPD:
1434 case ARM::VLD1q16_UPD:
1435 case ARM::VLD1q32_UPD:
1436 case ARM::VLD1q64_UPD:
1437 case ARM::VLD1d8T_UPD:
1438 case ARM::VLD1d16T_UPD:
1439 case ARM::VLD1d32T_UPD:
1440 case ARM::VLD1d64T_UPD:
1441 case ARM::VLD1d8Q_UPD:
1442 case ARM::VLD1d16Q_UPD:
1443 case ARM::VLD1d32Q_UPD:
1444 case ARM::VLD1d64Q_UPD:
1445 case ARM::VLD2d8_UPD:
1446 case ARM::VLD2d16_UPD:
1447 case ARM::VLD2d32_UPD:
1448 case ARM::VLD2q8_UPD:
1449 case ARM::VLD2q16_UPD:
1450 case ARM::VLD2q32_UPD:
1451 case ARM::VLD2b8_UPD:
1452 case ARM::VLD2b16_UPD:
1453 case ARM::VLD2b32_UPD:
1454 case ARM::VLD3d8_UPD:
1455 case ARM::VLD3d16_UPD:
1456 case ARM::VLD3d32_UPD:
1457 case ARM::VLD3q8_UPD:
1458 case ARM::VLD3q16_UPD:
1459 case ARM::VLD3q32_UPD:
1460 case ARM::VLD4d8_UPD:
1461 case ARM::VLD4d16_UPD:
1462 case ARM::VLD4d32_UPD:
1463 case ARM::VLD4q8_UPD:
1464 case ARM::VLD4q16_UPD:
1465 case ARM::VLD4q32_UPD:
1466 DecodeGPRRegisterClass(Inst, wb, Address, Decoder);
1472 // AddrMode6 Base (register+alignment)
1473 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder);
1475 // AddrMode6 Offset (register)
1477 Inst.addOperand(MCOperand::CreateReg(0));
1479 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1484 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1485 uint64_t Address, const void *Decoder) {
1486 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1487 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1488 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1489 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1490 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1491 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1493 // Writeback Operand
1494 switch (Inst.getOpcode()) {
1495 case ARM::VST1d8_UPD:
1496 case ARM::VST1d16_UPD:
1497 case ARM::VST1d32_UPD:
1498 case ARM::VST1d64_UPD:
1499 case ARM::VST1q8_UPD:
1500 case ARM::VST1q16_UPD:
1501 case ARM::VST1q32_UPD:
1502 case ARM::VST1q64_UPD:
1503 case ARM::VST1d8T_UPD:
1504 case ARM::VST1d16T_UPD:
1505 case ARM::VST1d32T_UPD:
1506 case ARM::VST1d64T_UPD:
1507 case ARM::VST1d8Q_UPD:
1508 case ARM::VST1d16Q_UPD:
1509 case ARM::VST1d32Q_UPD:
1510 case ARM::VST1d64Q_UPD:
1511 case ARM::VST2d8_UPD:
1512 case ARM::VST2d16_UPD:
1513 case ARM::VST2d32_UPD:
1514 case ARM::VST2q8_UPD:
1515 case ARM::VST2q16_UPD:
1516 case ARM::VST2q32_UPD:
1517 case ARM::VST2b8_UPD:
1518 case ARM::VST2b16_UPD:
1519 case ARM::VST2b32_UPD:
1520 case ARM::VST3d8_UPD:
1521 case ARM::VST3d16_UPD:
1522 case ARM::VST3d32_UPD:
1523 case ARM::VST3q8_UPD:
1524 case ARM::VST3q16_UPD:
1525 case ARM::VST3q32_UPD:
1526 case ARM::VST4d8_UPD:
1527 case ARM::VST4d16_UPD:
1528 case ARM::VST4d32_UPD:
1529 case ARM::VST4q8_UPD:
1530 case ARM::VST4q16_UPD:
1531 case ARM::VST4q32_UPD:
1532 DecodeGPRRegisterClass(Inst, wb, Address, Decoder);
1538 // AddrMode6 Base (register+alignment)
1539 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder);
1541 // AddrMode6 Offset (register)
1543 Inst.addOperand(MCOperand::CreateReg(0));
1545 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1547 // First input register
1548 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1550 // Second input register
1551 switch (Inst.getOpcode()) {
1556 case ARM::VST1q8_UPD:
1557 case ARM::VST1q16_UPD:
1558 case ARM::VST1q32_UPD:
1559 case ARM::VST1q64_UPD:
1564 case ARM::VST1d8T_UPD:
1565 case ARM::VST1d16T_UPD:
1566 case ARM::VST1d32T_UPD:
1567 case ARM::VST1d64T_UPD:
1572 case ARM::VST1d8Q_UPD:
1573 case ARM::VST1d16Q_UPD:
1574 case ARM::VST1d32Q_UPD:
1575 case ARM::VST1d64Q_UPD:
1579 case ARM::VST2d8_UPD:
1580 case ARM::VST2d16_UPD:
1581 case ARM::VST2d32_UPD:
1585 case ARM::VST2q8_UPD:
1586 case ARM::VST2q16_UPD:
1587 case ARM::VST2q32_UPD:
1591 case ARM::VST3d8_UPD:
1592 case ARM::VST3d16_UPD:
1593 case ARM::VST3d32_UPD:
1597 case ARM::VST4d8_UPD:
1598 case ARM::VST4d16_UPD:
1599 case ARM::VST4d32_UPD:
1600 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder);
1605 case ARM::VST2b8_UPD:
1606 case ARM::VST2b16_UPD:
1607 case ARM::VST2b32_UPD:
1611 case ARM::VST3q8_UPD:
1612 case ARM::VST3q16_UPD:
1613 case ARM::VST3q32_UPD:
1617 case ARM::VST4q8_UPD:
1618 case ARM::VST4q16_UPD:
1619 case ARM::VST4q32_UPD:
1620 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
1626 // Third input register
1627 switch (Inst.getOpcode()) {
1632 case ARM::VST1d8T_UPD:
1633 case ARM::VST1d16T_UPD:
1634 case ARM::VST1d32T_UPD:
1635 case ARM::VST1d64T_UPD:
1640 case ARM::VST1d8Q_UPD:
1641 case ARM::VST1d16Q_UPD:
1642 case ARM::VST1d32Q_UPD:
1643 case ARM::VST1d64Q_UPD:
1647 case ARM::VST2q8_UPD:
1648 case ARM::VST2q16_UPD:
1649 case ARM::VST2q32_UPD:
1653 case ARM::VST3d8_UPD:
1654 case ARM::VST3d16_UPD:
1655 case ARM::VST3d32_UPD:
1659 case ARM::VST4d8_UPD:
1660 case ARM::VST4d16_UPD:
1661 case ARM::VST4d32_UPD:
1662 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
1667 case ARM::VST3q8_UPD:
1668 case ARM::VST3q16_UPD:
1669 case ARM::VST3q32_UPD:
1673 case ARM::VST4q8_UPD:
1674 case ARM::VST4q16_UPD:
1675 case ARM::VST4q32_UPD:
1676 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder);
1682 // Fourth input register
1683 switch (Inst.getOpcode()) {
1688 case ARM::VST1d8Q_UPD:
1689 case ARM::VST1d16Q_UPD:
1690 case ARM::VST1d32Q_UPD:
1691 case ARM::VST1d64Q_UPD:
1695 case ARM::VST2q8_UPD:
1696 case ARM::VST2q16_UPD:
1697 case ARM::VST2q32_UPD:
1701 case ARM::VST4d8_UPD:
1702 case ARM::VST4d16_UPD:
1703 case ARM::VST4d32_UPD:
1704 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder);
1709 case ARM::VST4q8_UPD:
1710 case ARM::VST4q16_UPD:
1711 case ARM::VST4q32_UPD:
1712 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder);
1721 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1722 uint64_t Address, const void *Decoder) {
1723 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1724 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1725 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1726 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1727 unsigned align = fieldFromInstruction32(Insn, 4, 1);
1728 unsigned size = fieldFromInstruction32(Insn, 6, 2);
1729 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
1731 align *= (1 << size);
1733 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1734 if (regs == 2) DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder);
1735 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1737 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1738 Inst.addOperand(MCOperand::CreateImm(align));
1741 Inst.addOperand(MCOperand::CreateReg(0));
1743 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1748 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1749 uint64_t Address, const void *Decoder) {
1750 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1751 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1752 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1753 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1754 unsigned align = fieldFromInstruction32(Insn, 4, 1);
1755 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
1756 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
1759 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1760 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder);
1761 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1763 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1764 Inst.addOperand(MCOperand::CreateImm(align));
1767 Inst.addOperand(MCOperand::CreateReg(0));
1769 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1774 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1775 uint64_t Address, const void *Decoder) {
1776 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1777 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1778 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1779 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1780 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
1782 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1783 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder);
1784 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder);
1785 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1787 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1788 Inst.addOperand(MCOperand::CreateImm(0));
1791 Inst.addOperand(MCOperand::CreateReg(0));
1793 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1798 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1799 uint64_t Address, const void *Decoder) {
1800 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1801 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1802 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1803 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1804 unsigned size = fieldFromInstruction32(Insn, 6, 2);
1805 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
1806 unsigned align = fieldFromInstruction32(Insn, 4, 1);
1821 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1822 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder);
1823 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder);
1824 DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder);
1825 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1827 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
1828 Inst.addOperand(MCOperand::CreateImm(align));
1831 Inst.addOperand(MCOperand::CreateReg(0));
1833 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
1838 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1839 uint64_t Address, const void *Decoder) {
1840 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1841 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1842 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
1843 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
1844 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
1845 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
1846 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
1847 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
1850 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder);
1852 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1854 Inst.addOperand(MCOperand::CreateImm(imm));
1856 switch (Inst.getOpcode()) {
1857 case ARM::VORRiv4i16:
1858 case ARM::VORRiv2i32:
1859 case ARM::VBICiv4i16:
1860 case ARM::VBICiv2i32:
1861 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1863 case ARM::VORRiv8i16:
1864 case ARM::VORRiv4i32:
1865 case ARM::VBICiv8i16:
1866 case ARM::VBICiv4i32:
1867 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder);
1877 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
1878 uint64_t Address, const void *Decoder) {
1879 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1880 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1881 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1882 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
1883 unsigned size = fieldFromInstruction32(Insn, 18, 2);
1885 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder);
1886 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder);
1887 Inst.addOperand(MCOperand::CreateImm(8 << size));
1892 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
1893 uint64_t Address, const void *Decoder) {
1894 Inst.addOperand(MCOperand::CreateImm(8 - Val));
1898 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
1899 uint64_t Address, const void *Decoder) {
1900 Inst.addOperand(MCOperand::CreateImm(16 - Val));
1904 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
1905 uint64_t Address, const void *Decoder) {
1906 Inst.addOperand(MCOperand::CreateImm(32 - Val));
1910 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
1911 uint64_t Address, const void *Decoder) {
1912 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1916 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
1917 uint64_t Address, const void *Decoder) {
1918 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1919 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1920 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1921 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
1922 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1923 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
1924 unsigned op = fieldFromInstruction32(Insn, 6, 1);
1925 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
1927 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
1928 if (op) DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); // Writeback
1930 for (unsigned i = 0; i < length; ++i)
1931 DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder);
1933 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder);
1938 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
1939 uint64_t Address, const void *Decoder) {
1940 // The immediate needs to be a fully instantiated float. However, the
1941 // auto-generated decoder is only able to fill in some of the bits
1942 // necessary. For instance, the 'b' bit is replicated multiple times,
1943 // and is even present in inverted form in one bit. We do a little
1944 // binary parsing here to fill in those missing bits, and then
1945 // reinterpret it all as a float.
1951 fp_conv.integer = Val;
1952 uint32_t b = fieldFromInstruction32(Val, 25, 1);
1953 fp_conv.integer |= b << 26;
1954 fp_conv.integer |= b << 27;
1955 fp_conv.integer |= b << 28;
1956 fp_conv.integer |= b << 29;
1957 fp_conv.integer |= (~b & 0x1) << 30;
1959 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
1963 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
1964 uint64_t Address, const void *Decoder) {
1965 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
1966 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
1968 DecodetGPRRegisterClass(Inst, dst, Address, Decoder);
1970 if (Inst.getOpcode() == ARM::tADR)
1971 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
1972 else if (Inst.getOpcode() == ARM::tADDrSPi)
1973 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
1977 Inst.addOperand(MCOperand::CreateImm(imm));
1981 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
1982 uint64_t Address, const void *Decoder) {
1983 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
1987 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
1988 uint64_t Address, const void *Decoder) {
1989 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
1993 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
1994 uint64_t Address, const void *Decoder) {
1995 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
1999 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2000 uint64_t Address, const void *Decoder) {
2001 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2002 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2004 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder);
2005 DecodetGPRRegisterClass(Inst, Rm, Address, Decoder);
2010 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2011 uint64_t Address, const void *Decoder) {
2012 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2013 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2015 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder);
2016 Inst.addOperand(MCOperand::CreateImm(imm));
2021 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2022 uint64_t Address, const void *Decoder) {
2023 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2028 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2029 uint64_t Address, const void *Decoder) {
2030 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2031 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2036 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2037 uint64_t Address, const void *Decoder) {
2038 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2039 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2040 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2042 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
2043 DecoderGPRRegisterClass(Inst, Rm, Address, Decoder);
2044 Inst.addOperand(MCOperand::CreateImm(imm));
2049 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2050 uint64_t Address, const void *Decoder) {
2051 if (Inst.getOpcode() != ARM::t2PLDs) {
2052 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2053 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder);
2056 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2058 switch (Inst.getOpcode()) {
2060 Inst.setOpcode(ARM::t2LDRBpci);
2063 Inst.setOpcode(ARM::t2LDRHpci);
2066 Inst.setOpcode(ARM::t2LDRSHpci);
2069 Inst.setOpcode(ARM::t2LDRSBpci);
2072 Inst.setOpcode(ARM::t2PLDi12);
2073 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2079 int imm = fieldFromInstruction32(Insn, 0, 12);
2080 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2081 Inst.addOperand(MCOperand::CreateImm(imm));
2086 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2087 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2088 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2089 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder);
2094 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2095 uint64_t Address, const void *Decoder) {
2096 int imm = Val & 0xFF;
2097 if (!(Val & 0x100)) imm *= -1;
2098 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2103 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2104 uint64_t Address, const void *Decoder) {
2105 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2106 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2108 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
2109 DecodeT2Imm8S4(Inst, imm, Address, Decoder);
2114 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2115 uint64_t Address, const void *Decoder) {
2116 int imm = Val & 0xFF;
2117 if (!(Val & 0x100)) imm *= -1;
2118 Inst.addOperand(MCOperand::CreateImm(imm));
2124 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2125 uint64_t Address, const void *Decoder) {
2126 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2127 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2129 // Some instructions always use an additive offset.
2130 switch (Inst.getOpcode()) {
2142 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
2143 DecodeT2Imm8(Inst, imm, Address, Decoder);
2149 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2150 uint64_t Address, const void *Decoder) {
2151 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2152 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2154 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
2155 Inst.addOperand(MCOperand::CreateImm(imm));
2161 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2162 uint64_t Address, const void *Decoder) {
2163 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2165 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2166 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2167 Inst.addOperand(MCOperand::CreateImm(imm));
2172 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2173 uint64_t Address, const void *Decoder) {
2174 if (Inst.getOpcode() == ARM::tADDrSP) {
2175 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2176 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2178 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder);
2179 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2180 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder);
2181 } else if (Inst.getOpcode() == ARM::tADDspr) {
2182 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2184 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2185 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2186 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
2192 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2193 uint64_t Address, const void *Decoder) {
2194 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2195 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2197 Inst.addOperand(MCOperand::CreateImm(imod));
2198 Inst.addOperand(MCOperand::CreateImm(flags));
2203 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2204 uint64_t Address, const void *Decoder) {
2205 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2206 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2208 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
2209 Inst.addOperand(MCOperand::CreateImm(add));
2214 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2215 uint64_t Address, const void *Decoder) {
2216 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2220 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2221 uint64_t Address, const void *Decoder) {
2222 if (Val == 0xA || Val == 0xB)
2225 Inst.addOperand(MCOperand::CreateImm(Val));
2229 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
2230 uint64_t Address, const void *Decoder) {
2232 Inst.addOperand(MCOperand::CreateImm(32));
2234 Inst.addOperand(MCOperand::CreateImm(Val));
2238 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2239 uint64_t Address, const void *Decoder) {
2240 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2241 if (pred == 0xE || pred == 0xF) {
2242 unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2247 Inst.setOpcode(ARM::t2DSB);
2250 Inst.setOpcode(ARM::t2DMB);
2253 Inst.setOpcode(ARM::t2ISB);
2257 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2258 Inst.addOperand(MCOperand::CreateImm(imm));
2262 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2263 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2264 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2265 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2266 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2268 DecodeT2BROperand(Inst, brtarget, Address, Decoder);
2269 if (!DecodePredicateOperand(Inst, pred, Address, Decoder))
2275 // Decode a shifted immediate operand. These basically consist
2276 // of an 8-bit value, and a 4-bit directive that specifies either
2277 // a splat operation or a rotation.
2278 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2279 uint64_t Address, const void *Decoder) {
2280 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2282 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2283 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2286 Inst.addOperand(MCOperand::CreateImm(imm));
2289 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2292 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2295 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2300 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2301 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2302 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2303 Inst.addOperand(MCOperand::CreateImm(imm));
2309 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2310 uint64_t Address, const void *Decoder){
2311 Inst.addOperand(MCOperand::CreateImm(Val << 1));
2315 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2316 uint64_t Address, const void *Decoder){
2317 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2321 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val,
2322 uint64_t Address, const void *Decoder) {
2323 bool isImm = fieldFromInstruction32(Val, 9, 1);
2324 bool isAdd = fieldFromInstruction32(Val, 8, 1);
2325 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2328 DecodeGPRRegisterClass(Inst, imm, Address, Decoder);
2329 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8));
2331 Inst.addOperand(MCOperand::CreateReg(0));
2332 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8)));