1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
13 #include "ARMRegisterInfo.h"
14 #include "ARMSubtarget.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/EDInstInfo.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// ARMDisassembler - ARM disassembler for all ARM platforms.
35 class ARMDisassembler : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 ARMDisassembler(const MCSubtargetInfo &STI) :
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
49 const MemoryObject ®ion,
52 raw_ostream &cStream) const;
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60 class ThumbDisassembler : public MCDisassembler {
62 /// Constructor - Initializes the disassembler.
64 ThumbDisassembler(const MCSubtargetInfo &STI) :
68 ~ThumbDisassembler() {
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
74 const MemoryObject ®ion,
77 raw_ostream &cStream) const;
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
82 mutable std::vector<unsigned> ITBlock;
83 DecodeStatus AddThumbPredicate(MCInst&) const;
84 void UpdateThumbVFPPredicate(MCInst&) const;
88 static bool Check(DecodeStatus &Out, DecodeStatus In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
93 case MCDisassembler::SoftFail:
96 case MCDisassembler::Fail:
104 // Forward declare these because the autogenerated code will reference them.
105 // Definitions are further down.
106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
112 uint64_t Address, const void *Decoder);
113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
114 uint64_t Address, const void *Decoder);
115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116 uint64_t Address, const void *Decoder);
117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
118 uint64_t Address, const void *Decoder);
119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
120 uint64_t Address, const void *Decoder);
121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
122 uint64_t Address, const void *Decoder);
123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
126 const void *Decoder);
127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
128 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
131 uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
144 uint64_t Address, const void *Decoder);
145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
146 uint64_t Address, const void *Decoder);
147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
150 const void *Decoder);
151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
158 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
163 const void *Decoder);
164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
253 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
316 uint64_t Address, const void *Decoder);
320 #include "ARMGenDisassemblerTables.inc"
321 #include "ARMGenInstrInfo.inc"
322 #include "ARMGenEDInfo.inc"
324 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
325 return new ARMDisassembler(STI);
328 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
329 return new ThumbDisassembler(STI);
332 EDInstInfo *ARMDisassembler::getEDInfo() const {
336 EDInstInfo *ThumbDisassembler::getEDInfo() const {
340 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
341 const MemoryObject &Region,
344 raw_ostream &cs) const {
349 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
350 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
352 // We want to read exactly 4 bytes of data.
353 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
355 return MCDisassembler::Fail;
358 // Encoded as a small-endian 32-bit word in the stream.
359 uint32_t insn = (bytes[3] << 24) |
364 // Calling the auto-generated decoder function.
365 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
366 if (result != MCDisassembler::Fail) {
371 // VFP and NEON instructions, similarly, are shared between ARM
374 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
375 if (result != MCDisassembler::Fail) {
381 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
382 if (result != MCDisassembler::Fail) {
384 // Add a fake predicate operand, because we share these instruction
385 // definitions with Thumb2 where these instructions are predicable.
386 if (!DecodePredicateOperand(MI, 0xE, Address, this))
387 return MCDisassembler::Fail;
392 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
393 if (result != MCDisassembler::Fail) {
395 // Add a fake predicate operand, because we share these instruction
396 // definitions with Thumb2 where these instructions are predicable.
397 if (!DecodePredicateOperand(MI, 0xE, Address, this))
398 return MCDisassembler::Fail;
403 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
404 if (result != MCDisassembler::Fail) {
406 // Add a fake predicate operand, because we share these instruction
407 // definitions with Thumb2 where these instructions are predicable.
408 if (!DecodePredicateOperand(MI, 0xE, Address, this))
409 return MCDisassembler::Fail;
416 return MCDisassembler::Fail;
420 extern const MCInstrDesc ARMInsts[];
423 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
424 /// immediate Value in the MCInst. The immediate Value has had any PC
425 /// adjustment made by the caller. If the instruction is a branch instruction
426 /// then isBranch is true, else false. If the getOpInfo() function was set as
427 /// part of the setupForSymbolicDisassembly() call then that function is called
428 /// to get any symbolic information at the Address for this instruction. If
429 /// that returns non-zero then the symbolic information it returns is used to
430 /// create an MCExpr and that is added as an operand to the MCInst. If
431 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
432 /// Value is done and if a symbol is found an MCExpr is created with that, else
433 /// an MCExpr with Value is created. This function returns true if it adds an
434 /// operand to the MCInst and false otherwise.
435 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
436 bool isBranch, uint64_t InstSize,
437 MCInst &MI, const void *Decoder) {
438 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
439 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
443 struct LLVMOpInfo1 SymbolicOp;
444 SymbolicOp.Value = Value;
445 void *DisInfo = Dis->getDisInfoBlock();
446 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
448 LLVMSymbolLookupCallback SymbolLookUp =
449 Dis->getLLVMSymbolLookupCallback();
451 uint64_t ReferenceType;
452 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
453 const char *ReferenceName;
454 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
457 SymbolicOp.AddSymbol.Name = Name;
458 SymbolicOp.AddSymbol.Present = true;
459 SymbolicOp.Value = 0;
462 SymbolicOp.Value = Value;
464 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
465 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
476 MCContext *Ctx = Dis->getMCContext();
477 const MCExpr *Add = NULL;
478 if (SymbolicOp.AddSymbol.Present) {
479 if (SymbolicOp.AddSymbol.Name) {
480 StringRef Name(SymbolicOp.AddSymbol.Name);
481 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
482 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
484 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
488 const MCExpr *Sub = NULL;
489 if (SymbolicOp.SubtractSymbol.Present) {
490 if (SymbolicOp.SubtractSymbol.Name) {
491 StringRef Name(SymbolicOp.SubtractSymbol.Name);
492 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
493 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
495 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
499 const MCExpr *Off = NULL;
500 if (SymbolicOp.Value != 0)
501 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
507 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
509 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
511 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
516 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
523 Expr = MCConstantExpr::Create(0, *Ctx);
526 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
529 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
530 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
531 MI.addOperand(MCOperand::CreateExpr(Expr));
533 assert(0 && "bad SymbolicOp.VariantKind");
538 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
539 /// referenced by a load instruction with the base register that is the Pc.
540 /// These can often be values in a literal pool near the Address of the
541 /// instruction. The Address of the instruction and its immediate Value are
542 /// used as a possible literal pool entry. The SymbolLookUp call back will
543 /// return the name of a symbol referenced by the the literal pool's entry if
544 /// the referenced address is that of a symbol. Or it will return a pointer to
545 /// a literal 'C' string if the referenced address of the literal pool's entry
546 /// is an address into a section with 'C' string literals.
547 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
548 const void *Decoder) {
549 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
550 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
552 void *DisInfo = Dis->getDisInfoBlock();
553 uint64_t ReferenceType;
554 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
555 const char *ReferenceName;
556 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
557 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
558 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
559 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
563 // Thumb1 instructions don't have explicit S bits. Rather, they
564 // implicitly set CPSR. Since it's not represented in the encoding, the
565 // auto-generated decoder won't inject the CPSR operand. We need to fix
566 // that as a post-pass.
567 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
568 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
569 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
570 MCInst::iterator I = MI.begin();
571 for (unsigned i = 0; i < NumOps; ++i, ++I) {
572 if (I == MI.end()) break;
573 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
574 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
575 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
583 // Most Thumb instructions don't have explicit predicates in the
584 // encoding, but rather get their predicates from IT context. We need
585 // to fix up the predicate operands using this context information as a
587 MCDisassembler::DecodeStatus
588 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
589 MCDisassembler::DecodeStatus S = Success;
591 // A few instructions actually have predicates encoded in them. Don't
592 // try to overwrite it if we're seeing one of those.
593 switch (MI.getOpcode()) {
604 // Some instructions (mostly conditional branches) are not
605 // allowed in IT blocks.
606 if (!ITBlock.empty())
615 // Some instructions (mostly unconditional branches) can
616 // only appears at the end of, or outside of, an IT.
617 if (ITBlock.size() > 1)
624 // If we're in an IT block, base the predicate on that. Otherwise,
625 // assume a predicate of AL.
627 if (!ITBlock.empty()) {
635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
637 MCInst::iterator I = MI.begin();
638 for (unsigned i = 0; i < NumOps; ++i, ++I) {
639 if (I == MI.end()) break;
640 if (OpInfo[i].isPredicate()) {
641 I = MI.insert(I, MCOperand::CreateImm(CC));
644 MI.insert(I, MCOperand::CreateReg(0));
646 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
651 I = MI.insert(I, MCOperand::CreateImm(CC));
654 MI.insert(I, MCOperand::CreateReg(0));
656 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
661 // Thumb VFP instructions are a special case. Because we share their
662 // encodings between ARM and Thumb modes, and they are predicable in ARM
663 // mode, the auto-generated decoder will give them an (incorrect)
664 // predicate operand. We need to rewrite these operands based on the IT
665 // context as a post-pass.
666 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
668 if (!ITBlock.empty()) {
674 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
675 MCInst::iterator I = MI.begin();
676 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
677 for (unsigned i = 0; i < NumOps; ++i, ++I) {
678 if (OpInfo[i].isPredicate() ) {
684 I->setReg(ARM::CPSR);
690 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
691 const MemoryObject &Region,
694 raw_ostream &cs) const {
699 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
700 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
702 // We want to read exactly 2 bytes of data.
703 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
705 return MCDisassembler::Fail;
708 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
709 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
710 if (result != MCDisassembler::Fail) {
712 Check(result, AddThumbPredicate(MI));
717 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
720 bool InITBlock = !ITBlock.empty();
721 Check(result, AddThumbPredicate(MI));
722 AddThumb1SBit(MI, InITBlock);
727 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
728 if (result != MCDisassembler::Fail) {
731 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
732 // the Thumb predicate.
733 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
734 result = MCDisassembler::SoftFail;
736 Check(result, AddThumbPredicate(MI));
738 // If we find an IT instruction, we need to parse its condition
739 // code and mask operands so that we can apply them correctly
740 // to the subsequent instructions.
741 if (MI.getOpcode() == ARM::t2IT) {
743 // (3 - the number of trailing zeros) is the number of then / else.
744 unsigned firstcond = MI.getOperand(0).getImm();
745 unsigned Mask = MI.getOperand(1).getImm();
746 unsigned CondBit0 = Mask >> 4 & 1;
747 unsigned NumTZ = CountTrailingZeros_32(Mask);
748 assert(NumTZ <= 3 && "Invalid IT mask!");
749 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
750 bool T = ((Mask >> Pos) & 1) == CondBit0;
752 ITBlock.insert(ITBlock.begin(), firstcond);
754 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
757 ITBlock.push_back(firstcond);
763 // We want to read exactly 4 bytes of data.
764 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
766 return MCDisassembler::Fail;
769 uint32_t insn32 = (bytes[3] << 8) |
774 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
775 if (result != MCDisassembler::Fail) {
777 bool InITBlock = ITBlock.size();
778 Check(result, AddThumbPredicate(MI));
779 AddThumb1SBit(MI, InITBlock);
784 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
785 if (result != MCDisassembler::Fail) {
787 Check(result, AddThumbPredicate(MI));
792 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
793 if (result != MCDisassembler::Fail) {
795 UpdateThumbVFPPredicate(MI);
800 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
801 if (result != MCDisassembler::Fail) {
803 Check(result, AddThumbPredicate(MI));
807 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
809 uint32_t NEONLdStInsn = insn32;
810 NEONLdStInsn &= 0xF0FFFFFF;
811 NEONLdStInsn |= 0x04000000;
812 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
813 if (result != MCDisassembler::Fail) {
815 Check(result, AddThumbPredicate(MI));
820 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
822 uint32_t NEONDataInsn = insn32;
823 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
824 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
825 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
826 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
827 if (result != MCDisassembler::Fail) {
829 Check(result, AddThumbPredicate(MI));
835 return MCDisassembler::Fail;
839 extern "C" void LLVMInitializeARMDisassembler() {
840 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
841 createARMDisassembler);
842 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
843 createThumbDisassembler);
846 static const unsigned GPRDecoderTable[] = {
847 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
848 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
849 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
850 ARM::R12, ARM::SP, ARM::LR, ARM::PC
853 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
854 uint64_t Address, const void *Decoder) {
856 return MCDisassembler::Fail;
858 unsigned Register = GPRDecoderTable[RegNo];
859 Inst.addOperand(MCOperand::CreateReg(Register));
860 return MCDisassembler::Success;
864 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
865 uint64_t Address, const void *Decoder) {
866 if (RegNo == 15) return MCDisassembler::Fail;
867 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
870 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
871 uint64_t Address, const void *Decoder) {
873 return MCDisassembler::Fail;
874 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
877 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
878 uint64_t Address, const void *Decoder) {
879 unsigned Register = 0;
900 return MCDisassembler::Fail;
903 Inst.addOperand(MCOperand::CreateReg(Register));
904 return MCDisassembler::Success;
907 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
908 uint64_t Address, const void *Decoder) {
909 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
910 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
913 static const unsigned SPRDecoderTable[] = {
914 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
915 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
916 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
917 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
918 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
919 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
920 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
921 ARM::S28, ARM::S29, ARM::S30, ARM::S31
924 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
925 uint64_t Address, const void *Decoder) {
927 return MCDisassembler::Fail;
929 unsigned Register = SPRDecoderTable[RegNo];
930 Inst.addOperand(MCOperand::CreateReg(Register));
931 return MCDisassembler::Success;
934 static const unsigned DPRDecoderTable[] = {
935 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
936 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
937 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
938 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
939 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
940 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
941 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
942 ARM::D28, ARM::D29, ARM::D30, ARM::D31
945 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
946 uint64_t Address, const void *Decoder) {
948 return MCDisassembler::Fail;
950 unsigned Register = DPRDecoderTable[RegNo];
951 Inst.addOperand(MCOperand::CreateReg(Register));
952 return MCDisassembler::Success;
955 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
956 uint64_t Address, const void *Decoder) {
958 return MCDisassembler::Fail;
959 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
963 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
964 uint64_t Address, const void *Decoder) {
966 return MCDisassembler::Fail;
967 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
970 static const unsigned QPRDecoderTable[] = {
971 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
972 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
973 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
974 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
978 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
979 uint64_t Address, const void *Decoder) {
981 return MCDisassembler::Fail;
984 unsigned Register = QPRDecoderTable[RegNo];
985 Inst.addOperand(MCOperand::CreateReg(Register));
986 return MCDisassembler::Success;
989 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
990 uint64_t Address, const void *Decoder) {
991 if (Val == 0xF) return MCDisassembler::Fail;
992 // AL predicate is not allowed on Thumb1 branches.
993 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
994 return MCDisassembler::Fail;
995 Inst.addOperand(MCOperand::CreateImm(Val));
996 if (Val == ARMCC::AL) {
997 Inst.addOperand(MCOperand::CreateReg(0));
999 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1000 return MCDisassembler::Success;
1003 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
1004 uint64_t Address, const void *Decoder) {
1006 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1008 Inst.addOperand(MCOperand::CreateReg(0));
1009 return MCDisassembler::Success;
1012 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
1013 uint64_t Address, const void *Decoder) {
1014 uint32_t imm = Val & 0xFF;
1015 uint32_t rot = (Val & 0xF00) >> 7;
1016 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1017 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1018 return MCDisassembler::Success;
1021 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
1022 uint64_t Address, const void *Decoder) {
1023 DecodeStatus S = MCDisassembler::Success;
1025 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1026 unsigned type = fieldFromInstruction32(Val, 5, 2);
1027 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1029 // Register-immediate
1030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1031 return MCDisassembler::Fail;
1033 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1036 Shift = ARM_AM::lsl;
1039 Shift = ARM_AM::lsr;
1042 Shift = ARM_AM::asr;
1045 Shift = ARM_AM::ror;
1049 if (Shift == ARM_AM::ror && imm == 0)
1050 Shift = ARM_AM::rrx;
1052 unsigned Op = Shift | (imm << 3);
1053 Inst.addOperand(MCOperand::CreateImm(Op));
1058 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
1059 uint64_t Address, const void *Decoder) {
1060 DecodeStatus S = MCDisassembler::Success;
1062 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1063 unsigned type = fieldFromInstruction32(Val, 5, 2);
1064 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1066 // Register-register
1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1068 return MCDisassembler::Fail;
1069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1070 return MCDisassembler::Fail;
1072 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1075 Shift = ARM_AM::lsl;
1078 Shift = ARM_AM::lsr;
1081 Shift = ARM_AM::asr;
1084 Shift = ARM_AM::ror;
1088 Inst.addOperand(MCOperand::CreateImm(Shift));
1093 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
1094 uint64_t Address, const void *Decoder) {
1095 DecodeStatus S = MCDisassembler::Success;
1097 bool writebackLoad = false;
1098 unsigned writebackReg = 0;
1099 switch (Inst.getOpcode()) {
1102 case ARM::LDMIA_UPD:
1103 case ARM::LDMDB_UPD:
1104 case ARM::LDMIB_UPD:
1105 case ARM::LDMDA_UPD:
1106 case ARM::t2LDMIA_UPD:
1107 case ARM::t2LDMDB_UPD:
1108 writebackLoad = true;
1109 writebackReg = Inst.getOperand(0).getReg();
1113 // Empty register lists are not allowed.
1114 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1115 for (unsigned i = 0; i < 16; ++i) {
1116 if (Val & (1 << i)) {
1117 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1118 return MCDisassembler::Fail;
1119 // Writeback not allowed if Rn is in the target list.
1120 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1121 Check(S, MCDisassembler::SoftFail);
1128 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1129 uint64_t Address, const void *Decoder) {
1130 DecodeStatus S = MCDisassembler::Success;
1132 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1133 unsigned regs = Val & 0xFF;
1135 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1136 return MCDisassembler::Fail;
1137 for (unsigned i = 0; i < (regs - 1); ++i) {
1138 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1139 return MCDisassembler::Fail;
1145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1146 uint64_t Address, const void *Decoder) {
1147 DecodeStatus S = MCDisassembler::Success;
1149 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1150 unsigned regs = (Val & 0xFF) / 2;
1152 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1153 return MCDisassembler::Fail;
1154 for (unsigned i = 0; i < (regs - 1); ++i) {
1155 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1156 return MCDisassembler::Fail;
1162 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
1163 uint64_t Address, const void *Decoder) {
1164 // This operand encodes a mask of contiguous zeros between a specified MSB
1165 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1166 // the mask of all bits LSB-and-lower, and then xor them to create
1167 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1168 // create the final mask.
1169 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1170 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1172 DecodeStatus S = MCDisassembler::Success;
1173 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1175 uint32_t msb_mask = 0xFFFFFFFF;
1176 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1177 uint32_t lsb_mask = (1U << lsb) - 1;
1179 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1183 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
1184 uint64_t Address, const void *Decoder) {
1185 DecodeStatus S = MCDisassembler::Success;
1187 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1188 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1189 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1190 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1191 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1192 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1194 switch (Inst.getOpcode()) {
1195 case ARM::LDC_OFFSET:
1198 case ARM::LDC_OPTION:
1199 case ARM::LDCL_OFFSET:
1201 case ARM::LDCL_POST:
1202 case ARM::LDCL_OPTION:
1203 case ARM::STC_OFFSET:
1206 case ARM::STC_OPTION:
1207 case ARM::STCL_OFFSET:
1209 case ARM::STCL_POST:
1210 case ARM::STCL_OPTION:
1211 case ARM::t2LDC_OFFSET:
1212 case ARM::t2LDC_PRE:
1213 case ARM::t2LDC_POST:
1214 case ARM::t2LDC_OPTION:
1215 case ARM::t2LDCL_OFFSET:
1216 case ARM::t2LDCL_PRE:
1217 case ARM::t2LDCL_POST:
1218 case ARM::t2LDCL_OPTION:
1219 case ARM::t2STC_OFFSET:
1220 case ARM::t2STC_PRE:
1221 case ARM::t2STC_POST:
1222 case ARM::t2STC_OPTION:
1223 case ARM::t2STCL_OFFSET:
1224 case ARM::t2STCL_PRE:
1225 case ARM::t2STCL_POST:
1226 case ARM::t2STCL_OPTION:
1227 if (coproc == 0xA || coproc == 0xB)
1228 return MCDisassembler::Fail;
1234 Inst.addOperand(MCOperand::CreateImm(coproc));
1235 Inst.addOperand(MCOperand::CreateImm(CRd));
1236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1237 return MCDisassembler::Fail;
1239 switch (Inst.getOpcode()) {
1240 case ARM::t2LDC2_OFFSET:
1241 case ARM::t2LDC2L_OFFSET:
1242 case ARM::t2LDC2_PRE:
1243 case ARM::t2LDC2L_PRE:
1244 case ARM::t2STC2_OFFSET:
1245 case ARM::t2STC2L_OFFSET:
1246 case ARM::t2STC2_PRE:
1247 case ARM::t2STC2L_PRE:
1248 case ARM::LDC2_OFFSET:
1249 case ARM::LDC2L_OFFSET:
1251 case ARM::LDC2L_PRE:
1252 case ARM::STC2_OFFSET:
1253 case ARM::STC2L_OFFSET:
1255 case ARM::STC2L_PRE:
1256 case ARM::t2LDC_OFFSET:
1257 case ARM::t2LDCL_OFFSET:
1258 case ARM::t2LDC_PRE:
1259 case ARM::t2LDCL_PRE:
1260 case ARM::t2STC_OFFSET:
1261 case ARM::t2STCL_OFFSET:
1262 case ARM::t2STC_PRE:
1263 case ARM::t2STCL_PRE:
1264 case ARM::LDC_OFFSET:
1265 case ARM::LDCL_OFFSET:
1268 case ARM::STC_OFFSET:
1269 case ARM::STCL_OFFSET:
1272 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1273 Inst.addOperand(MCOperand::CreateImm(imm));
1275 case ARM::t2LDC2_POST:
1276 case ARM::t2LDC2L_POST:
1277 case ARM::t2STC2_POST:
1278 case ARM::t2STC2L_POST:
1279 case ARM::LDC2_POST:
1280 case ARM::LDC2L_POST:
1281 case ARM::STC2_POST:
1282 case ARM::STC2L_POST:
1283 case ARM::t2LDC_POST:
1284 case ARM::t2LDCL_POST:
1285 case ARM::t2STC_POST:
1286 case ARM::t2STCL_POST:
1288 case ARM::LDCL_POST:
1290 case ARM::STCL_POST:
1294 // The 'option' variant doesn't encode 'U' in the immediate since
1295 // the immediate is unsigned [0,255].
1296 Inst.addOperand(MCOperand::CreateImm(imm));
1300 switch (Inst.getOpcode()) {
1301 case ARM::LDC_OFFSET:
1304 case ARM::LDC_OPTION:
1305 case ARM::LDCL_OFFSET:
1307 case ARM::LDCL_POST:
1308 case ARM::LDCL_OPTION:
1309 case ARM::STC_OFFSET:
1312 case ARM::STC_OPTION:
1313 case ARM::STCL_OFFSET:
1315 case ARM::STCL_POST:
1316 case ARM::STCL_OPTION:
1317 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1318 return MCDisassembler::Fail;
1328 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1329 uint64_t Address, const void *Decoder) {
1330 DecodeStatus S = MCDisassembler::Success;
1332 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1333 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1334 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1335 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1336 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1337 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1338 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1339 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1341 // On stores, the writeback operand precedes Rt.
1342 switch (Inst.getOpcode()) {
1343 case ARM::STR_POST_IMM:
1344 case ARM::STR_POST_REG:
1345 case ARM::STRB_POST_IMM:
1346 case ARM::STRB_POST_REG:
1347 case ARM::STRT_POST_REG:
1348 case ARM::STRT_POST_IMM:
1349 case ARM::STRBT_POST_REG:
1350 case ARM::STRBT_POST_IMM:
1351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1352 return MCDisassembler::Fail;
1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1359 return MCDisassembler::Fail;
1361 // On loads, the writeback operand comes after Rt.
1362 switch (Inst.getOpcode()) {
1363 case ARM::LDR_POST_IMM:
1364 case ARM::LDR_POST_REG:
1365 case ARM::LDRB_POST_IMM:
1366 case ARM::LDRB_POST_REG:
1367 case ARM::LDRBT_POST_REG:
1368 case ARM::LDRBT_POST_IMM:
1369 case ARM::LDRT_POST_REG:
1370 case ARM::LDRT_POST_IMM:
1371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1372 return MCDisassembler::Fail;
1378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1379 return MCDisassembler::Fail;
1381 ARM_AM::AddrOpc Op = ARM_AM::add;
1382 if (!fieldFromInstruction32(Insn, 23, 1))
1385 bool writeback = (P == 0) || (W == 1);
1386 unsigned idx_mode = 0;
1388 idx_mode = ARMII::IndexModePre;
1389 else if (!P && writeback)
1390 idx_mode = ARMII::IndexModePost;
1392 if (writeback && (Rn == 15 || Rn == Rt))
1393 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1396 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1397 return MCDisassembler::Fail;
1398 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1399 switch( fieldFromInstruction32(Insn, 5, 2)) {
1413 return MCDisassembler::Fail;
1415 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1416 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1418 Inst.addOperand(MCOperand::CreateImm(imm));
1420 Inst.addOperand(MCOperand::CreateReg(0));
1421 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1422 Inst.addOperand(MCOperand::CreateImm(tmp));
1425 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1426 return MCDisassembler::Fail;
1431 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1432 uint64_t Address, const void *Decoder) {
1433 DecodeStatus S = MCDisassembler::Success;
1435 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1436 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1437 unsigned type = fieldFromInstruction32(Val, 5, 2);
1438 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1439 unsigned U = fieldFromInstruction32(Val, 12, 1);
1441 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1458 return MCDisassembler::Fail;
1459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1460 return MCDisassembler::Fail;
1463 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1465 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1466 Inst.addOperand(MCOperand::CreateImm(shift));
1472 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1473 uint64_t Address, const void *Decoder) {
1474 DecodeStatus S = MCDisassembler::Success;
1476 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1477 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1478 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1479 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1480 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1481 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1482 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1483 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1484 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1486 bool writeback = (W == 1) | (P == 0);
1488 // For {LD,ST}RD, Rt must be even, else undefined.
1489 switch (Inst.getOpcode()) {
1492 case ARM::STRD_POST:
1495 case ARM::LDRD_POST:
1496 if (Rt & 0x1) return MCDisassembler::Fail;
1502 if (writeback) { // Writeback
1504 U |= ARMII::IndexModePre << 9;
1506 U |= ARMII::IndexModePost << 9;
1508 // On stores, the writeback operand precedes Rt.
1509 switch (Inst.getOpcode()) {
1512 case ARM::STRD_POST:
1515 case ARM::STRH_POST:
1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1517 return MCDisassembler::Fail;
1524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1525 return MCDisassembler::Fail;
1526 switch (Inst.getOpcode()) {
1529 case ARM::STRD_POST:
1532 case ARM::LDRD_POST:
1533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1534 return MCDisassembler::Fail;
1541 // On loads, the writeback operand comes after Rt.
1542 switch (Inst.getOpcode()) {
1545 case ARM::LDRD_POST:
1548 case ARM::LDRH_POST:
1550 case ARM::LDRSH_PRE:
1551 case ARM::LDRSH_POST:
1553 case ARM::LDRSB_PRE:
1554 case ARM::LDRSB_POST:
1557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1558 return MCDisassembler::Fail;
1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1566 return MCDisassembler::Fail;
1569 Inst.addOperand(MCOperand::CreateReg(0));
1570 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1573 return MCDisassembler::Fail;
1574 Inst.addOperand(MCOperand::CreateImm(U));
1577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1578 return MCDisassembler::Fail;
1583 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1584 uint64_t Address, const void *Decoder) {
1585 DecodeStatus S = MCDisassembler::Success;
1587 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1588 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1605 Inst.addOperand(MCOperand::CreateImm(mode));
1606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1607 return MCDisassembler::Fail;
1612 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1614 uint64_t Address, const void *Decoder) {
1615 DecodeStatus S = MCDisassembler::Success;
1617 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1618 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1619 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1622 switch (Inst.getOpcode()) {
1624 Inst.setOpcode(ARM::RFEDA);
1626 case ARM::LDMDA_UPD:
1627 Inst.setOpcode(ARM::RFEDA_UPD);
1630 Inst.setOpcode(ARM::RFEDB);
1632 case ARM::LDMDB_UPD:
1633 Inst.setOpcode(ARM::RFEDB_UPD);
1636 Inst.setOpcode(ARM::RFEIA);
1638 case ARM::LDMIA_UPD:
1639 Inst.setOpcode(ARM::RFEIA_UPD);
1642 Inst.setOpcode(ARM::RFEIB);
1644 case ARM::LDMIB_UPD:
1645 Inst.setOpcode(ARM::RFEIB_UPD);
1648 Inst.setOpcode(ARM::SRSDA);
1650 case ARM::STMDA_UPD:
1651 Inst.setOpcode(ARM::SRSDA_UPD);
1654 Inst.setOpcode(ARM::SRSDB);
1656 case ARM::STMDB_UPD:
1657 Inst.setOpcode(ARM::SRSDB_UPD);
1660 Inst.setOpcode(ARM::SRSIA);
1662 case ARM::STMIA_UPD:
1663 Inst.setOpcode(ARM::SRSIA_UPD);
1666 Inst.setOpcode(ARM::SRSIB);
1668 case ARM::STMIB_UPD:
1669 Inst.setOpcode(ARM::SRSIB_UPD);
1672 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1675 // For stores (which become SRS's, the only operand is the mode.
1676 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1678 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1682 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1686 return MCDisassembler::Fail;
1687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1688 return MCDisassembler::Fail; // Tied
1689 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1690 return MCDisassembler::Fail;
1691 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1692 return MCDisassembler::Fail;
1697 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1698 uint64_t Address, const void *Decoder) {
1699 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1700 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1701 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1702 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1704 DecodeStatus S = MCDisassembler::Success;
1706 // imod == '01' --> UNPREDICTABLE
1707 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1708 // return failure here. The '01' imod value is unprintable, so there's
1709 // nothing useful we could do even if we returned UNPREDICTABLE.
1711 if (imod == 1) return MCDisassembler::Fail;
1714 Inst.setOpcode(ARM::CPS3p);
1715 Inst.addOperand(MCOperand::CreateImm(imod));
1716 Inst.addOperand(MCOperand::CreateImm(iflags));
1717 Inst.addOperand(MCOperand::CreateImm(mode));
1718 } else if (imod && !M) {
1719 Inst.setOpcode(ARM::CPS2p);
1720 Inst.addOperand(MCOperand::CreateImm(imod));
1721 Inst.addOperand(MCOperand::CreateImm(iflags));
1722 if (mode) S = MCDisassembler::SoftFail;
1723 } else if (!imod && M) {
1724 Inst.setOpcode(ARM::CPS1p);
1725 Inst.addOperand(MCOperand::CreateImm(mode));
1726 if (iflags) S = MCDisassembler::SoftFail;
1728 // imod == '00' && M == '0' --> UNPREDICTABLE
1729 Inst.setOpcode(ARM::CPS1p);
1730 Inst.addOperand(MCOperand::CreateImm(mode));
1731 S = MCDisassembler::SoftFail;
1737 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1738 uint64_t Address, const void *Decoder) {
1739 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1740 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1741 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1742 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1744 DecodeStatus S = MCDisassembler::Success;
1746 // imod == '01' --> UNPREDICTABLE
1747 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1748 // return failure here. The '01' imod value is unprintable, so there's
1749 // nothing useful we could do even if we returned UNPREDICTABLE.
1751 if (imod == 1) return MCDisassembler::Fail;
1754 Inst.setOpcode(ARM::t2CPS3p);
1755 Inst.addOperand(MCOperand::CreateImm(imod));
1756 Inst.addOperand(MCOperand::CreateImm(iflags));
1757 Inst.addOperand(MCOperand::CreateImm(mode));
1758 } else if (imod && !M) {
1759 Inst.setOpcode(ARM::t2CPS2p);
1760 Inst.addOperand(MCOperand::CreateImm(imod));
1761 Inst.addOperand(MCOperand::CreateImm(iflags));
1762 if (mode) S = MCDisassembler::SoftFail;
1763 } else if (!imod && M) {
1764 Inst.setOpcode(ARM::t2CPS1p);
1765 Inst.addOperand(MCOperand::CreateImm(mode));
1766 if (iflags) S = MCDisassembler::SoftFail;
1768 // imod == '00' && M == '0' --> UNPREDICTABLE
1769 Inst.setOpcode(ARM::t2CPS1p);
1770 Inst.addOperand(MCOperand::CreateImm(mode));
1771 S = MCDisassembler::SoftFail;
1777 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1778 uint64_t Address, const void *Decoder) {
1779 DecodeStatus S = MCDisassembler::Success;
1781 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1784 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1785 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1786 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1787 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1789 if (Inst.getOpcode() == ARM::t2MOVTi16)
1790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1791 return MCDisassembler::Fail;
1792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1793 return MCDisassembler::Fail;
1795 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1796 Inst.addOperand(MCOperand::CreateImm(imm));
1801 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1802 uint64_t Address, const void *Decoder) {
1803 DecodeStatus S = MCDisassembler::Success;
1805 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1806 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1809 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1810 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1812 if (Inst.getOpcode() == ARM::MOVTi16)
1813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1814 return MCDisassembler::Fail;
1815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1816 return MCDisassembler::Fail;
1818 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1819 Inst.addOperand(MCOperand::CreateImm(imm));
1821 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1822 return MCDisassembler::Fail;
1827 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1828 uint64_t Address, const void *Decoder) {
1829 DecodeStatus S = MCDisassembler::Success;
1831 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1832 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1833 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1834 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1835 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1838 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1841 return MCDisassembler::Fail;
1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1843 return MCDisassembler::Fail;
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1847 return MCDisassembler::Fail;
1849 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1850 return MCDisassembler::Fail;
1855 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1856 uint64_t Address, const void *Decoder) {
1857 DecodeStatus S = MCDisassembler::Success;
1859 unsigned add = fieldFromInstruction32(Val, 12, 1);
1860 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1861 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1864 return MCDisassembler::Fail;
1866 if (!add) imm *= -1;
1867 if (imm == 0 && !add) imm = INT32_MIN;
1868 Inst.addOperand(MCOperand::CreateImm(imm));
1870 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1875 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1876 uint64_t Address, const void *Decoder) {
1877 DecodeStatus S = MCDisassembler::Success;
1879 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1880 unsigned U = fieldFromInstruction32(Val, 8, 1);
1881 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1884 return MCDisassembler::Fail;
1887 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1889 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1894 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1895 uint64_t Address, const void *Decoder) {
1896 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1900 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1901 uint64_t Address, const void *Decoder) {
1902 DecodeStatus S = MCDisassembler::Success;
1904 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1905 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1908 Inst.setOpcode(ARM::BLXi);
1909 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1910 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1914 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1916 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1917 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1918 return MCDisassembler::Fail;
1924 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1925 uint64_t Address, const void *Decoder) {
1926 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1927 return MCDisassembler::Success;
1930 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1931 uint64_t Address, const void *Decoder) {
1932 DecodeStatus S = MCDisassembler::Success;
1934 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1935 unsigned align = fieldFromInstruction32(Val, 4, 2);
1937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1938 return MCDisassembler::Fail;
1940 Inst.addOperand(MCOperand::CreateImm(0));
1942 Inst.addOperand(MCOperand::CreateImm(4 << align));
1947 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1948 uint64_t Address, const void *Decoder) {
1949 DecodeStatus S = MCDisassembler::Success;
1951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1953 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1954 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1955 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1956 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1958 // First output register
1959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1960 return MCDisassembler::Fail;
1962 // Second output register
1963 switch (Inst.getOpcode()) {
1967 case ARM::VLD3d8_UPD:
1968 case ARM::VLD3d16_UPD:
1969 case ARM::VLD3d32_UPD:
1973 case ARM::VLD4d8_UPD:
1974 case ARM::VLD4d16_UPD:
1975 case ARM::VLD4d32_UPD:
1976 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1977 return MCDisassembler::Fail;
1982 case ARM::VLD3q8_UPD:
1983 case ARM::VLD3q16_UPD:
1984 case ARM::VLD3q32_UPD:
1988 case ARM::VLD4q8_UPD:
1989 case ARM::VLD4q16_UPD:
1990 case ARM::VLD4q32_UPD:
1991 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1992 return MCDisassembler::Fail;
1997 // Third output register
1998 switch(Inst.getOpcode()) {
2002 case ARM::VLD3d8_UPD:
2003 case ARM::VLD3d16_UPD:
2004 case ARM::VLD3d32_UPD:
2008 case ARM::VLD4d8_UPD:
2009 case ARM::VLD4d16_UPD:
2010 case ARM::VLD4d32_UPD:
2011 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2012 return MCDisassembler::Fail;
2017 case ARM::VLD3q8_UPD:
2018 case ARM::VLD3q16_UPD:
2019 case ARM::VLD3q32_UPD:
2023 case ARM::VLD4q8_UPD:
2024 case ARM::VLD4q16_UPD:
2025 case ARM::VLD4q32_UPD:
2026 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2027 return MCDisassembler::Fail;
2033 // Fourth output register
2034 switch (Inst.getOpcode()) {
2038 case ARM::VLD4d8_UPD:
2039 case ARM::VLD4d16_UPD:
2040 case ARM::VLD4d32_UPD:
2041 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2042 return MCDisassembler::Fail;
2047 case ARM::VLD4q8_UPD:
2048 case ARM::VLD4q16_UPD:
2049 case ARM::VLD4q32_UPD:
2050 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2051 return MCDisassembler::Fail;
2057 // Writeback operand
2058 switch (Inst.getOpcode()) {
2059 case ARM::VLD1d8wb_fixed:
2060 case ARM::VLD1d16wb_fixed:
2061 case ARM::VLD1d32wb_fixed:
2062 case ARM::VLD1d64wb_fixed:
2063 case ARM::VLD1d8wb_register:
2064 case ARM::VLD1d16wb_register:
2065 case ARM::VLD1d32wb_register:
2066 case ARM::VLD1d64wb_register:
2067 case ARM::VLD1q8wb_fixed:
2068 case ARM::VLD1q16wb_fixed:
2069 case ARM::VLD1q32wb_fixed:
2070 case ARM::VLD1q64wb_fixed:
2071 case ARM::VLD1q8wb_register:
2072 case ARM::VLD1q16wb_register:
2073 case ARM::VLD1q32wb_register:
2074 case ARM::VLD1q64wb_register:
2075 case ARM::VLD1d8Twb_fixed:
2076 case ARM::VLD1d8Twb_register:
2077 case ARM::VLD1d16Twb_fixed:
2078 case ARM::VLD1d16Twb_register:
2079 case ARM::VLD1d32Twb_fixed:
2080 case ARM::VLD1d32Twb_register:
2081 case ARM::VLD1d64Twb_fixed:
2082 case ARM::VLD1d64Twb_register:
2083 case ARM::VLD1d8Qwb_fixed:
2084 case ARM::VLD1d8Qwb_register:
2085 case ARM::VLD1d16Qwb_fixed:
2086 case ARM::VLD1d16Qwb_register:
2087 case ARM::VLD1d32Qwb_fixed:
2088 case ARM::VLD1d32Qwb_register:
2089 case ARM::VLD1d64Qwb_fixed:
2090 case ARM::VLD1d64Qwb_register:
2091 case ARM::VLD2d8_UPD:
2092 case ARM::VLD2d16_UPD:
2093 case ARM::VLD2d32_UPD:
2094 case ARM::VLD2q8_UPD:
2095 case ARM::VLD2q16_UPD:
2096 case ARM::VLD2q32_UPD:
2097 case ARM::VLD2b8_UPD:
2098 case ARM::VLD2b16_UPD:
2099 case ARM::VLD2b32_UPD:
2100 case ARM::VLD3d8_UPD:
2101 case ARM::VLD3d16_UPD:
2102 case ARM::VLD3d32_UPD:
2103 case ARM::VLD3q8_UPD:
2104 case ARM::VLD3q16_UPD:
2105 case ARM::VLD3q32_UPD:
2106 case ARM::VLD4d8_UPD:
2107 case ARM::VLD4d16_UPD:
2108 case ARM::VLD4d32_UPD:
2109 case ARM::VLD4q8_UPD:
2110 case ARM::VLD4q16_UPD:
2111 case ARM::VLD4q32_UPD:
2112 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2113 return MCDisassembler::Fail;
2119 // AddrMode6 Base (register+alignment)
2120 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2121 return MCDisassembler::Fail;
2123 // AddrMode6 Offset (register)
2124 switch (Inst.getOpcode()) {
2126 // The below have been updated to have explicit am6offset split
2127 // between fixed and register offset. For those instructions not
2128 // yet updated, we need to add an additional reg0 operand for the
2131 // The fixed offset encodes as Rm == 0xd, so we check for that.
2133 Inst.addOperand(MCOperand::CreateReg(0));
2136 // Fall through to handle the register offset variant.
2137 case ARM::VLD1d8wb_fixed:
2138 case ARM::VLD1d16wb_fixed:
2139 case ARM::VLD1d32wb_fixed:
2140 case ARM::VLD1d64wb_fixed:
2141 case ARM::VLD1d8Twb_fixed:
2142 case ARM::VLD1d16Twb_fixed:
2143 case ARM::VLD1d32Twb_fixed:
2144 case ARM::VLD1d64Twb_fixed:
2145 case ARM::VLD1d8Qwb_fixed:
2146 case ARM::VLD1d16Qwb_fixed:
2147 case ARM::VLD1d32Qwb_fixed:
2148 case ARM::VLD1d64Qwb_fixed:
2149 case ARM::VLD1d8wb_register:
2150 case ARM::VLD1d16wb_register:
2151 case ARM::VLD1d32wb_register:
2152 case ARM::VLD1d64wb_register:
2153 case ARM::VLD1q8wb_fixed:
2154 case ARM::VLD1q16wb_fixed:
2155 case ARM::VLD1q32wb_fixed:
2156 case ARM::VLD1q64wb_fixed:
2157 case ARM::VLD1q8wb_register:
2158 case ARM::VLD1q16wb_register:
2159 case ARM::VLD1q32wb_register:
2160 case ARM::VLD1q64wb_register:
2161 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2162 // variant encodes Rm == 0xf. Anything else is a register offset post-
2163 // increment and we need to add the register operand to the instruction.
2164 if (Rm != 0xD && Rm != 0xF &&
2165 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2166 return MCDisassembler::Fail;
2173 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
2174 uint64_t Address, const void *Decoder) {
2175 DecodeStatus S = MCDisassembler::Success;
2177 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2178 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2179 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2180 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2181 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2182 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2184 // Writeback Operand
2185 switch (Inst.getOpcode()) {
2186 case ARM::VST1d8_UPD:
2187 case ARM::VST1d16_UPD:
2188 case ARM::VST1d32_UPD:
2189 case ARM::VST1d64_UPD:
2190 case ARM::VST1q8_UPD:
2191 case ARM::VST1q16_UPD:
2192 case ARM::VST1q32_UPD:
2193 case ARM::VST1q64_UPD:
2194 case ARM::VST1d8T_UPD:
2195 case ARM::VST1d16T_UPD:
2196 case ARM::VST1d32T_UPD:
2197 case ARM::VST1d64T_UPD:
2198 case ARM::VST1d8Q_UPD:
2199 case ARM::VST1d16Q_UPD:
2200 case ARM::VST1d32Q_UPD:
2201 case ARM::VST1d64Q_UPD:
2202 case ARM::VST2d8_UPD:
2203 case ARM::VST2d16_UPD:
2204 case ARM::VST2d32_UPD:
2205 case ARM::VST2q8_UPD:
2206 case ARM::VST2q16_UPD:
2207 case ARM::VST2q32_UPD:
2208 case ARM::VST2b8_UPD:
2209 case ARM::VST2b16_UPD:
2210 case ARM::VST2b32_UPD:
2211 case ARM::VST3d8_UPD:
2212 case ARM::VST3d16_UPD:
2213 case ARM::VST3d32_UPD:
2214 case ARM::VST3q8_UPD:
2215 case ARM::VST3q16_UPD:
2216 case ARM::VST3q32_UPD:
2217 case ARM::VST4d8_UPD:
2218 case ARM::VST4d16_UPD:
2219 case ARM::VST4d32_UPD:
2220 case ARM::VST4q8_UPD:
2221 case ARM::VST4q16_UPD:
2222 case ARM::VST4q32_UPD:
2223 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2224 return MCDisassembler::Fail;
2230 // AddrMode6 Base (register+alignment)
2231 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2232 return MCDisassembler::Fail;
2234 // AddrMode6 Offset (register)
2236 Inst.addOperand(MCOperand::CreateReg(0));
2237 else if (Rm != 0xF) {
2238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2239 return MCDisassembler::Fail;
2242 // First input register
2243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2244 return MCDisassembler::Fail;
2246 // Second input register
2247 switch (Inst.getOpcode()) {
2252 case ARM::VST1q8_UPD:
2253 case ARM::VST1q16_UPD:
2254 case ARM::VST1q32_UPD:
2255 case ARM::VST1q64_UPD:
2260 case ARM::VST1d8T_UPD:
2261 case ARM::VST1d16T_UPD:
2262 case ARM::VST1d32T_UPD:
2263 case ARM::VST1d64T_UPD:
2268 case ARM::VST1d8Q_UPD:
2269 case ARM::VST1d16Q_UPD:
2270 case ARM::VST1d32Q_UPD:
2271 case ARM::VST1d64Q_UPD:
2275 case ARM::VST2d8_UPD:
2276 case ARM::VST2d16_UPD:
2277 case ARM::VST2d32_UPD:
2281 case ARM::VST2q8_UPD:
2282 case ARM::VST2q16_UPD:
2283 case ARM::VST2q32_UPD:
2287 case ARM::VST3d8_UPD:
2288 case ARM::VST3d16_UPD:
2289 case ARM::VST3d32_UPD:
2293 case ARM::VST4d8_UPD:
2294 case ARM::VST4d16_UPD:
2295 case ARM::VST4d32_UPD:
2296 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2297 return MCDisassembler::Fail;
2302 case ARM::VST2b8_UPD:
2303 case ARM::VST2b16_UPD:
2304 case ARM::VST2b32_UPD:
2308 case ARM::VST3q8_UPD:
2309 case ARM::VST3q16_UPD:
2310 case ARM::VST3q32_UPD:
2314 case ARM::VST4q8_UPD:
2315 case ARM::VST4q16_UPD:
2316 case ARM::VST4q32_UPD:
2317 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2318 return MCDisassembler::Fail;
2324 // Third input register
2325 switch (Inst.getOpcode()) {
2330 case ARM::VST1d8T_UPD:
2331 case ARM::VST1d16T_UPD:
2332 case ARM::VST1d32T_UPD:
2333 case ARM::VST1d64T_UPD:
2338 case ARM::VST1d8Q_UPD:
2339 case ARM::VST1d16Q_UPD:
2340 case ARM::VST1d32Q_UPD:
2341 case ARM::VST1d64Q_UPD:
2345 case ARM::VST2q8_UPD:
2346 case ARM::VST2q16_UPD:
2347 case ARM::VST2q32_UPD:
2351 case ARM::VST3d8_UPD:
2352 case ARM::VST3d16_UPD:
2353 case ARM::VST3d32_UPD:
2357 case ARM::VST4d8_UPD:
2358 case ARM::VST4d16_UPD:
2359 case ARM::VST4d32_UPD:
2360 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2361 return MCDisassembler::Fail;
2366 case ARM::VST3q8_UPD:
2367 case ARM::VST3q16_UPD:
2368 case ARM::VST3q32_UPD:
2372 case ARM::VST4q8_UPD:
2373 case ARM::VST4q16_UPD:
2374 case ARM::VST4q32_UPD:
2375 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2376 return MCDisassembler::Fail;
2382 // Fourth input register
2383 switch (Inst.getOpcode()) {
2388 case ARM::VST1d8Q_UPD:
2389 case ARM::VST1d16Q_UPD:
2390 case ARM::VST1d32Q_UPD:
2391 case ARM::VST1d64Q_UPD:
2395 case ARM::VST2q8_UPD:
2396 case ARM::VST2q16_UPD:
2397 case ARM::VST2q32_UPD:
2401 case ARM::VST4d8_UPD:
2402 case ARM::VST4d16_UPD:
2403 case ARM::VST4d32_UPD:
2404 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2405 return MCDisassembler::Fail;
2410 case ARM::VST4q8_UPD:
2411 case ARM::VST4q16_UPD:
2412 case ARM::VST4q32_UPD:
2413 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2414 return MCDisassembler::Fail;
2423 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2424 uint64_t Address, const void *Decoder) {
2425 DecodeStatus S = MCDisassembler::Success;
2427 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2428 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2429 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2430 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2431 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2432 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2433 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2435 align *= (1 << size);
2437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2438 return MCDisassembler::Fail;
2440 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2441 return MCDisassembler::Fail;
2444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2445 return MCDisassembler::Fail;
2448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2449 return MCDisassembler::Fail;
2450 Inst.addOperand(MCOperand::CreateImm(align));
2453 Inst.addOperand(MCOperand::CreateReg(0));
2454 else if (Rm != 0xF) {
2455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2456 return MCDisassembler::Fail;
2462 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2463 uint64_t Address, const void *Decoder) {
2464 DecodeStatus S = MCDisassembler::Success;
2466 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2467 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2468 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2469 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2470 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2471 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2472 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2476 return MCDisassembler::Fail;
2477 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2478 return MCDisassembler::Fail;
2480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2481 return MCDisassembler::Fail;
2484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2485 return MCDisassembler::Fail;
2486 Inst.addOperand(MCOperand::CreateImm(align));
2489 Inst.addOperand(MCOperand::CreateReg(0));
2490 else if (Rm != 0xF) {
2491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2492 return MCDisassembler::Fail;
2498 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2499 uint64_t Address, const void *Decoder) {
2500 DecodeStatus S = MCDisassembler::Success;
2502 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2503 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2504 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2505 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2506 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2509 return MCDisassembler::Fail;
2510 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2511 return MCDisassembler::Fail;
2512 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2513 return MCDisassembler::Fail;
2515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2516 return MCDisassembler::Fail;
2519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2520 return MCDisassembler::Fail;
2521 Inst.addOperand(MCOperand::CreateImm(0));
2524 Inst.addOperand(MCOperand::CreateReg(0));
2525 else if (Rm != 0xF) {
2526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2527 return MCDisassembler::Fail;
2533 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2534 uint64_t Address, const void *Decoder) {
2535 DecodeStatus S = MCDisassembler::Success;
2537 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2538 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2539 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2540 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2541 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2542 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2543 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2559 return MCDisassembler::Fail;
2560 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2561 return MCDisassembler::Fail;
2562 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2563 return MCDisassembler::Fail;
2564 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2565 return MCDisassembler::Fail;
2567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2568 return MCDisassembler::Fail;
2571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2572 return MCDisassembler::Fail;
2573 Inst.addOperand(MCOperand::CreateImm(align));
2576 Inst.addOperand(MCOperand::CreateReg(0));
2577 else if (Rm != 0xF) {
2578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2579 return MCDisassembler::Fail;
2586 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2587 uint64_t Address, const void *Decoder) {
2588 DecodeStatus S = MCDisassembler::Success;
2590 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2591 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2592 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2593 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2594 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2595 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2596 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2597 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2600 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2601 return MCDisassembler::Fail;
2603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2604 return MCDisassembler::Fail;
2607 Inst.addOperand(MCOperand::CreateImm(imm));
2609 switch (Inst.getOpcode()) {
2610 case ARM::VORRiv4i16:
2611 case ARM::VORRiv2i32:
2612 case ARM::VBICiv4i16:
2613 case ARM::VBICiv2i32:
2614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2615 return MCDisassembler::Fail;
2617 case ARM::VORRiv8i16:
2618 case ARM::VORRiv4i32:
2619 case ARM::VBICiv8i16:
2620 case ARM::VBICiv4i32:
2621 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2622 return MCDisassembler::Fail;
2631 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2632 uint64_t Address, const void *Decoder) {
2633 DecodeStatus S = MCDisassembler::Success;
2635 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2636 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2637 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2638 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2639 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2641 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2642 return MCDisassembler::Fail;
2643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2644 return MCDisassembler::Fail;
2645 Inst.addOperand(MCOperand::CreateImm(8 << size));
2650 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2651 uint64_t Address, const void *Decoder) {
2652 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2653 return MCDisassembler::Success;
2656 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2657 uint64_t Address, const void *Decoder) {
2658 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2659 return MCDisassembler::Success;
2662 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2663 uint64_t Address, const void *Decoder) {
2664 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2665 return MCDisassembler::Success;
2668 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2669 uint64_t Address, const void *Decoder) {
2670 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2671 return MCDisassembler::Success;
2674 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2675 uint64_t Address, const void *Decoder) {
2676 DecodeStatus S = MCDisassembler::Success;
2678 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2679 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2680 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2681 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2682 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2683 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2684 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2685 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2688 return MCDisassembler::Fail;
2690 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2691 return MCDisassembler::Fail; // Writeback
2694 for (unsigned i = 0; i < length; ++i) {
2695 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2696 return MCDisassembler::Fail;
2699 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2700 return MCDisassembler::Fail;
2705 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2706 uint64_t Address, const void *Decoder) {
2707 DecodeStatus S = MCDisassembler::Success;
2709 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2710 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2712 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2713 return MCDisassembler::Fail;
2715 switch(Inst.getOpcode()) {
2717 return MCDisassembler::Fail;
2719 break; // tADR does not explicitly represent the PC as an operand.
2721 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2725 Inst.addOperand(MCOperand::CreateImm(imm));
2729 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2730 uint64_t Address, const void *Decoder) {
2731 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2732 return MCDisassembler::Success;
2735 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2736 uint64_t Address, const void *Decoder) {
2737 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2738 return MCDisassembler::Success;
2741 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2742 uint64_t Address, const void *Decoder) {
2743 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2744 return MCDisassembler::Success;
2747 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2748 uint64_t Address, const void *Decoder) {
2749 DecodeStatus S = MCDisassembler::Success;
2751 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2752 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2754 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2755 return MCDisassembler::Fail;
2756 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2757 return MCDisassembler::Fail;
2762 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2763 uint64_t Address, const void *Decoder) {
2764 DecodeStatus S = MCDisassembler::Success;
2766 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2767 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2769 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2770 return MCDisassembler::Fail;
2771 Inst.addOperand(MCOperand::CreateImm(imm));
2776 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2777 uint64_t Address, const void *Decoder) {
2778 unsigned imm = Val << 2;
2780 Inst.addOperand(MCOperand::CreateImm(imm));
2781 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2783 return MCDisassembler::Success;
2786 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2787 uint64_t Address, const void *Decoder) {
2788 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2789 Inst.addOperand(MCOperand::CreateImm(Val));
2791 return MCDisassembler::Success;
2794 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2795 uint64_t Address, const void *Decoder) {
2796 DecodeStatus S = MCDisassembler::Success;
2798 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2799 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2800 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2803 return MCDisassembler::Fail;
2804 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2805 return MCDisassembler::Fail;
2806 Inst.addOperand(MCOperand::CreateImm(imm));
2811 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2812 uint64_t Address, const void *Decoder) {
2813 DecodeStatus S = MCDisassembler::Success;
2815 switch (Inst.getOpcode()) {
2821 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2822 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2823 return MCDisassembler::Fail;
2827 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2829 switch (Inst.getOpcode()) {
2831 Inst.setOpcode(ARM::t2LDRBpci);
2834 Inst.setOpcode(ARM::t2LDRHpci);
2837 Inst.setOpcode(ARM::t2LDRSHpci);
2840 Inst.setOpcode(ARM::t2LDRSBpci);
2843 Inst.setOpcode(ARM::t2PLDi12);
2844 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2847 return MCDisassembler::Fail;
2850 int imm = fieldFromInstruction32(Insn, 0, 12);
2851 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2852 Inst.addOperand(MCOperand::CreateImm(imm));
2857 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2858 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2859 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2860 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2861 return MCDisassembler::Fail;
2866 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2867 uint64_t Address, const void *Decoder) {
2868 int imm = Val & 0xFF;
2869 if (!(Val & 0x100)) imm *= -1;
2870 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2872 return MCDisassembler::Success;
2875 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2876 uint64_t Address, const void *Decoder) {
2877 DecodeStatus S = MCDisassembler::Success;
2879 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2880 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2883 return MCDisassembler::Fail;
2884 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2885 return MCDisassembler::Fail;
2890 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2891 uint64_t Address, const void *Decoder) {
2892 DecodeStatus S = MCDisassembler::Success;
2894 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2895 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2897 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2898 return MCDisassembler::Fail;
2900 Inst.addOperand(MCOperand::CreateImm(imm));
2905 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2906 uint64_t Address, const void *Decoder) {
2907 int imm = Val & 0xFF;
2910 else if (!(Val & 0x100))
2912 Inst.addOperand(MCOperand::CreateImm(imm));
2914 return MCDisassembler::Success;
2918 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2919 uint64_t Address, const void *Decoder) {
2920 DecodeStatus S = MCDisassembler::Success;
2922 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2923 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2925 // Some instructions always use an additive offset.
2926 switch (Inst.getOpcode()) {
2941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2942 return MCDisassembler::Fail;
2943 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2944 return MCDisassembler::Fail;
2949 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2950 uint64_t Address, const void *Decoder) {
2951 DecodeStatus S = MCDisassembler::Success;
2953 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2954 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2955 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2956 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2958 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2962 return MCDisassembler::Fail;
2965 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2966 return MCDisassembler::Fail;
2969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2970 return MCDisassembler::Fail;
2973 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2974 return MCDisassembler::Fail;
2979 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2980 uint64_t Address, const void *Decoder) {
2981 DecodeStatus S = MCDisassembler::Success;
2983 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2984 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2987 return MCDisassembler::Fail;
2988 Inst.addOperand(MCOperand::CreateImm(imm));
2994 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2995 uint64_t Address, const void *Decoder) {
2996 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2998 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2999 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3000 Inst.addOperand(MCOperand::CreateImm(imm));
3002 return MCDisassembler::Success;
3005 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
3006 uint64_t Address, const void *Decoder) {
3007 DecodeStatus S = MCDisassembler::Success;
3009 if (Inst.getOpcode() == ARM::tADDrSP) {
3010 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3011 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3014 return MCDisassembler::Fail;
3015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3016 return MCDisassembler::Fail;
3017 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3018 } else if (Inst.getOpcode() == ARM::tADDspr) {
3019 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3021 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3022 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3023 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3024 return MCDisassembler::Fail;
3030 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
3031 uint64_t Address, const void *Decoder) {
3032 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3033 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3035 Inst.addOperand(MCOperand::CreateImm(imod));
3036 Inst.addOperand(MCOperand::CreateImm(flags));
3038 return MCDisassembler::Success;
3041 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
3042 uint64_t Address, const void *Decoder) {
3043 DecodeStatus S = MCDisassembler::Success;
3044 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3045 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3048 return MCDisassembler::Fail;
3049 Inst.addOperand(MCOperand::CreateImm(add));
3054 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
3055 uint64_t Address, const void *Decoder) {
3056 if (!tryAddingSymbolicOperand(Address,
3057 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3058 true, 4, Inst, Decoder))
3059 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3060 return MCDisassembler::Success;
3063 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
3064 uint64_t Address, const void *Decoder) {
3065 if (Val == 0xA || Val == 0xB)
3066 return MCDisassembler::Fail;
3068 Inst.addOperand(MCOperand::CreateImm(Val));
3069 return MCDisassembler::Success;
3073 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3074 uint64_t Address, const void *Decoder) {
3075 DecodeStatus S = MCDisassembler::Success;
3077 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3078 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3080 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3084 return MCDisassembler::Fail;
3089 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3090 uint64_t Address, const void *Decoder) {
3091 DecodeStatus S = MCDisassembler::Success;
3093 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3094 if (pred == 0xE || pred == 0xF) {
3095 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3098 return MCDisassembler::Fail;
3100 Inst.setOpcode(ARM::t2DSB);
3103 Inst.setOpcode(ARM::t2DMB);
3106 Inst.setOpcode(ARM::t2ISB);
3110 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3111 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3114 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3115 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3116 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3117 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3118 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3120 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3121 return MCDisassembler::Fail;
3122 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3123 return MCDisassembler::Fail;
3128 // Decode a shifted immediate operand. These basically consist
3129 // of an 8-bit value, and a 4-bit directive that specifies either
3130 // a splat operation or a rotation.
3131 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
3132 uint64_t Address, const void *Decoder) {
3133 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3135 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3136 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3139 Inst.addOperand(MCOperand::CreateImm(imm));
3142 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3145 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3148 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3153 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3154 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3155 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3156 Inst.addOperand(MCOperand::CreateImm(imm));
3159 return MCDisassembler::Success;
3163 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3164 uint64_t Address, const void *Decoder){
3165 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3166 return MCDisassembler::Success;
3169 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
3170 uint64_t Address, const void *Decoder){
3171 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3172 return MCDisassembler::Success;
3175 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
3176 uint64_t Address, const void *Decoder) {
3179 return MCDisassembler::Fail;
3191 Inst.addOperand(MCOperand::CreateImm(Val));
3192 return MCDisassembler::Success;
3195 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
3196 uint64_t Address, const void *Decoder) {
3197 if (!Val) return MCDisassembler::Fail;
3198 Inst.addOperand(MCOperand::CreateImm(Val));
3199 return MCDisassembler::Success;
3202 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
3203 uint64_t Address, const void *Decoder) {
3204 DecodeStatus S = MCDisassembler::Success;
3206 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3207 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3208 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3210 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3213 return MCDisassembler::Fail;
3214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3215 return MCDisassembler::Fail;
3216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3217 return MCDisassembler::Fail;
3218 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3219 return MCDisassembler::Fail;
3225 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
3226 uint64_t Address, const void *Decoder){
3227 DecodeStatus S = MCDisassembler::Success;
3229 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3230 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3231 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3232 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3234 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3235 return MCDisassembler::Fail;
3237 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3238 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3241 return MCDisassembler::Fail;
3242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3243 return MCDisassembler::Fail;
3244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3245 return MCDisassembler::Fail;
3246 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3247 return MCDisassembler::Fail;
3252 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
3253 uint64_t Address, const void *Decoder) {
3254 DecodeStatus S = MCDisassembler::Success;
3256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3257 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3258 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3259 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3260 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3261 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3263 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3266 return MCDisassembler::Fail;
3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3268 return MCDisassembler::Fail;
3269 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3270 return MCDisassembler::Fail;
3271 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3272 return MCDisassembler::Fail;
3277 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
3278 uint64_t Address, const void *Decoder) {
3279 DecodeStatus S = MCDisassembler::Success;
3281 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3282 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3283 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3284 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3285 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3286 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3287 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3289 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3290 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3293 return MCDisassembler::Fail;
3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3295 return MCDisassembler::Fail;
3296 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3297 return MCDisassembler::Fail;
3298 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3299 return MCDisassembler::Fail;
3305 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
3306 uint64_t Address, const void *Decoder) {
3307 DecodeStatus S = MCDisassembler::Success;
3309 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3310 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3311 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3312 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3313 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3314 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3316 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3319 return MCDisassembler::Fail;
3320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3321 return MCDisassembler::Fail;
3322 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3323 return MCDisassembler::Fail;
3324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3325 return MCDisassembler::Fail;
3330 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
3331 uint64_t Address, const void *Decoder) {
3332 DecodeStatus S = MCDisassembler::Success;
3334 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3335 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3336 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3337 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3338 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3339 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3341 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3344 return MCDisassembler::Fail;
3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3346 return MCDisassembler::Fail;
3347 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3348 return MCDisassembler::Fail;
3349 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3350 return MCDisassembler::Fail;
3355 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
3356 uint64_t Address, const void *Decoder) {
3357 DecodeStatus S = MCDisassembler::Success;
3359 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3360 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3361 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3362 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3363 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3369 return MCDisassembler::Fail;
3371 if (fieldFromInstruction32(Insn, 4, 1))
3372 return MCDisassembler::Fail; // UNDEFINED
3373 index = fieldFromInstruction32(Insn, 5, 3);
3376 if (fieldFromInstruction32(Insn, 5, 1))
3377 return MCDisassembler::Fail; // UNDEFINED
3378 index = fieldFromInstruction32(Insn, 6, 2);
3379 if (fieldFromInstruction32(Insn, 4, 1))
3383 if (fieldFromInstruction32(Insn, 6, 1))
3384 return MCDisassembler::Fail; // UNDEFINED
3385 index = fieldFromInstruction32(Insn, 7, 1);
3386 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3391 return MCDisassembler::Fail;
3392 if (Rm != 0xF) { // Writeback
3393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3394 return MCDisassembler::Fail;
3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3397 return MCDisassembler::Fail;
3398 Inst.addOperand(MCOperand::CreateImm(align));
3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3402 return MCDisassembler::Fail;
3404 Inst.addOperand(MCOperand::CreateReg(0));
3407 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 Inst.addOperand(MCOperand::CreateImm(index));
3414 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
3415 uint64_t Address, const void *Decoder) {
3416 DecodeStatus S = MCDisassembler::Success;
3418 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3419 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3420 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3421 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3422 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3428 return MCDisassembler::Fail;
3430 if (fieldFromInstruction32(Insn, 4, 1))
3431 return MCDisassembler::Fail; // UNDEFINED
3432 index = fieldFromInstruction32(Insn, 5, 3);
3435 if (fieldFromInstruction32(Insn, 5, 1))
3436 return MCDisassembler::Fail; // UNDEFINED
3437 index = fieldFromInstruction32(Insn, 6, 2);
3438 if (fieldFromInstruction32(Insn, 4, 1))
3442 if (fieldFromInstruction32(Insn, 6, 1))
3443 return MCDisassembler::Fail; // UNDEFINED
3444 index = fieldFromInstruction32(Insn, 7, 1);
3445 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3449 if (Rm != 0xF) { // Writeback
3450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3451 return MCDisassembler::Fail;
3453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3454 return MCDisassembler::Fail;
3455 Inst.addOperand(MCOperand::CreateImm(align));
3458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3459 return MCDisassembler::Fail;
3461 Inst.addOperand(MCOperand::CreateReg(0));
3464 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3465 return MCDisassembler::Fail;
3466 Inst.addOperand(MCOperand::CreateImm(index));
3472 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
3473 uint64_t Address, const void *Decoder) {
3474 DecodeStatus S = MCDisassembler::Success;
3476 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3477 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3478 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3479 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3480 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3487 return MCDisassembler::Fail;
3489 index = fieldFromInstruction32(Insn, 5, 3);
3490 if (fieldFromInstruction32(Insn, 4, 1))
3494 index = fieldFromInstruction32(Insn, 6, 2);
3495 if (fieldFromInstruction32(Insn, 4, 1))
3497 if (fieldFromInstruction32(Insn, 5, 1))
3501 if (fieldFromInstruction32(Insn, 5, 1))
3502 return MCDisassembler::Fail; // UNDEFINED
3503 index = fieldFromInstruction32(Insn, 7, 1);
3504 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3506 if (fieldFromInstruction32(Insn, 6, 1))
3511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3512 return MCDisassembler::Fail;
3513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3514 return MCDisassembler::Fail;
3515 if (Rm != 0xF) { // Writeback
3516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3517 return MCDisassembler::Fail;
3519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3520 return MCDisassembler::Fail;
3521 Inst.addOperand(MCOperand::CreateImm(align));
3524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3525 return MCDisassembler::Fail;
3527 Inst.addOperand(MCOperand::CreateReg(0));
3530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3531 return MCDisassembler::Fail;
3532 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 Inst.addOperand(MCOperand::CreateImm(index));
3539 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3540 uint64_t Address, const void *Decoder) {
3541 DecodeStatus S = MCDisassembler::Success;
3543 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3544 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3545 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3546 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3547 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3554 return MCDisassembler::Fail;
3556 index = fieldFromInstruction32(Insn, 5, 3);
3557 if (fieldFromInstruction32(Insn, 4, 1))
3561 index = fieldFromInstruction32(Insn, 6, 2);
3562 if (fieldFromInstruction32(Insn, 4, 1))
3564 if (fieldFromInstruction32(Insn, 5, 1))
3568 if (fieldFromInstruction32(Insn, 5, 1))
3569 return MCDisassembler::Fail; // UNDEFINED
3570 index = fieldFromInstruction32(Insn, 7, 1);
3571 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3573 if (fieldFromInstruction32(Insn, 6, 1))
3578 if (Rm != 0xF) { // Writeback
3579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3580 return MCDisassembler::Fail;
3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3583 return MCDisassembler::Fail;
3584 Inst.addOperand(MCOperand::CreateImm(align));
3587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3588 return MCDisassembler::Fail;
3590 Inst.addOperand(MCOperand::CreateReg(0));
3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 Inst.addOperand(MCOperand::CreateImm(index));
3603 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3604 uint64_t Address, const void *Decoder) {
3605 DecodeStatus S = MCDisassembler::Success;
3607 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3608 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3609 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3610 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3611 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3618 return MCDisassembler::Fail;
3620 if (fieldFromInstruction32(Insn, 4, 1))
3621 return MCDisassembler::Fail; // UNDEFINED
3622 index = fieldFromInstruction32(Insn, 5, 3);
3625 if (fieldFromInstruction32(Insn, 4, 1))
3626 return MCDisassembler::Fail; // UNDEFINED
3627 index = fieldFromInstruction32(Insn, 6, 2);
3628 if (fieldFromInstruction32(Insn, 5, 1))
3632 if (fieldFromInstruction32(Insn, 4, 2))
3633 return MCDisassembler::Fail; // UNDEFINED
3634 index = fieldFromInstruction32(Insn, 7, 1);
3635 if (fieldFromInstruction32(Insn, 6, 1))
3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3641 return MCDisassembler::Fail;
3642 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3643 return MCDisassembler::Fail;
3644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3645 return MCDisassembler::Fail;
3647 if (Rm != 0xF) { // Writeback
3648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3649 return MCDisassembler::Fail;
3651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3652 return MCDisassembler::Fail;
3653 Inst.addOperand(MCOperand::CreateImm(align));
3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3657 return MCDisassembler::Fail;
3659 Inst.addOperand(MCOperand::CreateReg(0));
3662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3663 return MCDisassembler::Fail;
3664 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3665 return MCDisassembler::Fail;
3666 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3667 return MCDisassembler::Fail;
3668 Inst.addOperand(MCOperand::CreateImm(index));
3673 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3674 uint64_t Address, const void *Decoder) {
3675 DecodeStatus S = MCDisassembler::Success;
3677 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3678 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3679 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3680 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3681 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3688 return MCDisassembler::Fail;
3690 if (fieldFromInstruction32(Insn, 4, 1))
3691 return MCDisassembler::Fail; // UNDEFINED
3692 index = fieldFromInstruction32(Insn, 5, 3);
3695 if (fieldFromInstruction32(Insn, 4, 1))
3696 return MCDisassembler::Fail; // UNDEFINED
3697 index = fieldFromInstruction32(Insn, 6, 2);
3698 if (fieldFromInstruction32(Insn, 5, 1))
3702 if (fieldFromInstruction32(Insn, 4, 2))
3703 return MCDisassembler::Fail; // UNDEFINED
3704 index = fieldFromInstruction32(Insn, 7, 1);
3705 if (fieldFromInstruction32(Insn, 6, 1))
3710 if (Rm != 0xF) { // Writeback
3711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3712 return MCDisassembler::Fail;
3714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3715 return MCDisassembler::Fail;
3716 Inst.addOperand(MCOperand::CreateImm(align));
3719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3720 return MCDisassembler::Fail;
3722 Inst.addOperand(MCOperand::CreateReg(0));
3725 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3726 return MCDisassembler::Fail;
3727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3728 return MCDisassembler::Fail;
3729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 Inst.addOperand(MCOperand::CreateImm(index));
3737 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3738 uint64_t Address, const void *Decoder) {
3739 DecodeStatus S = MCDisassembler::Success;
3741 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3742 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3743 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3744 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3745 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3752 return MCDisassembler::Fail;
3754 if (fieldFromInstruction32(Insn, 4, 1))
3756 index = fieldFromInstruction32(Insn, 5, 3);
3759 if (fieldFromInstruction32(Insn, 4, 1))
3761 index = fieldFromInstruction32(Insn, 6, 2);
3762 if (fieldFromInstruction32(Insn, 5, 1))
3766 if (fieldFromInstruction32(Insn, 4, 2))
3767 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3768 index = fieldFromInstruction32(Insn, 7, 1);
3769 if (fieldFromInstruction32(Insn, 6, 1))
3774 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3775 return MCDisassembler::Fail;
3776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3777 return MCDisassembler::Fail;
3778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3779 return MCDisassembler::Fail;
3780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3781 return MCDisassembler::Fail;
3783 if (Rm != 0xF) { // Writeback
3784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3785 return MCDisassembler::Fail;
3787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3788 return MCDisassembler::Fail;
3789 Inst.addOperand(MCOperand::CreateImm(align));
3792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3793 return MCDisassembler::Fail;
3795 Inst.addOperand(MCOperand::CreateReg(0));
3798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3799 return MCDisassembler::Fail;
3800 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3801 return MCDisassembler::Fail;
3802 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3803 return MCDisassembler::Fail;
3804 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3805 return MCDisassembler::Fail;
3806 Inst.addOperand(MCOperand::CreateImm(index));
3811 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3812 uint64_t Address, const void *Decoder) {
3813 DecodeStatus S = MCDisassembler::Success;
3815 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3816 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3817 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3818 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3819 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3826 return MCDisassembler::Fail;
3828 if (fieldFromInstruction32(Insn, 4, 1))
3830 index = fieldFromInstruction32(Insn, 5, 3);
3833 if (fieldFromInstruction32(Insn, 4, 1))
3835 index = fieldFromInstruction32(Insn, 6, 2);
3836 if (fieldFromInstruction32(Insn, 5, 1))
3840 if (fieldFromInstruction32(Insn, 4, 2))
3841 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3842 index = fieldFromInstruction32(Insn, 7, 1);
3843 if (fieldFromInstruction32(Insn, 6, 1))
3848 if (Rm != 0xF) { // Writeback
3849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3850 return MCDisassembler::Fail;
3852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3853 return MCDisassembler::Fail;
3854 Inst.addOperand(MCOperand::CreateImm(align));
3857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3858 return MCDisassembler::Fail;
3860 Inst.addOperand(MCOperand::CreateReg(0));
3863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3864 return MCDisassembler::Fail;
3865 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3866 return MCDisassembler::Fail;
3867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3868 return MCDisassembler::Fail;
3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3870 return MCDisassembler::Fail;
3871 Inst.addOperand(MCOperand::CreateImm(index));
3876 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3877 uint64_t Address, const void *Decoder) {
3878 DecodeStatus S = MCDisassembler::Success;
3879 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3880 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3881 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3882 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3883 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3885 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3886 S = MCDisassembler::SoftFail;
3888 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3889 return MCDisassembler::Fail;
3890 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3893 return MCDisassembler::Fail;
3894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3895 return MCDisassembler::Fail;
3896 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3897 return MCDisassembler::Fail;
3902 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3903 uint64_t Address, const void *Decoder) {
3904 DecodeStatus S = MCDisassembler::Success;
3905 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3906 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3907 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3908 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3909 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3911 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3912 S = MCDisassembler::SoftFail;
3914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3915 return MCDisassembler::Fail;
3916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3917 return MCDisassembler::Fail;
3918 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3919 return MCDisassembler::Fail;
3920 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3921 return MCDisassembler::Fail;
3922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3923 return MCDisassembler::Fail;
3928 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
3929 uint64_t Address, const void *Decoder) {
3930 DecodeStatus S = MCDisassembler::Success;
3931 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3932 // The InstPrinter needs to have the low bit of the predicate in
3933 // the mask operand to be able to print it properly.
3934 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3938 S = MCDisassembler::SoftFail;
3941 if ((mask & 0xF) == 0) {
3942 // Preserve the high bit of the mask, which is the low bit of
3946 S = MCDisassembler::SoftFail;
3949 Inst.addOperand(MCOperand::CreateImm(pred));
3950 Inst.addOperand(MCOperand::CreateImm(mask));
3955 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3956 uint64_t Address, const void *Decoder) {
3957 DecodeStatus S = MCDisassembler::Success;
3959 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3960 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3961 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3962 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3963 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3964 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3965 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3966 bool writeback = (W == 1) | (P == 0);
3968 addr |= (U << 8) | (Rn << 9);
3970 if (writeback && (Rn == Rt || Rn == Rt2))
3971 Check(S, MCDisassembler::SoftFail);
3973 Check(S, MCDisassembler::SoftFail);
3976 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3977 return MCDisassembler::Fail;
3979 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3980 return MCDisassembler::Fail;
3981 // Writeback operand
3982 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3983 return MCDisassembler::Fail;
3985 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3986 return MCDisassembler::Fail;
3992 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3993 uint64_t Address, const void *Decoder) {
3994 DecodeStatus S = MCDisassembler::Success;
3996 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3997 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3999 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4000 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4001 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4002 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4003 bool writeback = (W == 1) | (P == 0);
4005 addr |= (U << 8) | (Rn << 9);
4007 if (writeback && (Rn == Rt || Rn == Rt2))
4008 Check(S, MCDisassembler::SoftFail);
4010 // Writeback operand
4011 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4012 return MCDisassembler::Fail;
4014 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4015 return MCDisassembler::Fail;
4017 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4018 return MCDisassembler::Fail;
4020 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4021 return MCDisassembler::Fail;
4026 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4027 uint64_t Address, const void *Decoder) {
4028 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4029 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4030 if (sign1 != sign2) return MCDisassembler::Fail;
4032 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4033 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4034 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4036 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4038 return MCDisassembler::Success;
4041 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4043 const void *Decoder) {
4044 DecodeStatus S = MCDisassembler::Success;
4046 // Shift of "asr #32" is not allowed in Thumb2 mode.
4047 if (Val == 0x20) S = MCDisassembler::SoftFail;
4048 Inst.addOperand(MCOperand::CreateImm(Val));
4052 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4053 uint64_t Address, const void *Decoder) {
4054 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4055 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4056 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4057 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4060 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4062 DecodeStatus S = MCDisassembler::Success;
4063 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4064 return MCDisassembler::Fail;
4065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4066 return MCDisassembler::Fail;
4067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4068 return MCDisassembler::Fail;
4069 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4070 return MCDisassembler::Fail;