1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassemblerCore.h"
19 #include "ARMAddressingModes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
23 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
24 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
25 /// describing the operand info for each ARMInsts[i].
27 /// Together with an instruction's encoding format, we can take advantage of the
28 /// NumOperands and the OpInfo fields of the target instruction description in
29 /// the quest to build out the MCOperand list for an MCInst.
31 /// The general guideline is that with a known format, the number of dst and src
32 /// operands are well-known. The dst is built first, followed by the src
33 /// operand(s). The operands not yet used at this point are for the Implicit
34 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
35 /// defined with two components:
37 /// def pred { // Operand PredicateOperand
38 /// ValueType Type = OtherVT;
39 /// string PrintMethod = "printPredicateOperand";
40 /// string AsmOperandLowerMethod = ?;
41 /// dag MIOperandInfo = (ops i32imm, CCR);
42 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
43 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
46 /// which is manifested by the TargetOperandInfo[] of:
48 /// { 0, 0|(1<<TOI::Predicate), 0 },
49 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
51 /// So the first predicate MCOperand corresponds to the immediate part of the
52 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
53 /// corresponds to a register kind of ARM::CPSR.
55 /// For the Defs part, in the simple case of only cc_out:$s, we have:
57 /// def cc_out { // Operand OptionalDefOperand
58 /// ValueType Type = OtherVT;
59 /// string PrintMethod = "printSBitModifierOperand";
60 /// string AsmOperandLowerMethod = ?;
61 /// dag MIOperandInfo = (ops CCR);
62 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
63 /// dag DefaultOps = (ops (i32 zero_reg));
66 /// which is manifested by the one TargetOperandInfo of:
68 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
70 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
71 #include "ARMGenInstrInfo.inc"
75 const char *ARMUtils::OpcodeName(unsigned Opcode) {
76 return ARMInsts[Opcode].Name;
79 // Return the register enum Based on RegClass and the raw register number.
80 // For DRegPair, see comments below.
82 static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister,
83 bool DRegPair = false) {
85 if (DRegPair && RegClassID == ARM::QPRRegClassID) {
86 // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified
87 // in the ARM Architecture Manual as far as I understand it (A8.6.307).
88 // Therefore, we morph the RegClassID to be the sub register class and don't
89 // subsequently transform the RawRegister encoding when calculating RegNum.
91 // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part
92 // where this workaround is meant for.
93 RegClassID = ARM::DPRRegClassID;
96 // For this purpose, we can treat rGPR as if it were GPR.
97 if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
99 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
101 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
107 switch (RegClassID) {
108 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
109 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
110 case ARM::DPR_VFP2RegClassID:
112 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
113 case ARM::QPR_VFP2RegClassID:
115 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
119 switch (RegClassID) {
120 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
121 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
122 case ARM::DPR_VFP2RegClassID:
124 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
125 case ARM::QPR_VFP2RegClassID:
127 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
131 switch (RegClassID) {
132 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
133 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
134 case ARM::DPR_VFP2RegClassID:
136 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
137 case ARM::QPR_VFP2RegClassID:
139 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
143 switch (RegClassID) {
144 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
145 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
146 case ARM::DPR_VFP2RegClassID:
148 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
149 case ARM::QPR_VFP2RegClassID:
151 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
155 switch (RegClassID) {
156 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
157 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
158 case ARM::DPR_VFP2RegClassID:
160 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
161 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
165 switch (RegClassID) {
166 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
167 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
168 case ARM::DPR_VFP2RegClassID:
170 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
171 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
175 switch (RegClassID) {
176 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
177 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
178 case ARM::DPR_VFP2RegClassID:
180 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
181 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
185 switch (RegClassID) {
186 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
187 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
188 case ARM::DPR_VFP2RegClassID:
190 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
191 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
195 switch (RegClassID) {
196 case ARM::GPRRegClassID: return ARM::R8;
197 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
198 case ARM::QPRRegClassID: return ARM::Q8;
199 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
203 switch (RegClassID) {
204 case ARM::GPRRegClassID: return ARM::R9;
205 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
206 case ARM::QPRRegClassID: return ARM::Q9;
207 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
211 switch (RegClassID) {
212 case ARM::GPRRegClassID: return ARM::R10;
213 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
214 case ARM::QPRRegClassID: return ARM::Q10;
215 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
219 switch (RegClassID) {
220 case ARM::GPRRegClassID: return ARM::R11;
221 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
222 case ARM::QPRRegClassID: return ARM::Q11;
223 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
227 switch (RegClassID) {
228 case ARM::GPRRegClassID: return ARM::R12;
229 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
230 case ARM::QPRRegClassID: return ARM::Q12;
231 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
235 switch (RegClassID) {
236 case ARM::GPRRegClassID: return ARM::SP;
237 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
238 case ARM::QPRRegClassID: return ARM::Q13;
239 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
243 switch (RegClassID) {
244 case ARM::GPRRegClassID: return ARM::LR;
245 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
246 case ARM::QPRRegClassID: return ARM::Q14;
247 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
251 switch (RegClassID) {
252 case ARM::GPRRegClassID: return ARM::PC;
253 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
254 case ARM::QPRRegClassID: return ARM::Q15;
255 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
259 switch (RegClassID) {
260 case ARM::DPRRegClassID: return ARM::D16;
261 case ARM::SPRRegClassID: return ARM::S16;
265 switch (RegClassID) {
266 case ARM::DPRRegClassID: return ARM::D17;
267 case ARM::SPRRegClassID: return ARM::S17;
271 switch (RegClassID) {
272 case ARM::DPRRegClassID: return ARM::D18;
273 case ARM::SPRRegClassID: return ARM::S18;
277 switch (RegClassID) {
278 case ARM::DPRRegClassID: return ARM::D19;
279 case ARM::SPRRegClassID: return ARM::S19;
283 switch (RegClassID) {
284 case ARM::DPRRegClassID: return ARM::D20;
285 case ARM::SPRRegClassID: return ARM::S20;
289 switch (RegClassID) {
290 case ARM::DPRRegClassID: return ARM::D21;
291 case ARM::SPRRegClassID: return ARM::S21;
295 switch (RegClassID) {
296 case ARM::DPRRegClassID: return ARM::D22;
297 case ARM::SPRRegClassID: return ARM::S22;
301 switch (RegClassID) {
302 case ARM::DPRRegClassID: return ARM::D23;
303 case ARM::SPRRegClassID: return ARM::S23;
307 switch (RegClassID) {
308 case ARM::DPRRegClassID: return ARM::D24;
309 case ARM::SPRRegClassID: return ARM::S24;
313 switch (RegClassID) {
314 case ARM::DPRRegClassID: return ARM::D25;
315 case ARM::SPRRegClassID: return ARM::S25;
319 switch (RegClassID) {
320 case ARM::DPRRegClassID: return ARM::D26;
321 case ARM::SPRRegClassID: return ARM::S26;
325 switch (RegClassID) {
326 case ARM::DPRRegClassID: return ARM::D27;
327 case ARM::SPRRegClassID: return ARM::S27;
331 switch (RegClassID) {
332 case ARM::DPRRegClassID: return ARM::D28;
333 case ARM::SPRRegClassID: return ARM::S28;
337 switch (RegClassID) {
338 case ARM::DPRRegClassID: return ARM::D29;
339 case ARM::SPRRegClassID: return ARM::S29;
343 switch (RegClassID) {
344 case ARM::DPRRegClassID: return ARM::D30;
345 case ARM::SPRRegClassID: return ARM::S30;
349 switch (RegClassID) {
350 case ARM::DPRRegClassID: return ARM::D31;
351 case ARM::SPRRegClassID: return ARM::S31;
355 DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
356 // Encoding error. Mark the builder with error code != 0.
361 ///////////////////////////////
363 // Utility Functions //
365 ///////////////////////////////
367 // Extract/Decode Rd: Inst{15-12}.
368 static inline unsigned decodeRd(uint32_t insn) {
369 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
372 // Extract/Decode Rn: Inst{19-16}.
373 static inline unsigned decodeRn(uint32_t insn) {
374 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
377 // Extract/Decode Rm: Inst{3-0}.
378 static inline unsigned decodeRm(uint32_t insn) {
379 return (insn & ARMII::GPRRegMask);
382 // Extract/Decode Rs: Inst{11-8}.
383 static inline unsigned decodeRs(uint32_t insn) {
384 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
387 static inline unsigned getCondField(uint32_t insn) {
388 return (insn >> ARMII::CondShift);
391 static inline unsigned getIBit(uint32_t insn) {
392 return (insn >> ARMII::I_BitShift) & 1;
395 static inline unsigned getAM3IBit(uint32_t insn) {
396 return (insn >> ARMII::AM3_I_BitShift) & 1;
399 static inline unsigned getPBit(uint32_t insn) {
400 return (insn >> ARMII::P_BitShift) & 1;
403 static inline unsigned getUBit(uint32_t insn) {
404 return (insn >> ARMII::U_BitShift) & 1;
407 static inline unsigned getPUBits(uint32_t insn) {
408 return (insn >> ARMII::U_BitShift) & 3;
411 static inline unsigned getSBit(uint32_t insn) {
412 return (insn >> ARMII::S_BitShift) & 1;
415 static inline unsigned getWBit(uint32_t insn) {
416 return (insn >> ARMII::W_BitShift) & 1;
419 static inline unsigned getDBit(uint32_t insn) {
420 return (insn >> ARMII::D_BitShift) & 1;
423 static inline unsigned getNBit(uint32_t insn) {
424 return (insn >> ARMII::N_BitShift) & 1;
427 static inline unsigned getMBit(uint32_t insn) {
428 return (insn >> ARMII::M_BitShift) & 1;
431 // See A8.4 Shifts applied to a register.
432 // A8.4.2 Register controlled shifts.
434 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
435 // into llvm enums for shift opcode. The API clients should pass in the value
436 // encoded with two bits, so the assert stays to signal a wrong API usage.
438 // A8-12: DecodeRegShift()
439 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
441 default: assert(0 && "No such value"); return ARM_AM::no_shift;
442 case 0: return ARM_AM::lsl;
443 case 1: return ARM_AM::lsr;
444 case 2: return ARM_AM::asr;
445 case 3: return ARM_AM::ror;
449 // See A8.4 Shifts applied to a register.
450 // A8.4.1 Constant shifts.
452 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
453 // encodings into the intended ShiftOpc and shift amount.
455 // A8-11: DecodeImmShift()
456 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
457 // If type == 0b11 and imm5 == 0, we have an rrx, instead.
458 if (ShOp == ARM_AM::ror && ShImm == 0)
460 // If (lsr or asr) and imm5 == 0, shift amount is 32.
461 if ((ShOp == ARM_AM::lsr || ShOp == ARM_AM::asr) && ShImm == 0)
465 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
466 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
467 // clients should pass in the value encoded with two bits, so the assert stays
468 // to signal a wrong API usage.
469 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
471 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
472 case 1: return ARM_AM::ia; // P=0 U=1
473 case 3: return ARM_AM::ib; // P=1 U=1
474 case 0: return ARM_AM::da; // P=0 U=0
475 case 2: return ARM_AM::db; // P=1 U=0
479 ////////////////////////////////////////////
481 // Disassemble function definitions //
483 ////////////////////////////////////////////
485 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
486 /// instr into a list of MCOperands in the appropriate order, with possible dst,
487 /// followed by possible src(s).
489 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
490 /// the CPSR, is factored into ARMBasicMCBuilder's method named
491 /// TryPredicateAndSBitModifier.
493 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
494 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
496 assert(0 && "Unexpected pseudo instruction!");
500 // Multiply Instructions.
501 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
502 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
504 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
505 // Rd{19-16} Rn{3-0} Rm{11-8}
507 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
508 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
510 // The mapping of the multiply registers to the "regular" ARM registers, where
511 // there are convenience decoder functions, is:
517 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
518 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
520 const TargetInstrDesc &TID = ARMInsts[Opcode];
521 unsigned short NumDefs = TID.getNumDefs();
522 const TargetOperandInfo *OpInfo = TID.OpInfo;
523 unsigned &OpIdx = NumOpsAdded;
527 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
529 && OpInfo[0].RegClass == ARM::GPRRegClassID
530 && OpInfo[1].RegClass == ARM::GPRRegClassID
531 && OpInfo[2].RegClass == ARM::GPRRegClassID
532 && "Expect three register operands");
534 // Instructions with two destination registers have RdLo{15-12} first.
536 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
537 "Expect 4th register operand");
538 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
543 // The destination register: RdHi{19-16} or Rd{19-16}.
544 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
547 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
548 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
550 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
554 // Many multiply instructions (e.g., MLA) have three src registers.
555 // The third register operand is Ra{15-12}.
556 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
557 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
565 // Helper routines for disassembly of coprocessor instructions.
567 static bool LdStCopOpcode(unsigned Opcode) {
568 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
569 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
573 static bool CoprocessorOpcode(unsigned Opcode) {
574 if (LdStCopOpcode(Opcode))
580 case ARM::CDP: case ARM::CDP2:
581 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
582 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
586 static inline unsigned GetCoprocessor(uint32_t insn) {
587 return slice(insn, 11, 8);
589 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
590 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
592 static inline unsigned GetCopOpc2(uint32_t insn) {
593 return slice(insn, 7, 5);
595 static inline unsigned GetCopOpc(uint32_t insn) {
596 return slice(insn, 7, 4);
598 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
601 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
603 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
605 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
607 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
609 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
613 // LDC_OPTION: cop CRd Rn imm8
615 // STC_OPTION: cop CRd Rn imm8
618 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
619 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
621 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
623 unsigned &OpIdx = NumOpsAdded;
624 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
625 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
626 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
627 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
628 bool LdStCop = LdStCopOpcode(Opcode);
632 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
635 // Unindex if P:W = 0b00 --> _OPTION variant
636 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
638 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
640 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
644 MI.addOperand(MCOperand::CreateReg(0));
645 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
646 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
648 MI.addOperand(MCOperand::CreateImm(Offset));
651 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
655 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
656 : GetCopOpc1(insn, NoGPR)));
658 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
659 : MCOperand::CreateReg(
660 getRegisterEnum(B, ARM::GPRRegClassID,
663 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
664 getRegisterEnum(B, ARM::GPRRegClassID,
666 : MCOperand::CreateImm(decodeRn(insn)));
668 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
673 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
681 // Branch Instructions.
682 // BLr9: SignExtend(Imm24:'00', 32)
683 // Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
684 // SMC: ZeroExtend(imm4, 32)
685 // SVC: ZeroExtend(Imm24, 32)
687 // Various coprocessor instructions are assigned BrFrm arbitrarily.
688 // Delegates to DisassembleCoprocessor() helper function.
691 // MSR/MSRsys: Rm mask=Inst{19-16}
693 // MSRi/MSRsysi: so_imm
694 // SRSW/SRS: addrmode4:$addr mode_imm
695 // RFEW/RFE: addrmode4:$addr Rn
696 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
697 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
699 if (CoprocessorOpcode(Opcode))
700 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
702 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
703 if (!OpInfo) return false;
705 // MRS and MRSsys take one GPR reg Rd.
706 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
707 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
708 "Reg operand expected");
709 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
714 // BXJ takes one GPR reg Rm.
715 if (Opcode == ARM::BXJ) {
716 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
717 "Reg operand expected");
718 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
723 // MSR and MSRsys take one GPR reg Rm, followed by the mask.
724 if (Opcode == ARM::MSR || Opcode == ARM::MSRsys) {
725 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
726 "Reg operand expected");
727 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
729 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
733 // MSRi and MSRsysi take one so_imm operand, followed by the mask.
734 if (Opcode == ARM::MSRi || Opcode == ARM::MSRsysi) {
735 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
736 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
737 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
738 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
739 unsigned Imm = insn & 0xFF;
740 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
741 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
745 // SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the
746 // mode immediate (Inst{4-0}).
747 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
748 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
749 // ARMInstPrinter::printAddrMode4Operand() prints special mode string
750 // if the base register is SP; so don't set ARM::SP.
751 MI.addOperand(MCOperand::CreateReg(0));
752 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
753 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
755 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
756 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
758 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
764 assert((Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred
765 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
766 "Unexpected Opcode");
768 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected");
771 if (Opcode == ARM::SMC) {
772 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
773 Imm32 = slice(insn, 3, 0);
774 } else if (Opcode == ARM::SVC) {
775 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
776 Imm32 = slice(insn, 23, 0);
778 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
779 unsigned Imm26 = slice(insn, 23, 0) << 2;
780 //Imm32 = signextend<signed int, 26>(Imm26);
781 Imm32 = SignExtend32<26>(Imm26);
783 // When executing an ARM instruction, PC reads as the address of the current
784 // instruction plus 8. The assembler subtracts 8 from the difference
785 // between the branch instruction and the target address, disassembler has
786 // to add 8 to compensate.
790 MI.addOperand(MCOperand::CreateImm(Imm32));
796 // Misc. Branch Instructions.
797 // BR_JTadd, BR_JTr, BR_JTm
800 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
801 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
803 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
804 if (!OpInfo) return false;
806 unsigned &OpIdx = NumOpsAdded;
810 // BX_RET has only two predicate operands, do an early return.
811 if (Opcode == ARM::BX_RET)
814 // BLXr9 and BRIND take one GPR reg.
815 if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
816 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
817 "Reg operand expected");
818 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
824 // BR_JTadd is an ADD with Rd = PC, (Rn, Rm) as the target and index regs.
825 if (Opcode == ARM::BR_JTadd) {
826 // InOperandList with GPR:$target and GPR:$idx regs.
828 assert(NumOps == 4 && "Expect 4 operands");
829 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
831 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
834 // Fill in the two remaining imm operands to signify build completion.
835 MI.addOperand(MCOperand::CreateImm(0));
836 MI.addOperand(MCOperand::CreateImm(0));
842 // BR_JTr is a MOV with Rd = PC, and Rm as the source register.
843 if (Opcode == ARM::BR_JTr) {
844 // InOperandList with GPR::$target reg.
846 assert(NumOps == 3 && "Expect 3 operands");
847 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
850 // Fill in the two remaining imm operands to signify build completion.
851 MI.addOperand(MCOperand::CreateImm(0));
852 MI.addOperand(MCOperand::CreateImm(0));
858 // BR_JTm is an LDR with Rt = PC.
859 if (Opcode == ARM::BR_JTm) {
860 // This is the reg/reg form, with base reg followed by +/- reg shop imm.
861 // See also ARMAddressingModes.h (Addressing Mode #2).
863 assert(NumOps == 5 && getIBit(insn) == 1 && "Expect 5 operands && I-bit=1");
864 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
867 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
869 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
870 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
872 // Inst{6-5} encodes the shift opcode.
873 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
874 // Inst{11-7} encodes the imm5 shift amount.
875 unsigned ShImm = slice(insn, 11, 7);
877 // A8.4.1. Possible rrx or shift amount of 32...
878 getImmShiftSE(ShOp, ShImm);
879 MI.addOperand(MCOperand::CreateImm(
880 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
882 // Fill in the two remaining imm operands to signify build completion.
883 MI.addOperand(MCOperand::CreateImm(0));
884 MI.addOperand(MCOperand::CreateImm(0));
893 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
894 uint32_t lsb = slice(insn, 11, 7);
895 uint32_t msb = slice(insn, 20, 16);
898 DEBUG(errs() << "Encoding error: msb < lsb\n");
902 for (uint32_t i = lsb; i <= msb; ++i)
908 // A major complication is the fact that some of the saturating add/subtract
909 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
910 // They are QADD, QDADD, QDSUB, and QSUB.
911 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
912 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
914 const TargetInstrDesc &TID = ARMInsts[Opcode];
915 unsigned short NumDefs = TID.getNumDefs();
916 bool isUnary = isUnaryDP(TID.TSFlags);
917 const TargetOperandInfo *OpInfo = TID.OpInfo;
918 unsigned &OpIdx = NumOpsAdded;
922 // Disassemble register def if there is one.
923 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
924 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
929 // Now disassemble the src operands.
933 // Special-case handling of BFC/BFI/SBFX/UBFX.
934 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
935 MI.addOperand(MCOperand::CreateReg(0));
936 if (Opcode == ARM::BFI) {
937 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
942 if (!getBFCInvMask(insn, mask))
945 MI.addOperand(MCOperand::CreateImm(mask));
949 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
950 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
952 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
953 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
958 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
959 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
961 // BinaryDP has an Rn operand.
963 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
964 "Reg operand expected");
965 MI.addOperand(MCOperand::CreateReg(
966 getRegisterEnum(B, ARM::GPRRegClassID,
967 RmRn ? decodeRm(insn) : decodeRn(insn))));
971 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
972 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
973 MI.addOperand(MCOperand::CreateReg(0));
977 // Now disassemble operand 2.
981 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
982 // We have a reg/reg form.
983 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
984 // routed here as well.
985 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
986 MI.addOperand(MCOperand::CreateReg(
987 getRegisterEnum(B, ARM::GPRRegClassID,
988 RmRn? decodeRn(insn) : decodeRm(insn))));
990 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
991 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
992 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
993 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
994 MI.addOperand(MCOperand::CreateImm(Imm16));
997 // We have a reg/imm form.
998 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
999 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
1000 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
1001 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1002 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
1003 unsigned Imm = insn & 0xFF;
1004 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
1011 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1012 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1014 const TargetInstrDesc &TID = ARMInsts[Opcode];
1015 unsigned short NumDefs = TID.getNumDefs();
1016 bool isUnary = isUnaryDP(TID.TSFlags);
1017 const TargetOperandInfo *OpInfo = TID.OpInfo;
1018 unsigned &OpIdx = NumOpsAdded;
1022 // Disassemble register def if there is one.
1023 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
1024 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1029 // Disassemble the src operands.
1030 if (OpIdx >= NumOps)
1033 // BinaryDP has an Rn operand.
1035 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1036 "Reg operand expected");
1037 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1042 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
1043 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1044 MI.addOperand(MCOperand::CreateReg(0));
1048 // Disassemble operand 2, which consists of three components.
1049 if (OpIdx + 2 >= NumOps)
1052 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1053 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
1054 (OpInfo[OpIdx+2].RegClass < 0) &&
1055 "Expect 3 reg operands");
1057 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
1058 unsigned Rs = slice(insn, 4, 4);
1060 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1063 // Register-controlled shifts: [Rm, Rs, shift].
1064 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1066 // Inst{6-5} encodes the shift opcode.
1067 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1068 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
1070 // Constant shifts: [Rm, reg0, shift_imm].
1071 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
1072 // Inst{6-5} encodes the shift opcode.
1073 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1074 // Inst{11-7} encodes the imm5 shift amount.
1075 unsigned ShImm = slice(insn, 11, 7);
1077 // A8.4.1. Possible rrx or shift amount of 32...
1078 getImmShiftSE(ShOp, ShImm);
1079 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1086 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1087 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1089 const TargetInstrDesc &TID = ARMInsts[Opcode];
1090 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1091 const TargetOperandInfo *OpInfo = TID.OpInfo;
1092 if (!OpInfo) return false;
1094 unsigned &OpIdx = NumOpsAdded;
1098 assert(((!isStore && TID.getNumDefs() > 0) ||
1099 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1100 && "Invalid arguments");
1102 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1103 if (isPrePost && isStore) {
1104 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1105 "Reg operand expected");
1106 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1111 // Disassemble the dst/src operand.
1112 if (OpIdx >= NumOps)
1115 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1116 "Reg operand expected");
1117 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1121 // After dst of a pre- and post-indexed load is the address base writeback.
1122 if (isPrePost && !isStore) {
1123 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1124 "Reg operand expected");
1125 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1130 // Disassemble the base operand.
1131 if (OpIdx >= NumOps)
1134 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1135 "Reg operand expected");
1136 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1137 && "Index mode or tied_to operand expected");
1138 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1142 // For reg/reg form, base reg is followed by +/- reg shop imm.
1143 // For immediate form, it is followed by +/- imm12.
1144 // See also ARMAddressingModes.h (Addressing Mode #2).
1145 if (OpIdx + 1 >= NumOps)
1148 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1149 (OpInfo[OpIdx+1].RegClass < 0) &&
1150 "Expect 1 reg operand followed by 1 imm operand");
1152 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1153 if (getIBit(insn) == 0) {
1154 MI.addOperand(MCOperand::CreateReg(0));
1156 // Disassemble the 12-bit immediate offset.
1157 unsigned Imm12 = slice(insn, 11, 0);
1158 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
1159 MI.addOperand(MCOperand::CreateImm(Offset));
1161 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1162 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1164 // Inst{6-5} encodes the shift opcode.
1165 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1166 // Inst{11-7} encodes the imm5 shift amount.
1167 unsigned ShImm = slice(insn, 11, 7);
1169 // A8.4.1. Possible rrx or shift amount of 32...
1170 getImmShiftSE(ShOp, ShImm);
1171 MI.addOperand(MCOperand::CreateImm(
1172 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
1179 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1180 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1181 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1184 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1185 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1186 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1189 static bool HasDualReg(unsigned Opcode) {
1193 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1194 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1199 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1200 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1202 const TargetInstrDesc &TID = ARMInsts[Opcode];
1203 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1204 const TargetOperandInfo *OpInfo = TID.OpInfo;
1205 if (!OpInfo) return false;
1207 unsigned &OpIdx = NumOpsAdded;
1211 assert(((!isStore && TID.getNumDefs() > 0) ||
1212 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1213 && "Invalid arguments");
1215 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1216 if (isPrePost && isStore) {
1217 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1218 "Reg operand expected");
1219 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1224 bool DualReg = HasDualReg(Opcode);
1226 // Disassemble the dst/src operand.
1227 if (OpIdx >= NumOps)
1230 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1231 "Reg operand expected");
1232 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1236 // Fill in LDRD and STRD's second operand.
1238 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1239 decodeRd(insn) + 1)));
1243 // After dst of a pre- and post-indexed load is the address base writeback.
1244 if (isPrePost && !isStore) {
1245 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1246 "Reg operand expected");
1247 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1252 // Disassemble the base operand.
1253 if (OpIdx >= NumOps)
1256 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1257 "Reg operand expected");
1258 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1259 && "Index mode or tied_to operand expected");
1260 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1264 // For reg/reg form, base reg is followed by +/- reg.
1265 // For immediate form, it is followed by +/- imm8.
1266 // See also ARMAddressingModes.h (Addressing Mode #3).
1267 if (OpIdx + 1 >= NumOps)
1270 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1271 (OpInfo[OpIdx+1].RegClass < 0) &&
1272 "Expect 1 reg operand followed by 1 imm operand");
1274 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1275 if (getAM3IBit(insn) == 1) {
1276 MI.addOperand(MCOperand::CreateReg(0));
1278 // Disassemble the 8-bit immediate offset.
1279 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1280 unsigned Imm4L = insn & 0xF;
1281 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1282 MI.addOperand(MCOperand::CreateImm(Offset));
1284 // Disassemble the offset reg (Rm).
1285 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1287 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1288 MI.addOperand(MCOperand::CreateImm(Offset));
1295 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1296 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1297 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1301 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1302 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1303 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1306 // The algorithm for disassembly of LdStMulFrm is different from others because
1307 // it explicitly populates the two predicate operands after operand 0 (the base)
1308 // and operand 1 (the AM4 mode imm). After operand 3, we need to populate the
1309 // reglist with each affected register encoded as an MCOperand.
1310 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1311 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1313 assert(NumOps >= 5 && "LdStMulFrm expects NumOps >= 5");
1315 unsigned &OpIdx = NumOpsAdded;
1319 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1321 // Writeback to base, if necessary.
1322 if (Opcode == ARM::LDM_UPD || Opcode == ARM::STM_UPD) {
1323 MI.addOperand(MCOperand::CreateReg(Base));
1327 MI.addOperand(MCOperand::CreateReg(Base));
1329 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1330 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
1332 // Handling the two predicate operands before the reglist.
1333 int64_t CondVal = insn >> ARMII::CondShift;
1334 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1335 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1339 // Fill the variadic part of reglist.
1340 unsigned RegListBits = insn & ((1 << 16) - 1);
1341 for (unsigned i = 0; i < 16; ++i) {
1342 if ((RegListBits >> i) & 1) {
1343 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1352 // LDREX, LDREXB, LDREXH: Rd Rn
1353 // LDREXD: Rd Rd+1 Rn
1354 // STREX, STREXB, STREXH: Rd Rm Rn
1355 // STREXD: Rd Rm Rm+1 Rn
1357 // SWP, SWPB: Rd Rm Rn
1358 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1359 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1361 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1362 if (!OpInfo) return false;
1364 unsigned &OpIdx = NumOpsAdded;
1369 && OpInfo[0].RegClass == ARM::GPRRegClassID
1370 && OpInfo[1].RegClass == ARM::GPRRegClassID
1371 && "Expect 2 reg operands");
1373 bool isStore = slice(insn, 20, 20) == 0;
1374 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1376 // Add the destination operand.
1377 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1381 // Store register Exclusive needs a source operand.
1383 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1388 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1389 decodeRm(insn)+1)));
1393 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1394 decodeRd(insn)+1)));
1398 // Finally add the pointer operand.
1399 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1406 // Misc. Arithmetic Instructions.
1408 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1409 // RBIT, REV, REV16, REVSH: Rd Rm
1410 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1411 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1413 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1414 unsigned &OpIdx = NumOpsAdded;
1419 && OpInfo[0].RegClass == ARM::GPRRegClassID
1420 && OpInfo[1].RegClass == ARM::GPRRegClassID
1421 && "Expect 2 reg operands");
1423 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1425 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1430 assert(NumOps >= 4 && "Expect >= 4 operands");
1431 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1436 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1440 // If there is still an operand info left which is an immediate operand, add
1441 // an additional imm5 LSL/ASR operand.
1442 if (ThreeReg && OpInfo[OpIdx].RegClass < 0
1443 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1444 // Extract the 5-bit immediate field Inst{11-7}.
1445 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1446 MI.addOperand(MCOperand::CreateImm(ShiftAmt));
1453 /// DisassembleSatFrm - Disassemble saturate instructions:
1454 /// SSAT, SSAT16, USAT, and USAT16.
1455 static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1456 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1458 const TargetInstrDesc &TID = ARMInsts[Opcode];
1459 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1461 // Disassemble register def.
1462 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1465 unsigned Pos = slice(insn, 20, 16);
1466 if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16)
1468 MI.addOperand(MCOperand::CreateImm(Pos));
1470 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1473 if (NumOpsAdded == 4) {
1474 ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
1475 // Inst{11-7} encodes the imm5 shift amount.
1476 unsigned ShAmt = slice(insn, 11, 7);
1478 // A8.6.183. Possible ASR shift amount of 32...
1479 if (Opc == ARM_AM::asr)
1482 Opc = ARM_AM::no_shift;
1484 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
1489 // Extend instructions.
1490 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1491 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1492 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1493 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1494 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1496 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1497 unsigned &OpIdx = NumOpsAdded;
1502 && OpInfo[0].RegClass == ARM::GPRRegClassID
1503 && OpInfo[1].RegClass == ARM::GPRRegClassID
1504 && "Expect 2 reg operands");
1506 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1508 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1513 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1518 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1522 // If there is still an operand info left which is an immediate operand, add
1523 // an additional rotate immediate operand.
1524 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1525 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1526 // Extract the 2-bit rotate field Inst{11-10}.
1527 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1528 // Rotation by 8, 16, or 24 bits.
1529 MI.addOperand(MCOperand::CreateImm(rot << 3));
1536 /////////////////////////////////////
1538 // Utility Functions For VFP //
1540 /////////////////////////////////////
1542 // Extract/Decode Dd/Sd:
1544 // SP => d = UInt(Vd:D)
1545 // DP => d = UInt(D:Vd)
1546 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1547 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1548 : (decodeRd(insn) | getDBit(insn) << 4);
1551 // Extract/Decode Dn/Sn:
1553 // SP => n = UInt(Vn:N)
1554 // DP => n = UInt(N:Vn)
1555 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1556 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1557 : (decodeRn(insn) | getNBit(insn) << 4);
1560 // Extract/Decode Dm/Sm:
1562 // SP => m = UInt(Vm:M)
1563 // DP => m = UInt(M:Vm)
1564 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1565 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1566 : (decodeRm(insn) | getMBit(insn) << 4);
1571 static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
1572 assert(N == 32 || N == 64);
1575 unsigned bit6 = slice(byte, 6, 6);
1577 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1579 Result |= 0x1f << 25;
1581 Result |= 0x1 << 30;
1583 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1584 (uint64_t)slice(byte, 5, 0) << 48;
1586 Result |= 0xffL << 54;
1588 Result |= 0x1L << 62;
1594 // VFP Unary Format Instructions:
1596 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1597 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1598 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1599 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1600 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1602 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1604 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1605 unsigned &OpIdx = NumOpsAdded;
1609 unsigned RegClass = OpInfo[OpIdx].RegClass;
1610 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1611 "Reg operand expected");
1612 bool isSP = (RegClass == ARM::SPRRegClassID);
1614 MI.addOperand(MCOperand::CreateReg(
1615 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1618 // Early return for compare with zero instructions.
1619 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1620 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1623 RegClass = OpInfo[OpIdx].RegClass;
1624 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1625 "Reg operand expected");
1626 isSP = (RegClass == ARM::SPRRegClassID);
1628 MI.addOperand(MCOperand::CreateReg(
1629 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1635 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1636 // Some of them have operand constraints which tie the first operand in the
1637 // InOperandList to that of the dst. As far as asm printing is concerned, this
1638 // tied_to operand is simply skipped.
1639 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1640 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1642 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1644 const TargetInstrDesc &TID = ARMInsts[Opcode];
1645 const TargetOperandInfo *OpInfo = TID.OpInfo;
1646 unsigned &OpIdx = NumOpsAdded;
1650 unsigned RegClass = OpInfo[OpIdx].RegClass;
1651 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1652 "Reg operand expected");
1653 bool isSP = (RegClass == ARM::SPRRegClassID);
1655 MI.addOperand(MCOperand::CreateReg(
1656 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1659 // Skip tied_to operand constraint.
1660 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1661 assert(NumOps >= 4 && "Expect >=4 operands");
1662 MI.addOperand(MCOperand::CreateReg(0));
1666 MI.addOperand(MCOperand::CreateReg(
1667 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1670 MI.addOperand(MCOperand::CreateReg(
1671 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1677 // A8.6.295 vcvt (floating-point <-> integer)
1678 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1679 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1681 // A8.6.297 vcvt (floating-point and fixed-point)
1682 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1683 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1684 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1686 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1688 const TargetInstrDesc &TID = ARMInsts[Opcode];
1689 const TargetOperandInfo *OpInfo = TID.OpInfo;
1690 if (!OpInfo) return false;
1692 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1693 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1694 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1698 assert(NumOps >= 3 && "Expect >= 3 operands");
1699 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1700 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1701 MI.addOperand(MCOperand::CreateReg(
1702 getRegisterEnum(B, RegClassID,
1703 decodeVFPRd(insn, SP))));
1705 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1706 "Tied to operand expected");
1707 MI.addOperand(MI.getOperand(0));
1709 assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() &&
1710 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1711 MI.addOperand(MCOperand::CreateImm(fbits));
1716 // The Rd (destination) and Rm (source) bits have different interpretations
1717 // depending on their single-precisonness.
1719 if (slice(insn, 18, 18) == 1) { // to_integer operation
1720 d = decodeVFPRd(insn, true /* Is Single Precision */);
1721 MI.addOperand(MCOperand::CreateReg(
1722 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1723 m = decodeVFPRm(insn, SP);
1724 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1726 d = decodeVFPRd(insn, SP);
1727 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1728 m = decodeVFPRm(insn, true /* Is Single Precision */);
1729 MI.addOperand(MCOperand::CreateReg(
1730 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1738 // VMOVRS - A8.6.330
1739 // Rt => Rd; Sn => UInt(Vn:N)
1740 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1741 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1743 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1745 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1747 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1748 decodeVFPRn(insn, true))));
1753 // VMOVRRD - A8.6.332
1754 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1756 // VMOVRRS - A8.6.331
1757 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1758 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1759 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1761 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1763 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1764 unsigned &OpIdx = NumOpsAdded;
1766 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1768 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1772 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1773 unsigned Sm = decodeVFPRm(insn, true);
1774 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1776 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1780 MI.addOperand(MCOperand::CreateReg(
1781 getRegisterEnum(B, ARM::DPRRegClassID,
1782 decodeVFPRm(insn, false))));
1788 // VMOVSR - A8.6.330
1789 // Rt => Rd; Sn => UInt(Vn:N)
1790 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1791 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1793 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1795 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1796 decodeVFPRn(insn, true))));
1797 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1803 // VMOVDRR - A8.6.332
1804 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1806 // VMOVRRS - A8.6.331
1807 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1808 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1809 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1811 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1813 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1814 unsigned &OpIdx = NumOpsAdded;
1818 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1819 unsigned Sm = decodeVFPRm(insn, true);
1820 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1822 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1826 MI.addOperand(MCOperand::CreateReg(
1827 getRegisterEnum(B, ARM::DPRRegClassID,
1828 decodeVFPRm(insn, false))));
1832 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1834 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1840 // VFP Load/Store Instructions.
1841 // VLDRD, VLDRS, VSTRD, VSTRS
1842 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1843 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1845 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1847 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS) ? true : false;
1848 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1850 // Extract Dd/Sd for operand 0.
1851 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1853 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1855 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1856 MI.addOperand(MCOperand::CreateReg(Base));
1858 // Next comes the AM5 Opcode.
1859 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1860 unsigned char Imm8 = insn & 0xFF;
1861 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1868 // VFP Load/Store Multiple Instructions.
1869 // This is similar to the algorithm for LDM/STM in that operand 0 (the base) and
1870 // operand 1 (the AM5 mode imm) is followed by two predicate operands. It is
1871 // followed by a reglist of either DPR(s) or SPR(s).
1873 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1874 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1875 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1877 assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
1879 unsigned &OpIdx = NumOpsAdded;
1883 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1885 // Writeback to base, if necessary.
1886 if (Opcode == ARM::VLDMD_UPD || Opcode == ARM::VLDMS_UPD ||
1887 Opcode == ARM::VSTMD_UPD || Opcode == ARM::VSTMS_UPD) {
1888 MI.addOperand(MCOperand::CreateReg(Base));
1892 MI.addOperand(MCOperand::CreateReg(Base));
1894 // Next comes the AM5 Opcode.
1895 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1896 // Must be either "ia" or "db" submode.
1897 if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) {
1898 DEBUG(errs() << "Illegal addressing mode 5 sub-mode!\n");
1902 unsigned char Imm8 = insn & 0xFF;
1903 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(SubMode, Imm8)));
1905 // Handling the two predicate operands before the reglist.
1906 int64_t CondVal = insn >> ARMII::CondShift;
1907 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1908 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1912 bool isSPVFP = (Opcode == ARM::VLDMS || Opcode == ARM::VLDMS_UPD ||
1913 Opcode == ARM::VSTMS || Opcode == ARM::VSTMS_UPD) ? true : false;
1914 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1917 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1919 // Fill the variadic part of reglist.
1920 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1921 for (unsigned i = 0; i < Regs; ++i) {
1922 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1930 // Misc. VFP Instructions.
1931 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1932 // FCONSTD (DPR and a VFPf64Imm operand)
1933 // FCONSTS (SPR and a VFPf32Imm operand)
1934 // VMRS/VMSR (GPR operand)
1935 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1936 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1938 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1939 unsigned &OpIdx = NumOpsAdded;
1943 if (Opcode == ARM::FMSTAT)
1946 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1948 unsigned RegEnum = 0;
1949 switch (OpInfo[0].RegClass) {
1950 case ARM::DPRRegClassID:
1951 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1953 case ARM::SPRRegClassID:
1954 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1956 case ARM::GPRRegClassID:
1957 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1960 assert(0 && "Invalid reg class id");
1964 MI.addOperand(MCOperand::CreateReg(RegEnum));
1967 // Extract/decode the f64/f32 immediate.
1968 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1969 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1970 // The asm syntax specifies the before-expanded <imm>.
1971 // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1972 // Opcode == ARM::FCONSTD ? 64 : 32)
1973 MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0)));
1980 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
1981 #include "ThumbDisassemblerCore.h"
1983 /////////////////////////////////////////////////////
1985 // Utility Functions For ARM Advanced SIMD //
1987 /////////////////////////////////////////////////////
1989 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
1990 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
1992 // A7.3 Register encoding
1994 // Extract/Decode NEON D/Vd:
1996 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
1997 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
1998 // handling it in the getRegisterEnum() utility function.
1999 // D = Inst{22}, Vd = Inst{15-12}
2000 static unsigned decodeNEONRd(uint32_t insn) {
2001 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
2002 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
2005 // Extract/Decode NEON N/Vn:
2007 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
2008 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
2009 // handling it in the getRegisterEnum() utility function.
2010 // N = Inst{7}, Vn = Inst{19-16}
2011 static unsigned decodeNEONRn(uint32_t insn) {
2012 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
2013 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
2016 // Extract/Decode NEON M/Vm:
2018 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
2019 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
2020 // handling it in the getRegisterEnum() utility function.
2021 // M = Inst{5}, Vm = Inst{3-0}
2022 static unsigned decodeNEONRm(uint32_t insn) {
2023 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
2024 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
2035 } // End of unnamed namespace
2037 // size field -> Inst{11-10}
2038 // index_align field -> Inst{7-4}
2040 // The Lane Index interpretation depends on the Data Size:
2041 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
2042 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
2043 // 32 (encoded as size = 0b10) -> Index = index_align[3]
2045 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
2046 static unsigned decodeLaneIndex(uint32_t insn) {
2047 unsigned size = insn >> 10 & 3;
2048 assert((size == 0 || size == 1 || size == 2) &&
2049 "Encoding error: size should be either 0, 1, or 2");
2051 unsigned index_align = insn >> 4 & 0xF;
2052 return (index_align >> 1) >> size;
2055 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
2056 // op = Inst{5}, cmode = Inst{11-8}
2057 // i = Inst{24} (ARM architecture)
2058 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
2059 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
2060 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
2061 unsigned char op = (insn >> 5) & 1;
2062 unsigned char cmode = (insn >> 8) & 0xF;
2063 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
2064 ((insn >> 16) & 7) << 4 |
2066 return (op << 12) | (cmode << 8) | Imm8;
2069 // A8.6.339 VMUL, VMULL (by scalar)
2070 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2071 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2072 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2079 assert(0 && "Unreachable code!");
2084 // A8.6.339 VMUL, VMULL (by scalar)
2085 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2086 // ESize32 => index = Inst{5} (M) D0-D15
2087 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2090 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2092 return (insn >> 5) & 1;
2094 assert(0 && "Unreachable code!");
2099 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2100 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2101 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2102 return 64 - ((insn >> 16) & 0x3F);
2105 // A8.6.302 VDUP (scalar)
2106 // ESize8 => index = Inst{19-17}
2107 // ESize16 => index = Inst{19-18}
2108 // ESize32 => index = Inst{19}
2109 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2112 return (insn >> 17) & 7;
2114 return (insn >> 18) & 3;
2116 return (insn >> 19) & 1;
2118 assert(0 && "Unspecified element size!");
2123 // A8.6.328 VMOV (ARM core register to scalar)
2124 // A8.6.329 VMOV (scalar to ARM core register)
2125 // ESize8 => index = Inst{21:6-5}
2126 // ESize16 => index = Inst{21:6}
2127 // ESize32 => index = Inst{21}
2128 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2131 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2133 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2135 return ((insn >> 21) & 1);
2137 assert(0 && "Unspecified element size!");
2142 // Imm6 = Inst{21-16}, L = Inst{7}
2144 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2146 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2147 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2148 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2149 // '1xxxxxx' => esize = 64; shift_amount = imm6
2151 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2153 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2154 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2155 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2156 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2158 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2159 ElemSize esize = ESizeNA;
2160 unsigned L = (insn >> 7) & 1;
2161 unsigned imm6 = (insn >> 16) & 0x3F;
2165 else if (imm6 >> 4 == 1)
2167 else if (imm6 >> 5 == 1)
2170 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2175 return esize == ESize64 ? imm6 : (imm6 - esize);
2177 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2181 // Imm4 = Inst{11-8}
2182 static unsigned decodeN3VImm(uint32_t insn) {
2183 return (insn >> 8) & 0xF;
2186 static bool UseDRegPair(unsigned Opcode) {
2190 case ARM::VLD1q8_UPD:
2191 case ARM::VLD1q16_UPD:
2192 case ARM::VLD1q32_UPD:
2193 case ARM::VLD1q64_UPD:
2194 case ARM::VST1q8_UPD:
2195 case ARM::VST1q16_UPD:
2196 case ARM::VST1q32_UPD:
2197 case ARM::VST1q64_UPD:
2203 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2205 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2207 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2209 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2211 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2212 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2213 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2216 const TargetInstrDesc &TID = ARMInsts[Opcode];
2217 const TargetOperandInfo *OpInfo = TID.OpInfo;
2219 // At least one DPR register plus addressing mode #6.
2220 assert(NumOps >= 3 && "Expect >= 3 operands");
2222 unsigned &OpIdx = NumOpsAdded;
2226 // We have homogeneous NEON registers for Load/Store.
2227 unsigned RegClass = 0;
2228 bool DRegPair = UseDRegPair(Opcode);
2230 // Double-spaced registers have increments of 2.
2231 unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1;
2233 unsigned Rn = decodeRn(insn);
2234 unsigned Rm = decodeRm(insn);
2235 unsigned Rd = decodeNEONRd(insn);
2237 // A7.7.1 Advanced SIMD addressing mode.
2240 // LLVM Addressing Mode #6.
2241 unsigned RmEnum = 0;
2243 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2246 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2247 // then possible lane index.
2248 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2249 "Reg operand expected");
2252 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2257 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2258 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2259 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2261 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2265 MI.addOperand(MCOperand::CreateReg(RmEnum));
2269 assert(OpIdx < NumOps &&
2270 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2271 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2272 "Reg operand expected");
2274 RegClass = OpInfo[OpIdx].RegClass;
2275 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2276 MI.addOperand(MCOperand::CreateReg(
2277 getRegisterEnum(B, RegClass, Rd, DRegPair)));
2282 // Handle possible lane index.
2283 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2284 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2285 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2290 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2291 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2292 RegClass = OpInfo[0].RegClass;
2294 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2295 MI.addOperand(MCOperand::CreateReg(
2296 getRegisterEnum(B, RegClass, Rd, DRegPair)));
2302 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2307 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2308 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2309 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2311 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2315 MI.addOperand(MCOperand::CreateReg(RmEnum));
2319 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2320 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2321 "Tied to operand expected");
2322 MI.addOperand(MCOperand::CreateReg(0));
2326 // Handle possible lane index.
2327 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2328 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2329 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2334 // Accessing registers past the end of the NEON register file is not
2343 // If L (Inst{21}) == 0, store instructions.
2344 // Find out about double-spaced-ness of the Opcode and pass it on to
2345 // DisassembleNLdSt0().
2346 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2347 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2349 const StringRef Name = ARMInsts[Opcode].Name;
2350 bool DblSpaced = false;
2352 if (Name.find("LN") != std::string::npos) {
2353 // To one lane instructions.
2354 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2356 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2357 if (Name.endswith("16") || Name.endswith("16_UPD"))
2358 DblSpaced = slice(insn, 5, 5) == 1;
2360 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2361 if (Name.endswith("32") || Name.endswith("32_UPD"))
2362 DblSpaced = slice(insn, 6, 6) == 1;
2365 // Multiple n-element structures with type encoded as Inst{11-8}.
2366 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2368 // n == 2 && type == 0b1001 -> DblSpaced = true
2369 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2370 DblSpaced = slice(insn, 11, 8) == 9;
2372 // n == 3 && type == 0b0101 -> DblSpaced = true
2373 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2374 DblSpaced = slice(insn, 11, 8) == 5;
2376 // n == 4 && type == 0b0001 -> DblSpaced = true
2377 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2378 DblSpaced = slice(insn, 11, 8) == 1;
2381 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2382 slice(insn, 21, 21) == 0, DblSpaced, B);
2387 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2388 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2390 const TargetInstrDesc &TID = ARMInsts[Opcode];
2391 const TargetOperandInfo *OpInfo = TID.OpInfo;
2393 assert(NumOps >= 2 &&
2394 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2395 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2396 (OpInfo[1].RegClass < 0) &&
2397 "Expect 1 reg operand followed by 1 imm operand");
2399 // Qd/Dd = Inst{22:15-12} => NEON Rd
2400 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2401 decodeNEONRd(insn))));
2403 ElemSize esize = ESizeNA;
2406 case ARM::VMOVv16i8:
2409 case ARM::VMOVv4i16:
2410 case ARM::VMOVv8i16:
2411 case ARM::VMVNv4i16:
2412 case ARM::VMVNv8i16:
2415 case ARM::VMOVv2i32:
2416 case ARM::VMOVv4i32:
2417 case ARM::VMVNv2i32:
2418 case ARM::VMVNv4i32:
2421 case ARM::VMOVv1i64:
2422 case ARM::VMOVv2i64:
2426 assert(0 && "Unreachable code!");
2430 // One register and a modified immediate value.
2431 // Add the imm operand.
2432 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2442 N2V_VectorConvert_Between_Float_Fixed
2444 } // End of unnamed namespace
2446 // Vector Convert [between floating-point and fixed-point]
2447 // Qd/Dd Qm/Dm [fbits]
2449 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2450 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2453 // Vector Move Long:
2456 // Vector Move Narrow:
2460 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2461 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2463 const TargetInstrDesc &TID = ARMInsts[Opc];
2464 const TargetOperandInfo *OpInfo = TID.OpInfo;
2466 assert(NumOps >= 2 &&
2467 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2468 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2469 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2470 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2471 "Expect >= 2 operands and first 2 as reg operands");
2473 unsigned &OpIdx = NumOpsAdded;
2477 ElemSize esize = ESizeNA;
2478 if (Flag == N2V_VectorDupLane) {
2479 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2480 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2481 "Unexpected Opcode");
2482 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2483 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2487 // Qd/Dd = Inst{22:15-12} => NEON Rd
2488 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2489 decodeNEONRd(insn))));
2493 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2495 MI.addOperand(MCOperand::CreateReg(0));
2499 // Dm = Inst{5:3-0} => NEON Rm
2500 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2501 decodeNEONRm(insn))));
2504 // VZIP and others have two TIED_TO reg operands.
2506 while (OpIdx < NumOps &&
2507 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2508 // Add TIED_TO operand.
2509 MI.addOperand(MI.getOperand(Idx));
2513 // Add the imm operand, if required.
2514 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2515 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2517 unsigned imm = 0xFFFFFFFF;
2519 if (Flag == N2V_VectorDupLane)
2520 imm = decodeNVLaneDupIndex(insn, esize);
2521 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2522 imm = decodeVCVTFractionBits(insn);
2524 assert(imm != 0xFFFFFFFF && "Internal error");
2525 MI.addOperand(MCOperand::CreateImm(imm));
2532 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2533 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2535 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2538 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2539 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2541 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2542 N2V_VectorConvert_Between_Float_Fixed, B);
2544 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2545 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2547 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2548 N2V_VectorDupLane, B);
2551 // Vector Shift [Accumulate] Instructions.
2552 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2554 // Vector Shift Left Long (with maximum shift count) Instructions.
2555 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2557 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2558 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2560 const TargetInstrDesc &TID = ARMInsts[Opcode];
2561 const TargetOperandInfo *OpInfo = TID.OpInfo;
2563 assert(NumOps >= 3 &&
2564 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2565 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2566 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2567 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2568 "Expect >= 3 operands and first 2 as reg operands");
2570 unsigned &OpIdx = NumOpsAdded;
2574 // Qd/Dd = Inst{22:15-12} => NEON Rd
2575 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2576 decodeNEONRd(insn))));
2579 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2581 MI.addOperand(MCOperand::CreateReg(0));
2585 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2586 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2587 "Reg operand expected");
2589 // Qm/Dm = Inst{5:3-0} => NEON Rm
2590 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2591 decodeNEONRm(insn))));
2594 assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
2596 // Add the imm operand.
2598 // VSHLL has maximum shift count as the imm, inferred from its size.
2602 Imm = decodeNVSAmt(insn, LeftShift);
2614 MI.addOperand(MCOperand::CreateImm(Imm));
2620 // Left shift instructions.
2621 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2622 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2624 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2627 // Right shift instructions have different shift amount interpretation.
2628 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2629 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2631 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2640 N3V_Multiply_By_Scalar
2642 } // End of unnamed namespace
2644 // NEON Three Register Instructions with Optional Immediate Operand
2646 // Vector Extract Instructions.
2647 // Qd/Dd Qn/Dn Qm/Dm imm4
2649 // Vector Shift (Register) Instructions.
2650 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2652 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2653 // Qd/Dd Qn/Dn RestrictedDm index
2656 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2657 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2659 const TargetInstrDesc &TID = ARMInsts[Opcode];
2660 const TargetOperandInfo *OpInfo = TID.OpInfo;
2662 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2663 assert(NumOps >= 3 &&
2664 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2665 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2666 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2667 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2668 "Expect >= 3 operands and first 2 as reg operands");
2670 unsigned &OpIdx = NumOpsAdded;
2674 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2675 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2676 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2677 ElemSize esize = ESizeNA;
2678 if (Flag == N3V_Multiply_By_Scalar) {
2679 unsigned size = (insn >> 20) & 3;
2680 if (size == 1) esize = ESize16;
2681 if (size == 2) esize = ESize32;
2682 assert (esize == ESize16 || esize == ESize32);
2685 // Qd/Dd = Inst{22:15-12} => NEON Rd
2686 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2687 decodeNEONRd(insn))));
2690 // VABA, VABAL, VBSLd, VBSLq, ...
2691 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2693 MI.addOperand(MCOperand::CreateReg(0));
2697 // Dn = Inst{7:19-16} => NEON Rn
2699 // Dm = Inst{5:3-0} => NEON Rm
2700 MI.addOperand(MCOperand::CreateReg(
2701 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2702 VdVnVm ? decodeNEONRn(insn)
2703 : decodeNEONRm(insn))));
2706 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2708 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2711 // Dm = Inst{5:3-0} => NEON Rm
2713 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2715 // Dn = Inst{7:19-16} => NEON Rn
2716 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2717 : decodeNEONRm(insn))
2718 : decodeNEONRn(insn);
2720 MI.addOperand(MCOperand::CreateReg(
2721 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2724 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2725 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2726 // Add the imm operand.
2729 Imm = decodeN3VImm(insn);
2730 else if (IsDmRestricted)
2731 Imm = decodeRestrictedDmIndex(insn, esize);
2733 assert(0 && "Internal error: unreachable code!");
2737 MI.addOperand(MCOperand::CreateImm(Imm));
2744 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2745 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2747 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2750 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2751 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2753 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2754 N3V_VectorShift, B);
2756 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2757 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2759 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2760 N3V_VectorExtract, B);
2762 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2763 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2765 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2766 N3V_Multiply_By_Scalar, B);
2769 // Vector Table Lookup
2771 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2772 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2773 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2774 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2775 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2776 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2778 const TargetInstrDesc &TID = ARMInsts[Opcode];
2779 const TargetOperandInfo *OpInfo = TID.OpInfo;
2780 if (!OpInfo) return false;
2782 assert(NumOps >= 3 &&
2783 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2784 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2785 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2786 "Expect >= 3 operands and first 3 as reg operands");
2788 unsigned &OpIdx = NumOpsAdded;
2792 unsigned Rn = decodeNEONRn(insn);
2794 // {Dn} encoded as len = 0b00
2795 // {Dn Dn+1} encoded as len = 0b01
2796 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2797 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2798 unsigned Len = slice(insn, 9, 8) + 1;
2800 // Dd (the destination vector)
2801 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2802 decodeNEONRd(insn))));
2805 // Process tied_to operand constraint.
2807 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2808 MI.addOperand(MI.getOperand(Idx));
2812 // Do the <list> now.
2813 for (unsigned i = 0; i < Len; ++i) {
2814 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2815 "Reg operand expected");
2816 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2821 // Dm (the index vector)
2822 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2823 "Reg operand (index vector) expected");
2824 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2825 decodeNEONRm(insn))));
2831 // Vector Get Lane (move scalar to ARM core register) Instructions.
2832 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2833 static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2834 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2836 const TargetInstrDesc &TID = ARMInsts[Opcode];
2837 const TargetOperandInfo *OpInfo = TID.OpInfo;
2838 if (!OpInfo) return false;
2840 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2841 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2842 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2843 OpInfo[2].RegClass < 0 &&
2844 "Expect >= 3 operands with one dst operand");
2847 Opcode == ARM::VGETLNi32 ? ESize32
2848 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2851 // Rt = Inst{15-12} => ARM Rd
2852 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2855 // Dn = Inst{7:19-16} => NEON Rn
2856 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2857 decodeNEONRn(insn))));
2859 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2865 // Vector Set Lane (move ARM core register to scalar) Instructions.
2866 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2867 static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2868 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2870 const TargetInstrDesc &TID = ARMInsts[Opcode];
2871 const TargetOperandInfo *OpInfo = TID.OpInfo;
2872 if (!OpInfo) return false;
2874 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2875 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2876 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2877 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2878 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2879 OpInfo[3].RegClass < 0 &&
2880 "Expect >= 3 operands with one dst operand");
2883 Opcode == ARM::VSETLNi8 ? ESize8
2884 : (Opcode == ARM::VSETLNi16 ? ESize16
2887 // Dd = Inst{7:19-16} => NEON Rn
2888 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2889 decodeNEONRn(insn))));
2892 MI.addOperand(MCOperand::CreateReg(0));
2894 // Rt = Inst{15-12} => ARM Rd
2895 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2898 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2904 // Vector Duplicate Instructions (from ARM core register to all elements).
2905 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2906 static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2907 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2909 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2911 assert(NumOps >= 2 &&
2912 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2913 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2914 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2915 "Expect >= 2 operands and first 2 as reg operand");
2917 unsigned RegClass = OpInfo[0].RegClass;
2919 // Qd/Dd = Inst{7:19-16} => NEON Rn
2920 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2921 decodeNEONRn(insn))));
2923 // Rt = Inst{15-12} => ARM Rd
2924 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2934 static inline bool MemBarrierInstr(uint32_t insn) {
2935 unsigned op7_4 = slice(insn, 7, 4);
2936 if (slice(insn, 31, 20) == 0xf57 && (op7_4 >= 4 && op7_4 <= 6))
2942 static inline bool PreLoadOpcode(unsigned Opcode) {
2944 case ARM::PLDi: case ARM::PLDr:
2945 case ARM::PLDWi: case ARM::PLDWr:
2946 case ARM::PLIi: case ARM::PLIr:
2953 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2954 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2956 // Preload Data/Instruction requires either 2 or 4 operands.
2957 // PLDi, PLDWi, PLIi: Rn [+/-]imm12 add = (U == '1')
2958 // PLDr[a|m], PLDWr[a|m], PLIr[a|m]: Rn Rm addrmode2_opc
2960 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2963 if (Opcode == ARM::PLDi || Opcode == ARM::PLDWi || Opcode == ARM::PLIi) {
2964 unsigned Imm12 = slice(insn, 11, 0);
2965 bool Negative = getUBit(insn) == 0;
2966 int Offset = Negative ? -1 - Imm12 : 1 * Imm12;
2967 MI.addOperand(MCOperand::CreateImm(Offset));
2970 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2973 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
2975 // Inst{6-5} encodes the shift opcode.
2976 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
2977 // Inst{11-7} encodes the imm5 shift amount.
2978 unsigned ShImm = slice(insn, 11, 7);
2980 // A8.4.1. Possible rrx or shift amount of 32...
2981 getImmShiftSE(ShOp, ShImm);
2982 MI.addOperand(MCOperand::CreateImm(
2983 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
2990 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2991 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2993 if (MemBarrierInstr(insn))
3011 // CPS has a singleton $opt operand that contains the following information:
3012 // opt{4-0} = mode from Inst{4-0}
3013 // opt{5} = changemode from Inst{17}
3014 // opt{8-6} = AIF from Inst{8-6}
3015 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3016 if (Opcode == ARM::CPS) {
3017 unsigned Option = slice(insn, 4, 0) | slice(insn, 17, 17) << 5 |
3018 slice(insn, 8, 6) << 6 | slice(insn, 19, 18) << 9;
3019 MI.addOperand(MCOperand::CreateImm(Option));
3024 // DBG has its option specified in Inst{3-0}.
3025 if (Opcode == ARM::DBG) {
3026 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3031 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
3032 if (Opcode == ARM::BKPT) {
3033 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
3034 slice(insn, 3, 0)));
3039 if (PreLoadOpcode(Opcode))
3040 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
3042 assert(0 && "Unexpected misc instruction!");
3046 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
3047 /// We divide the disassembly task into different categories, with each one
3048 /// corresponding to a specific instruction encoding format. There could be
3049 /// exceptions when handling a specific format, and that is why the Opcode is
3050 /// also present in the function prototype.
3051 static const DisassembleFP FuncPtrs[] = {
3055 &DisassembleBrMiscFrm,
3057 &DisassembleDPSoRegFrm,
3060 &DisassembleLdMiscFrm,
3061 &DisassembleStMiscFrm,
3062 &DisassembleLdStMulFrm,
3063 &DisassembleLdStExFrm,
3064 &DisassembleArithMiscFrm,
3067 &DisassembleVFPUnaryFrm,
3068 &DisassembleVFPBinaryFrm,
3069 &DisassembleVFPConv1Frm,
3070 &DisassembleVFPConv2Frm,
3071 &DisassembleVFPConv3Frm,
3072 &DisassembleVFPConv4Frm,
3073 &DisassembleVFPConv5Frm,
3074 &DisassembleVFPLdStFrm,
3075 &DisassembleVFPLdStMulFrm,
3076 &DisassembleVFPMiscFrm,
3077 &DisassembleThumbFrm,
3078 &DisassembleMiscFrm,
3079 &DisassembleNGetLnFrm,
3080 &DisassembleNSetLnFrm,
3081 &DisassembleNDupFrm,
3083 // VLD and VST (including one lane) Instructions.
3086 // A7.4.6 One register and a modified immediate value
3087 // 1-Register Instructions with imm.
3088 // LLVM only defines VMOVv instructions.
3089 &DisassembleN1RegModImmFrm,
3091 // 2-Register Instructions with no imm.
3092 &DisassembleN2RegFrm,
3094 // 2-Register Instructions with imm (vector convert float/fixed point).
3095 &DisassembleNVCVTFrm,
3097 // 2-Register Instructions with imm (vector dup lane).
3098 &DisassembleNVecDupLnFrm,
3100 // Vector Shift Left Instructions.
3101 &DisassembleN2RegVecShLFrm,
3103 // Vector Shift Righ Instructions, which has different interpretation of the
3104 // shift amount from the imm6 field.
3105 &DisassembleN2RegVecShRFrm,
3107 // 3-Register Data-Processing Instructions.
3108 &DisassembleN3RegFrm,
3110 // Vector Shift (Register) Instructions.
3111 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3112 &DisassembleN3RegVecShFrm,
3114 // Vector Extract Instructions.
3115 &DisassembleNVecExtractFrm,
3117 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3118 // By Scalar Instructions.
3119 &DisassembleNVecMulScalarFrm,
3121 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3122 // values in a table and generate a new vector.
3123 &DisassembleNVTBLFrm,
3128 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3129 /// The general idea is to set the Opcode for the MCInst, followed by adding
3130 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3131 /// to the Format-specific disassemble function for disassembly, followed by
3132 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3133 /// which follow the Dst/Src Operands.
3134 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3135 // Stage 1 sets the Opcode.
3136 MI.setOpcode(Opcode);
3137 // If the number of operands is zero, we're done!
3141 // Stage 2 calls the format-specific disassemble function to build the operand
3145 unsigned NumOpsAdded = 0;
3146 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3148 if (!OK || this->Err != 0) return false;
3149 if (NumOpsAdded >= NumOps)
3152 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3153 // FIXME: Should this be done selectively?
3154 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3157 // A8.3 Conditional execution
3158 // A8.3.1 Pseudocode details of conditional execution
3159 // Condition bits '111x' indicate the instruction is always executed.
3160 static uint32_t CondCode(uint32_t CondField) {
3161 if (CondField == 0xF)
3166 /// DoPredicateOperands - DoPredicateOperands process the predicate operands
3167 /// of some Thumb instructions which come before the reglist operands. It
3168 /// returns true if the two predicate operands have been processed.
3169 bool ARMBasicMCBuilder::DoPredicateOperands(MCInst& MI, unsigned Opcode,
3170 uint32_t /* insn */, unsigned short NumOpsRemaining) {
3172 assert(NumOpsRemaining > 0 && "Invalid argument");
3174 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3175 unsigned Idx = MI.getNumOperands();
3177 // First, we check whether this instr specifies the PredicateOperand through
3178 // a pair of TargetOperandInfos with isPredicate() property.
3179 if (NumOpsRemaining >= 2 &&
3180 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3181 OpInfo[Idx].RegClass < 0 &&
3182 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3184 // If we are inside an IT block, get the IT condition bits maintained via
3185 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3188 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3190 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3191 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3198 /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
3199 /// the possible Predicate and SBitModifier, to build the remaining MCOperand
3201 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3202 uint32_t insn, unsigned short NumOpsRemaining) {
3204 assert(NumOpsRemaining > 0 && "Invalid argument");
3206 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3207 const std::string &Name = ARMInsts[Opcode].Name;
3208 unsigned Idx = MI.getNumOperands();
3210 // First, we check whether this instr specifies the PredicateOperand through
3211 // a pair of TargetOperandInfos with isPredicate() property.
3212 if (NumOpsRemaining >= 2 &&
3213 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3214 OpInfo[Idx].RegClass < 0 &&
3215 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3217 // If we are inside an IT block, get the IT condition bits maintained via
3218 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3221 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3223 if (Name.length() > 1 && Name[0] == 't') {
3224 // Thumb conditional branch instructions have their cond field embedded,
3228 if (Name == "t2Bcc")
3229 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22))));
3230 else if (Name == "tBcc")
3231 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8))));
3233 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3235 // ARM instructions get their condition field from Inst{31-28}.
3236 MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
3239 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3241 NumOpsRemaining -= 2;
3244 if (NumOpsRemaining == 0)
3247 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3248 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3249 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3253 if (NumOpsRemaining == 0)
3259 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3260 /// after BuildIt is finished.
3261 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3264 if (!SP) return Status;
3266 if (Opcode == ARM::t2IT)
3267 Status = SP->InitIT(slice(insn, 7, 0)) ? Status : false;
3268 else if (InITBlock())
3274 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3275 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3277 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3278 unsigned Idx = (unsigned)format;
3279 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3280 Disasm = FuncPtrs[Idx];
3283 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3284 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3285 /// Return NULL if it fails to create/return a proper builder. API clients
3286 /// are responsible for freeing up of the allocated memory. Cacheing can be
3287 /// performed by the API clients to improve performance.
3288 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3289 // For "Unknown format", fail by returning a NULL pointer.
3290 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1)) {
3291 DEBUG(errs() << "Unknown format\n");
3295 return new ARMBasicMCBuilder(Opcode, Format,
3296 ARMInsts[Opcode].getNumOperands());