1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassemblerCore.h"
19 #include "ARMAddressingModes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
23 //#define DEBUG(X) do { X; } while (0)
25 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
26 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
27 /// describing the operand info for each ARMInsts[i].
29 /// Together with an instruction's encoding format, we can take advantage of the
30 /// NumOperands and the OpInfo fields of the target instruction description in
31 /// the quest to build out the MCOperand list for an MCInst.
33 /// The general guideline is that with a known format, the number of dst and src
34 /// operands are well-known. The dst is built first, followed by the src
35 /// operand(s). The operands not yet used at this point are for the Implicit
36 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
37 /// defined with two components:
39 /// def pred { // Operand PredicateOperand
40 /// ValueType Type = OtherVT;
41 /// string PrintMethod = "printPredicateOperand";
42 /// string AsmOperandLowerMethod = ?;
43 /// dag MIOperandInfo = (ops i32imm, CCR);
44 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
45 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
48 /// which is manifested by the TargetOperandInfo[] of:
50 /// { 0, 0|(1<<TOI::Predicate), 0 },
51 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
53 /// So the first predicate MCOperand corresponds to the immediate part of the
54 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
55 /// corresponds to a register kind of ARM::CPSR.
57 /// For the Defs part, in the simple case of only cc_out:$s, we have:
59 /// def cc_out { // Operand OptionalDefOperand
60 /// ValueType Type = OtherVT;
61 /// string PrintMethod = "printSBitModifierOperand";
62 /// string AsmOperandLowerMethod = ?;
63 /// dag MIOperandInfo = (ops CCR);
64 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
65 /// dag DefaultOps = (ops (i32 zero_reg));
68 /// which is manifested by the one TargetOperandInfo of:
70 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
72 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
73 #include "ARMGenInstrInfo.inc"
77 const char *ARMUtils::OpcodeName(unsigned Opcode) {
78 return ARMInsts[Opcode].Name;
81 // Return the register enum Based on RegClass and the raw register number.
84 getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
85 // For this purpose, we can treat rGPR as if it were GPR.
86 if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
88 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
90 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
97 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
98 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
99 case ARM::DPR_VFP2RegClassID:
101 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
102 case ARM::QPR_VFP2RegClassID:
104 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
108 switch (RegClassID) {
109 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
110 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
111 case ARM::DPR_VFP2RegClassID:
113 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
114 case ARM::QPR_VFP2RegClassID:
116 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
120 switch (RegClassID) {
121 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
122 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
123 case ARM::DPR_VFP2RegClassID:
125 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
126 case ARM::QPR_VFP2RegClassID:
128 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
132 switch (RegClassID) {
133 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
134 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
135 case ARM::DPR_VFP2RegClassID:
137 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
138 case ARM::QPR_VFP2RegClassID:
140 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
144 switch (RegClassID) {
145 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
146 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
147 case ARM::DPR_VFP2RegClassID:
149 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
150 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
154 switch (RegClassID) {
155 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
156 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
157 case ARM::DPR_VFP2RegClassID:
159 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
160 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
164 switch (RegClassID) {
165 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
166 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
167 case ARM::DPR_VFP2RegClassID:
169 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
170 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
174 switch (RegClassID) {
175 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
176 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
177 case ARM::DPR_VFP2RegClassID:
179 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
180 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
184 switch (RegClassID) {
185 case ARM::GPRRegClassID: return ARM::R8;
186 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
187 case ARM::QPRRegClassID: return ARM::Q8;
188 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
192 switch (RegClassID) {
193 case ARM::GPRRegClassID: return ARM::R9;
194 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
195 case ARM::QPRRegClassID: return ARM::Q9;
196 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
200 switch (RegClassID) {
201 case ARM::GPRRegClassID: return ARM::R10;
202 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
203 case ARM::QPRRegClassID: return ARM::Q10;
204 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
208 switch (RegClassID) {
209 case ARM::GPRRegClassID: return ARM::R11;
210 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
211 case ARM::QPRRegClassID: return ARM::Q11;
212 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
216 switch (RegClassID) {
217 case ARM::GPRRegClassID: return ARM::R12;
218 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
219 case ARM::QPRRegClassID: return ARM::Q12;
220 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
224 switch (RegClassID) {
225 case ARM::GPRRegClassID: return ARM::SP;
226 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
227 case ARM::QPRRegClassID: return ARM::Q13;
228 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
232 switch (RegClassID) {
233 case ARM::GPRRegClassID: return ARM::LR;
234 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
235 case ARM::QPRRegClassID: return ARM::Q14;
236 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
240 switch (RegClassID) {
241 case ARM::GPRRegClassID: return ARM::PC;
242 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
243 case ARM::QPRRegClassID: return ARM::Q15;
244 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
248 switch (RegClassID) {
249 case ARM::DPRRegClassID: return ARM::D16;
250 case ARM::SPRRegClassID: return ARM::S16;
254 switch (RegClassID) {
255 case ARM::DPRRegClassID: return ARM::D17;
256 case ARM::SPRRegClassID: return ARM::S17;
260 switch (RegClassID) {
261 case ARM::DPRRegClassID: return ARM::D18;
262 case ARM::SPRRegClassID: return ARM::S18;
266 switch (RegClassID) {
267 case ARM::DPRRegClassID: return ARM::D19;
268 case ARM::SPRRegClassID: return ARM::S19;
272 switch (RegClassID) {
273 case ARM::DPRRegClassID: return ARM::D20;
274 case ARM::SPRRegClassID: return ARM::S20;
278 switch (RegClassID) {
279 case ARM::DPRRegClassID: return ARM::D21;
280 case ARM::SPRRegClassID: return ARM::S21;
284 switch (RegClassID) {
285 case ARM::DPRRegClassID: return ARM::D22;
286 case ARM::SPRRegClassID: return ARM::S22;
290 switch (RegClassID) {
291 case ARM::DPRRegClassID: return ARM::D23;
292 case ARM::SPRRegClassID: return ARM::S23;
296 switch (RegClassID) {
297 case ARM::DPRRegClassID: return ARM::D24;
298 case ARM::SPRRegClassID: return ARM::S24;
302 switch (RegClassID) {
303 case ARM::DPRRegClassID: return ARM::D25;
304 case ARM::SPRRegClassID: return ARM::S25;
308 switch (RegClassID) {
309 case ARM::DPRRegClassID: return ARM::D26;
310 case ARM::SPRRegClassID: return ARM::S26;
314 switch (RegClassID) {
315 case ARM::DPRRegClassID: return ARM::D27;
316 case ARM::SPRRegClassID: return ARM::S27;
320 switch (RegClassID) {
321 case ARM::DPRRegClassID: return ARM::D28;
322 case ARM::SPRRegClassID: return ARM::S28;
326 switch (RegClassID) {
327 case ARM::DPRRegClassID: return ARM::D29;
328 case ARM::SPRRegClassID: return ARM::S29;
332 switch (RegClassID) {
333 case ARM::DPRRegClassID: return ARM::D30;
334 case ARM::SPRRegClassID: return ARM::S30;
338 switch (RegClassID) {
339 case ARM::DPRRegClassID: return ARM::D31;
340 case ARM::SPRRegClassID: return ARM::S31;
344 DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
345 // Encoding error. Mark the builder with error code != 0.
350 ///////////////////////////////
352 // Utility Functions //
354 ///////////////////////////////
356 // Extract/Decode Rd: Inst{15-12}.
357 static inline unsigned decodeRd(uint32_t insn) {
358 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
361 // Extract/Decode Rn: Inst{19-16}.
362 static inline unsigned decodeRn(uint32_t insn) {
363 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
366 // Extract/Decode Rm: Inst{3-0}.
367 static inline unsigned decodeRm(uint32_t insn) {
368 return (insn & ARMII::GPRRegMask);
371 // Extract/Decode Rs: Inst{11-8}.
372 static inline unsigned decodeRs(uint32_t insn) {
373 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
376 static inline unsigned getCondField(uint32_t insn) {
377 return (insn >> ARMII::CondShift);
380 static inline unsigned getIBit(uint32_t insn) {
381 return (insn >> ARMII::I_BitShift) & 1;
384 static inline unsigned getAM3IBit(uint32_t insn) {
385 return (insn >> ARMII::AM3_I_BitShift) & 1;
388 static inline unsigned getPBit(uint32_t insn) {
389 return (insn >> ARMII::P_BitShift) & 1;
392 static inline unsigned getUBit(uint32_t insn) {
393 return (insn >> ARMII::U_BitShift) & 1;
396 static inline unsigned getPUBits(uint32_t insn) {
397 return (insn >> ARMII::U_BitShift) & 3;
400 static inline unsigned getSBit(uint32_t insn) {
401 return (insn >> ARMII::S_BitShift) & 1;
404 static inline unsigned getWBit(uint32_t insn) {
405 return (insn >> ARMII::W_BitShift) & 1;
408 static inline unsigned getDBit(uint32_t insn) {
409 return (insn >> ARMII::D_BitShift) & 1;
412 static inline unsigned getNBit(uint32_t insn) {
413 return (insn >> ARMII::N_BitShift) & 1;
416 static inline unsigned getMBit(uint32_t insn) {
417 return (insn >> ARMII::M_BitShift) & 1;
420 // See A8.4 Shifts applied to a register.
421 // A8.4.2 Register controlled shifts.
423 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
424 // into llvm enums for shift opcode. The API clients should pass in the value
425 // encoded with two bits, so the assert stays to signal a wrong API usage.
427 // A8-12: DecodeRegShift()
428 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
430 default: assert(0 && "No such value"); return ARM_AM::no_shift;
431 case 0: return ARM_AM::lsl;
432 case 1: return ARM_AM::lsr;
433 case 2: return ARM_AM::asr;
434 case 3: return ARM_AM::ror;
438 // See A8.4 Shifts applied to a register.
439 // A8.4.1 Constant shifts.
441 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
442 // encodings into the intended ShiftOpc and shift amount.
444 // A8-11: DecodeImmShift()
445 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
449 case ARM_AM::no_shift:
453 ShOp = ARM_AM::no_shift;
465 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
466 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
467 // clients should pass in the value encoded with two bits, so the assert stays
468 // to signal a wrong API usage.
469 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
471 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
472 case 1: return ARM_AM::ia; // P=0 U=1
473 case 3: return ARM_AM::ib; // P=1 U=1
474 case 0: return ARM_AM::da; // P=0 U=0
475 case 2: return ARM_AM::db; // P=1 U=0
479 ////////////////////////////////////////////
481 // Disassemble function definitions //
483 ////////////////////////////////////////////
485 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
486 /// instr into a list of MCOperands in the appropriate order, with possible dst,
487 /// followed by possible src(s).
489 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
490 /// the CPSR, is factored into ARMBasicMCBuilder's method named
491 /// TryPredicateAndSBitModifier.
493 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
494 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
496 assert(0 && "Unexpected pseudo instruction!");
500 // Multiply Instructions.
501 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
502 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
504 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
505 // Rd{19-16} Rn{3-0} Rm{11-8}
507 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
508 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
510 // The mapping of the multiply registers to the "regular" ARM registers, where
511 // there are convenience decoder functions, is:
517 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
518 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
520 const TargetInstrDesc &TID = ARMInsts[Opcode];
521 unsigned short NumDefs = TID.getNumDefs();
522 const TargetOperandInfo *OpInfo = TID.OpInfo;
523 unsigned &OpIdx = NumOpsAdded;
527 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
529 && OpInfo[0].RegClass == ARM::GPRRegClassID
530 && OpInfo[1].RegClass == ARM::GPRRegClassID
531 && OpInfo[2].RegClass == ARM::GPRRegClassID
532 && "Expect three register operands");
534 // Instructions with two destination registers have RdLo{15-12} first.
536 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
537 "Expect 4th register operand");
538 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
543 // The destination register: RdHi{19-16} or Rd{19-16}.
544 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
547 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
548 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
550 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
554 // Many multiply instructions (e.g., MLA) have three src registers.
555 // The third register operand is Ra{15-12}.
556 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
557 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
565 // Helper routines for disassembly of coprocessor instructions.
567 static bool LdStCopOpcode(unsigned Opcode) {
568 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
569 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
573 static bool CoprocessorOpcode(unsigned Opcode) {
574 if (LdStCopOpcode(Opcode))
580 case ARM::CDP: case ARM::CDP2:
581 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
582 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
586 static inline unsigned GetCoprocessor(uint32_t insn) {
587 return slice(insn, 11, 8);
589 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
590 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
592 static inline unsigned GetCopOpc2(uint32_t insn) {
593 return slice(insn, 7, 5);
595 static inline unsigned GetCopOpc(uint32_t insn) {
596 return slice(insn, 7, 4);
598 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
601 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
603 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
605 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
607 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
609 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
613 // LDC_OPTION: cop CRd Rn imm8
615 // STC_OPTION: cop CRd Rn imm8
618 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
619 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
621 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
623 unsigned &OpIdx = NumOpsAdded;
624 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
625 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
626 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
627 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
628 bool LdStCop = LdStCopOpcode(Opcode);
632 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
635 // Unindex if P:W = 0b00 --> _OPTION variant
636 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
638 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
640 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
644 MI.addOperand(MCOperand::CreateReg(0));
645 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
646 const TargetInstrDesc &TID = ARMInsts[Opcode];
648 (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
649 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
650 ARM_AM::no_shift, IndexMode);
651 MI.addOperand(MCOperand::CreateImm(Offset));
654 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
658 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
659 : GetCopOpc1(insn, NoGPR)));
661 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
662 : MCOperand::CreateReg(
663 getRegisterEnum(B, ARM::GPRRegClassID,
666 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
667 getRegisterEnum(B, ARM::GPRRegClassID,
669 : MCOperand::CreateImm(decodeRn(insn)));
671 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
676 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
684 // Branch Instructions.
685 // BL: SignExtend(Imm24:'00', 32)
686 // Bcc, BL_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
687 // SMC: ZeroExtend(imm4, 32)
688 // SVC: ZeroExtend(Imm24, 32)
690 // Various coprocessor instructions are assigned BrFrm arbitrarily.
691 // Delegates to DisassembleCoprocessor() helper function.
694 // MSR/MSRsys: Rm mask=Inst{19-16}
696 // MSRi/MSRsysi: so_imm
697 // SRSW/SRS: ldstm_mode:$amode mode_imm
698 // RFEW/RFE: ldstm_mode:$amode Rn
699 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
700 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
702 if (CoprocessorOpcode(Opcode))
703 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
705 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
706 if (!OpInfo) return false;
708 // MRS and MRSsys take one GPR reg Rd.
709 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
710 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
711 "Reg operand expected");
712 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
717 // BXJ takes one GPR reg Rm.
718 if (Opcode == ARM::BXJ) {
719 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
720 "Reg operand expected");
721 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
726 // MSR take a mask, followed by one GPR reg Rm. The mask contains the R Bit in
727 // bit 4, and the special register fields in bits 3-0.
728 if (Opcode == ARM::MSR) {
729 assert(NumOps >= 1 && OpInfo[1].RegClass == ARM::GPRRegClassID &&
730 "Reg operand expected");
731 MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
732 slice(insn, 19, 16) /* Special Reg */ ));
733 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
738 // MSRi take a mask, followed by one so_imm operand. The mask contains the
739 // R Bit in bit 4, and the special register fields in bits 3-0.
740 if (Opcode == ARM::MSRi) {
741 MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
742 slice(insn, 19, 16) /* Special Reg */ ));
743 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
744 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
745 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
746 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
747 unsigned Imm = insn & 0xFF;
748 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
752 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
753 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
754 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
755 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
757 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
758 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
760 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
766 assert((Opcode == ARM::Bcc || Opcode == ARM::BL || Opcode == ARM::BL_pred
767 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
768 "Unexpected Opcode");
770 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected");
773 if (Opcode == ARM::SMC) {
774 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
775 Imm32 = slice(insn, 3, 0);
776 } else if (Opcode == ARM::SVC) {
777 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
778 Imm32 = slice(insn, 23, 0);
780 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
781 unsigned Imm26 = slice(insn, 23, 0) << 2;
782 //Imm32 = signextend<signed int, 26>(Imm26);
783 Imm32 = SignExtend32<26>(Imm26);
786 MI.addOperand(MCOperand::CreateImm(Imm32));
792 // Misc. Branch Instructions.
795 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
796 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
798 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
799 if (!OpInfo) return false;
801 unsigned &OpIdx = NumOpsAdded;
805 // BX_RET and MOVPCLR have only two predicate operands; do an early return.
806 if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR)
809 // BLX and BX take one GPR reg.
810 if (Opcode == ARM::BLX || Opcode == ARM::BLX_pred ||
812 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
813 "Reg operand expected");
814 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
820 // BLXi takes imm32 (the PC offset).
821 if (Opcode == ARM::BLXi) {
822 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected");
823 // SignExtend(imm24:H:'0', 32) where imm24 = Inst{23-0} and H = Inst{24}.
824 unsigned Imm26 = slice(insn, 23, 0) << 2 | slice(insn, 24, 24) << 1;
825 int Imm32 = SignExtend32<26>(Imm26);
826 MI.addOperand(MCOperand::CreateImm(Imm32));
834 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
835 uint32_t lsb = slice(insn, 11, 7);
836 uint32_t msb = slice(insn, 20, 16);
839 DEBUG(errs() << "Encoding error: msb < lsb\n");
843 for (uint32_t i = lsb; i <= msb; ++i)
849 // A major complication is the fact that some of the saturating add/subtract
850 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
851 // They are QADD, QDADD, QDSUB, and QSUB.
852 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
853 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
855 const TargetInstrDesc &TID = ARMInsts[Opcode];
856 unsigned short NumDefs = TID.getNumDefs();
857 bool isUnary = isUnaryDP(TID.TSFlags);
858 const TargetOperandInfo *OpInfo = TID.OpInfo;
859 unsigned &OpIdx = NumOpsAdded;
863 // Disassemble register def if there is one.
864 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
865 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
870 // Now disassemble the src operands.
874 // Special-case handling of BFC/BFI/SBFX/UBFX.
875 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
876 MI.addOperand(MCOperand::CreateReg(0));
877 if (Opcode == ARM::BFI) {
878 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
883 if (!getBFCInvMask(insn, mask))
886 MI.addOperand(MCOperand::CreateImm(mask));
890 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
891 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
893 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
894 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
899 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
900 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
902 // BinaryDP has an Rn operand.
904 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
905 "Reg operand expected");
906 MI.addOperand(MCOperand::CreateReg(
907 getRegisterEnum(B, ARM::GPRRegClassID,
908 RmRn ? decodeRm(insn) : decodeRn(insn))));
912 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
913 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
914 MI.addOperand(MCOperand::CreateReg(0));
918 // Now disassemble operand 2.
922 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
923 // We have a reg/reg form.
924 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
925 // routed here as well.
926 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
927 MI.addOperand(MCOperand::CreateReg(
928 getRegisterEnum(B, ARM::GPRRegClassID,
929 RmRn? decodeRn(insn) : decodeRm(insn))));
931 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
932 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
933 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
934 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
935 MI.addOperand(MCOperand::CreateImm(Imm16));
938 // We have a reg/imm form.
939 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
940 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
941 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
942 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
943 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
944 unsigned Imm = insn & 0xFF;
945 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
952 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
953 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
955 const TargetInstrDesc &TID = ARMInsts[Opcode];
956 unsigned short NumDefs = TID.getNumDefs();
957 bool isUnary = isUnaryDP(TID.TSFlags);
958 const TargetOperandInfo *OpInfo = TID.OpInfo;
959 unsigned &OpIdx = NumOpsAdded;
963 // Disassemble register def if there is one.
964 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
965 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
970 // Disassemble the src operands.
974 // BinaryDP has an Rn operand.
976 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
977 "Reg operand expected");
978 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
983 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
984 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
985 MI.addOperand(MCOperand::CreateReg(0));
989 // Disassemble operand 2, which consists of three components.
990 if (OpIdx + 2 >= NumOps)
993 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
994 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
995 (OpInfo[OpIdx+2].RegClass < 0) &&
996 "Expect 3 reg operands");
998 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
999 unsigned Rs = slice(insn, 4, 4);
1001 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1004 // Register-controlled shifts: [Rm, Rs, shift].
1005 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1007 // Inst{6-5} encodes the shift opcode.
1008 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1009 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
1011 // Constant shifts: [Rm, reg0, shift_imm].
1012 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
1013 // Inst{6-5} encodes the shift opcode.
1014 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1015 // Inst{11-7} encodes the imm5 shift amount.
1016 unsigned ShImm = slice(insn, 11, 7);
1018 // A8.4.1. Possible rrx or shift amount of 32...
1019 getImmShiftSE(ShOp, ShImm);
1020 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1027 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1028 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1030 const TargetInstrDesc &TID = ARMInsts[Opcode];
1031 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1032 const TargetOperandInfo *OpInfo = TID.OpInfo;
1033 if (!OpInfo) return false;
1035 unsigned &OpIdx = NumOpsAdded;
1039 assert(((!isStore && TID.getNumDefs() > 0) ||
1040 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1041 && "Invalid arguments");
1043 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1044 if (isPrePost && isStore) {
1045 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1046 "Reg operand expected");
1047 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1052 // Disassemble the dst/src operand.
1053 if (OpIdx >= NumOps)
1056 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1057 "Reg operand expected");
1058 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1062 // After dst of a pre- and post-indexed load is the address base writeback.
1063 if (isPrePost && !isStore) {
1064 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1065 "Reg operand expected");
1066 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1071 // Disassemble the base operand.
1072 if (OpIdx >= NumOps)
1075 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1076 "Reg operand expected");
1077 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1078 && "Index mode or tied_to operand expected");
1079 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1083 // For reg/reg form, base reg is followed by +/- reg shop imm.
1084 // For immediate form, it is followed by +/- imm12.
1085 // See also ARMAddressingModes.h (Addressing Mode #2).
1086 if (OpIdx + 1 >= NumOps)
1089 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1090 unsigned IndexMode =
1091 (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
1092 if (getIBit(insn) == 0) {
1093 // For pre- and post-indexed case, add a reg0 operand (Addressing Mode #2).
1094 // Otherwise, skip the reg operand since for addrmode_imm12, Rn has already
1097 MI.addOperand(MCOperand::CreateReg(0));
1101 // Disassemble the 12-bit immediate offset, which is the second operand in
1102 // $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
1104 unsigned Imm12 = slice(insn, 11, 0);
1105 int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
1106 MI.addOperand(MCOperand::CreateImm(Offset));
1109 // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of
1110 // A8.6.86 LDRT. So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1,
1111 // we should reject this insn as invalid.
1114 if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1))
1117 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1118 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1120 // Inst{6-5} encodes the shift opcode.
1121 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1122 // Inst{11-7} encodes the imm5 shift amount.
1123 unsigned ShImm = slice(insn, 11, 7);
1125 // A8.4.1. Possible rrx or shift amount of 32...
1126 getImmShiftSE(ShOp, ShImm);
1127 MI.addOperand(MCOperand::CreateImm(
1128 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp, IndexMode)));
1135 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1136 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1137 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1140 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1141 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1142 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1145 static bool HasDualReg(unsigned Opcode) {
1149 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1150 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1155 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1156 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1158 const TargetInstrDesc &TID = ARMInsts[Opcode];
1159 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1160 const TargetOperandInfo *OpInfo = TID.OpInfo;
1161 if (!OpInfo) return false;
1163 unsigned &OpIdx = NumOpsAdded;
1167 assert(((!isStore && TID.getNumDefs() > 0) ||
1168 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1169 && "Invalid arguments");
1171 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1172 if (isPrePost && isStore) {
1173 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1174 "Reg operand expected");
1175 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1180 bool DualReg = HasDualReg(Opcode);
1182 // Disassemble the dst/src operand.
1183 if (OpIdx >= NumOps)
1186 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1187 "Reg operand expected");
1188 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1192 // Fill in LDRD and STRD's second operand, but only if it's offset mode OR we
1193 // have a pre-or-post-indexed store operation.
1194 if (DualReg && (!isPrePost || isStore)) {
1195 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1196 decodeRd(insn) + 1)));
1200 // After dst of a pre- and post-indexed load is the address base writeback.
1201 if (isPrePost && !isStore) {
1202 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1203 "Reg operand expected");
1204 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1209 // Disassemble the base operand.
1210 if (OpIdx >= NumOps)
1213 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1214 "Reg operand expected");
1215 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1216 && "Offset mode or tied_to operand expected");
1217 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1221 // For reg/reg form, base reg is followed by +/- reg.
1222 // For immediate form, it is followed by +/- imm8.
1223 // See also ARMAddressingModes.h (Addressing Mode #3).
1224 if (OpIdx + 1 >= NumOps)
1227 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1228 (OpInfo[OpIdx+1].RegClass < 0) &&
1229 "Expect 1 reg operand followed by 1 imm operand");
1231 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1232 if (getAM3IBit(insn) == 1) {
1233 MI.addOperand(MCOperand::CreateReg(0));
1235 // Disassemble the 8-bit immediate offset.
1236 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1237 unsigned Imm4L = insn & 0xF;
1238 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1239 MI.addOperand(MCOperand::CreateImm(Offset));
1241 // Disassemble the offset reg (Rm).
1242 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1244 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1245 MI.addOperand(MCOperand::CreateImm(Offset));
1252 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1253 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1254 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1258 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1259 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1260 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1263 // The algorithm for disassembly of LdStMulFrm is different from others because
1264 // it explicitly populates the two predicate operands after the base register.
1265 // After that, we need to populate the reglist with each affected register
1266 // encoded as an MCOperand.
1267 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1268 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1270 assert(NumOps >= 4 && "LdStMulFrm expects NumOps >= 4");
1273 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1275 // Writeback to base, if necessary.
1276 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::STMIA_UPD ||
1277 Opcode == ARM::LDMDA_UPD || Opcode == ARM::STMDA_UPD ||
1278 Opcode == ARM::LDMDB_UPD || Opcode == ARM::STMDB_UPD ||
1279 Opcode == ARM::LDMIB_UPD || Opcode == ARM::STMIB_UPD) {
1280 MI.addOperand(MCOperand::CreateReg(Base));
1284 // Add the base register operand.
1285 MI.addOperand(MCOperand::CreateReg(Base));
1287 // Handling the two predicate operands before the reglist.
1288 int64_t CondVal = insn >> ARMII::CondShift;
1289 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1290 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1294 // Fill the variadic part of reglist.
1295 unsigned RegListBits = insn & ((1 << 16) - 1);
1296 for (unsigned i = 0; i < 16; ++i) {
1297 if ((RegListBits >> i) & 1) {
1298 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1307 // LDREX, LDREXB, LDREXH: Rd Rn
1308 // LDREXD: Rd Rd+1 Rn
1309 // STREX, STREXB, STREXH: Rd Rm Rn
1310 // STREXD: Rd Rm Rm+1 Rn
1312 // SWP, SWPB: Rd Rm Rn
1313 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1314 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1316 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1317 if (!OpInfo) return false;
1319 unsigned &OpIdx = NumOpsAdded;
1324 && OpInfo[0].RegClass == ARM::GPRRegClassID
1325 && OpInfo[1].RegClass == ARM::GPRRegClassID
1326 && "Expect 2 reg operands");
1328 bool isStore = slice(insn, 20, 20) == 0;
1329 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1331 // Add the destination operand.
1332 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1336 // Store register Exclusive needs a source operand.
1338 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1343 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1344 decodeRm(insn)+1)));
1348 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1349 decodeRd(insn)+1)));
1353 // Finally add the pointer operand.
1354 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1361 // Misc. Arithmetic Instructions.
1363 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1364 // RBIT, REV, REV16, REVSH: Rd Rm
1365 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1366 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1368 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1369 unsigned &OpIdx = NumOpsAdded;
1374 && OpInfo[0].RegClass == ARM::GPRRegClassID
1375 && OpInfo[1].RegClass == ARM::GPRRegClassID
1376 && "Expect 2 reg operands");
1378 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1380 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1385 assert(NumOps >= 4 && "Expect >= 4 operands");
1386 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1391 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1395 // If there is still an operand info left which is an immediate operand, add
1396 // an additional imm5 LSL/ASR operand.
1397 if (ThreeReg && OpInfo[OpIdx].RegClass < 0
1398 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1399 // Extract the 5-bit immediate field Inst{11-7}.
1400 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1401 ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
1402 if (Opcode == ARM::PKHBT)
1404 else if (Opcode == ARM::PKHBT)
1406 getImmShiftSE(Opc, ShiftAmt);
1407 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
1414 /// DisassembleSatFrm - Disassemble saturate instructions:
1415 /// SSAT, SSAT16, USAT, and USAT16.
1416 static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1417 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1419 const TargetInstrDesc &TID = ARMInsts[Opcode];
1420 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1422 // Disassemble register def.
1423 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1426 unsigned Pos = slice(insn, 20, 16);
1427 if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16)
1429 MI.addOperand(MCOperand::CreateImm(Pos));
1431 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1434 if (NumOpsAdded == 4) {
1435 ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
1436 // Inst{11-7} encodes the imm5 shift amount.
1437 unsigned ShAmt = slice(insn, 11, 7);
1439 // A8.6.183. Possible ASR shift amount of 32...
1440 if (Opc == ARM_AM::asr)
1443 Opc = ARM_AM::no_shift;
1445 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
1450 // Extend instructions.
1451 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1452 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1453 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1454 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1455 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1457 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1458 unsigned &OpIdx = NumOpsAdded;
1463 && OpInfo[0].RegClass == ARM::GPRRegClassID
1464 && OpInfo[1].RegClass == ARM::GPRRegClassID
1465 && "Expect 2 reg operands");
1467 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1469 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1474 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1479 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1483 // If there is still an operand info left which is an immediate operand, add
1484 // an additional rotate immediate operand.
1485 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1486 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1487 // Extract the 2-bit rotate field Inst{11-10}.
1488 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1489 // Rotation by 8, 16, or 24 bits.
1490 MI.addOperand(MCOperand::CreateImm(rot << 3));
1497 /////////////////////////////////////
1499 // Utility Functions For VFP //
1501 /////////////////////////////////////
1503 // Extract/Decode Dd/Sd:
1505 // SP => d = UInt(Vd:D)
1506 // DP => d = UInt(D:Vd)
1507 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1508 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1509 : (decodeRd(insn) | getDBit(insn) << 4);
1512 // Extract/Decode Dn/Sn:
1514 // SP => n = UInt(Vn:N)
1515 // DP => n = UInt(N:Vn)
1516 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1517 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1518 : (decodeRn(insn) | getNBit(insn) << 4);
1521 // Extract/Decode Dm/Sm:
1523 // SP => m = UInt(Vm:M)
1524 // DP => m = UInt(M:Vm)
1525 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1526 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1527 : (decodeRm(insn) | getMBit(insn) << 4);
1531 static APInt VFPExpandImm(unsigned char byte, unsigned N) {
1532 assert(N == 32 || N == 64);
1535 unsigned bit6 = slice(byte, 6, 6);
1537 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1539 Result |= 0x1f << 25;
1541 Result |= 0x1 << 30;
1543 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1544 (uint64_t)slice(byte, 5, 0) << 48;
1546 Result |= 0xffULL << 54;
1548 Result |= 0x1ULL << 62;
1550 return APInt(N, Result);
1553 // VFP Unary Format Instructions:
1555 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1556 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1557 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1558 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1559 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1561 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1563 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1564 unsigned &OpIdx = NumOpsAdded;
1568 unsigned RegClass = OpInfo[OpIdx].RegClass;
1569 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1570 "Reg operand expected");
1571 bool isSP = (RegClass == ARM::SPRRegClassID);
1573 MI.addOperand(MCOperand::CreateReg(
1574 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1577 // Early return for compare with zero instructions.
1578 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1579 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1582 RegClass = OpInfo[OpIdx].RegClass;
1583 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1584 "Reg operand expected");
1585 isSP = (RegClass == ARM::SPRRegClassID);
1587 MI.addOperand(MCOperand::CreateReg(
1588 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1594 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1595 // Some of them have operand constraints which tie the first operand in the
1596 // InOperandList to that of the dst. As far as asm printing is concerned, this
1597 // tied_to operand is simply skipped.
1598 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1599 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1601 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1603 const TargetInstrDesc &TID = ARMInsts[Opcode];
1604 const TargetOperandInfo *OpInfo = TID.OpInfo;
1605 unsigned &OpIdx = NumOpsAdded;
1609 unsigned RegClass = OpInfo[OpIdx].RegClass;
1610 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1611 "Reg operand expected");
1612 bool isSP = (RegClass == ARM::SPRRegClassID);
1614 MI.addOperand(MCOperand::CreateReg(
1615 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1618 // Skip tied_to operand constraint.
1619 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1620 assert(NumOps >= 4 && "Expect >=4 operands");
1621 MI.addOperand(MCOperand::CreateReg(0));
1625 MI.addOperand(MCOperand::CreateReg(
1626 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1629 MI.addOperand(MCOperand::CreateReg(
1630 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1636 // A8.6.295 vcvt (floating-point <-> integer)
1637 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1638 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1640 // A8.6.297 vcvt (floating-point and fixed-point)
1641 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1642 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1643 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1645 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1647 const TargetInstrDesc &TID = ARMInsts[Opcode];
1648 const TargetOperandInfo *OpInfo = TID.OpInfo;
1649 if (!OpInfo) return false;
1651 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1652 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1653 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1657 assert(NumOps >= 3 && "Expect >= 3 operands");
1658 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1659 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1660 MI.addOperand(MCOperand::CreateReg(
1661 getRegisterEnum(B, RegClassID,
1662 decodeVFPRd(insn, SP))));
1664 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1665 "Tied to operand expected");
1666 MI.addOperand(MI.getOperand(0));
1668 assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() &&
1669 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1670 MI.addOperand(MCOperand::CreateImm(fbits));
1675 // The Rd (destination) and Rm (source) bits have different interpretations
1676 // depending on their single-precisonness.
1678 if (slice(insn, 18, 18) == 1) { // to_integer operation
1679 d = decodeVFPRd(insn, true /* Is Single Precision */);
1680 MI.addOperand(MCOperand::CreateReg(
1681 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1682 m = decodeVFPRm(insn, SP);
1683 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1685 d = decodeVFPRd(insn, SP);
1686 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1687 m = decodeVFPRm(insn, true /* Is Single Precision */);
1688 MI.addOperand(MCOperand::CreateReg(
1689 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1697 // VMOVRS - A8.6.330
1698 // Rt => Rd; Sn => UInt(Vn:N)
1699 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1700 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1702 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1704 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1706 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1707 decodeVFPRn(insn, true))));
1712 // VMOVRRD - A8.6.332
1713 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1715 // VMOVRRS - A8.6.331
1716 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1717 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1718 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1720 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1722 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1723 unsigned &OpIdx = NumOpsAdded;
1725 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1727 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1731 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1732 unsigned Sm = decodeVFPRm(insn, true);
1733 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1735 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1739 MI.addOperand(MCOperand::CreateReg(
1740 getRegisterEnum(B, ARM::DPRRegClassID,
1741 decodeVFPRm(insn, false))));
1747 // VMOVSR - A8.6.330
1748 // Rt => Rd; Sn => UInt(Vn:N)
1749 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1750 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1752 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1754 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1755 decodeVFPRn(insn, true))));
1756 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1762 // VMOVDRR - A8.6.332
1763 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1765 // VMOVRRS - A8.6.331
1766 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1767 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1768 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1770 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1772 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1773 unsigned &OpIdx = NumOpsAdded;
1777 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1778 unsigned Sm = decodeVFPRm(insn, true);
1779 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1781 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1785 MI.addOperand(MCOperand::CreateReg(
1786 getRegisterEnum(B, ARM::DPRRegClassID,
1787 decodeVFPRm(insn, false))));
1791 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1793 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1799 // VFP Load/Store Instructions.
1800 // VLDRD, VLDRS, VSTRD, VSTRS
1801 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1802 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1804 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1806 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS);
1807 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1809 // Extract Dd/Sd for operand 0.
1810 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1812 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1814 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1815 MI.addOperand(MCOperand::CreateReg(Base));
1817 // Next comes the AM5 Opcode.
1818 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1819 unsigned char Imm8 = insn & 0xFF;
1820 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1827 // VFP Load/Store Multiple Instructions.
1828 // We have an optional write back reg, the base, and two predicate operands.
1829 // It is then followed by a reglist of either DPR(s) or SPR(s).
1831 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1832 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1833 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1835 assert(NumOps >= 4 && "VFPLdStMulFrm expects NumOps >= 4");
1837 unsigned &OpIdx = NumOpsAdded;
1841 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1843 // Writeback to base, if necessary.
1844 if (Opcode == ARM::VLDMDIA_UPD || Opcode == ARM::VLDMSIA_UPD ||
1845 Opcode == ARM::VLDMDDB_UPD || Opcode == ARM::VLDMSDB_UPD ||
1846 Opcode == ARM::VSTMDIA_UPD || Opcode == ARM::VSTMSIA_UPD ||
1847 Opcode == ARM::VSTMDDB_UPD || Opcode == ARM::VSTMSDB_UPD) {
1848 MI.addOperand(MCOperand::CreateReg(Base));
1852 MI.addOperand(MCOperand::CreateReg(Base));
1854 // Handling the two predicate operands before the reglist.
1855 int64_t CondVal = insn >> ARMII::CondShift;
1856 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1857 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1861 bool isSPVFP = (Opcode == ARM::VLDMSIA ||
1862 Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMSDB_UPD ||
1863 Opcode == ARM::VSTMSIA ||
1864 Opcode == ARM::VSTMSIA_UPD || Opcode == ARM::VSTMSDB_UPD);
1865 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1868 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1870 // Fill the variadic part of reglist.
1871 unsigned char Imm8 = insn & 0xFF;
1872 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1874 // Apply some sanity checks before proceeding.
1875 if (Regs == 0 || (RegD + Regs) > 32 || (!isSPVFP && Regs > 16))
1878 for (unsigned i = 0; i < Regs; ++i) {
1879 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1887 // Misc. VFP Instructions.
1888 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1889 // FCONSTD (DPR and a VFPf64Imm operand)
1890 // FCONSTS (SPR and a VFPf32Imm operand)
1891 // VMRS/VMSR (GPR operand)
1892 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1893 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1895 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1896 unsigned &OpIdx = NumOpsAdded;
1900 if (Opcode == ARM::FMSTAT)
1903 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1905 unsigned RegEnum = 0;
1906 switch (OpInfo[0].RegClass) {
1907 case ARM::DPRRegClassID:
1908 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1910 case ARM::SPRRegClassID:
1911 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1913 case ARM::GPRRegClassID:
1914 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1917 assert(0 && "Invalid reg class id");
1921 MI.addOperand(MCOperand::CreateReg(RegEnum));
1924 // Extract/decode the f64/f32 immediate.
1925 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1926 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1927 // The asm syntax specifies the floating point value, not the 8-bit literal.
1928 APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1929 Opcode == ARM::FCONSTD ? 64 : 32);
1930 APFloat immFP = APFloat(immRaw, true);
1931 double imm = Opcode == ARM::FCONSTD ? immFP.convertToDouble() :
1932 immFP.convertToFloat();
1933 MI.addOperand(MCOperand::CreateFPImm(imm));
1941 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
1942 #include "ThumbDisassemblerCore.h"
1944 /////////////////////////////////////////////////////
1946 // Utility Functions For ARM Advanced SIMD //
1948 /////////////////////////////////////////////////////
1950 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
1951 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
1953 // A7.3 Register encoding
1955 // Extract/Decode NEON D/Vd:
1957 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
1958 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
1959 // handling it in the getRegisterEnum() utility function.
1960 // D = Inst{22}, Vd = Inst{15-12}
1961 static unsigned decodeNEONRd(uint32_t insn) {
1962 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
1963 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
1966 // Extract/Decode NEON N/Vn:
1968 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
1969 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
1970 // handling it in the getRegisterEnum() utility function.
1971 // N = Inst{7}, Vn = Inst{19-16}
1972 static unsigned decodeNEONRn(uint32_t insn) {
1973 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
1974 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
1977 // Extract/Decode NEON M/Vm:
1979 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
1980 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
1981 // handling it in the getRegisterEnum() utility function.
1982 // M = Inst{5}, Vm = Inst{3-0}
1983 static unsigned decodeNEONRm(uint32_t insn) {
1984 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
1985 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
1996 } // End of unnamed namespace
1998 // size field -> Inst{11-10}
1999 // index_align field -> Inst{7-4}
2001 // The Lane Index interpretation depends on the Data Size:
2002 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
2003 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
2004 // 32 (encoded as size = 0b10) -> Index = index_align[3]
2006 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
2007 static unsigned decodeLaneIndex(uint32_t insn) {
2008 unsigned size = insn >> 10 & 3;
2009 assert((size == 0 || size == 1 || size == 2) &&
2010 "Encoding error: size should be either 0, 1, or 2");
2012 unsigned index_align = insn >> 4 & 0xF;
2013 return (index_align >> 1) >> size;
2016 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
2017 // op = Inst{5}, cmode = Inst{11-8}
2018 // i = Inst{24} (ARM architecture)
2019 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
2020 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
2021 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
2022 unsigned char op = (insn >> 5) & 1;
2023 unsigned char cmode = (insn >> 8) & 0xF;
2024 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
2025 ((insn >> 16) & 7) << 4 |
2027 return (op << 12) | (cmode << 8) | Imm8;
2030 // A8.6.339 VMUL, VMULL (by scalar)
2031 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2032 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2033 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2040 assert(0 && "Unreachable code!");
2045 // A8.6.339 VMUL, VMULL (by scalar)
2046 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2047 // ESize32 => index = Inst{5} (M) D0-D15
2048 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2051 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2053 return (insn >> 5) & 1;
2055 assert(0 && "Unreachable code!");
2060 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2061 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2062 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2063 return 64 - ((insn >> 16) & 0x3F);
2066 // A8.6.302 VDUP (scalar)
2067 // ESize8 => index = Inst{19-17}
2068 // ESize16 => index = Inst{19-18}
2069 // ESize32 => index = Inst{19}
2070 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2073 return (insn >> 17) & 7;
2075 return (insn >> 18) & 3;
2077 return (insn >> 19) & 1;
2079 assert(0 && "Unspecified element size!");
2084 // A8.6.328 VMOV (ARM core register to scalar)
2085 // A8.6.329 VMOV (scalar to ARM core register)
2086 // ESize8 => index = Inst{21:6-5}
2087 // ESize16 => index = Inst{21:6}
2088 // ESize32 => index = Inst{21}
2089 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2092 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2094 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2096 return ((insn >> 21) & 1);
2098 assert(0 && "Unspecified element size!");
2103 // Imm6 = Inst{21-16}, L = Inst{7}
2105 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2107 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2108 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2109 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2110 // '1xxxxxx' => esize = 64; shift_amount = imm6
2112 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2114 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2115 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2116 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2117 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2119 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2120 ElemSize esize = ESizeNA;
2121 unsigned L = (insn >> 7) & 1;
2122 unsigned imm6 = (insn >> 16) & 0x3F;
2126 else if (imm6 >> 4 == 1)
2128 else if (imm6 >> 5 == 1)
2131 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2136 return esize == ESize64 ? imm6 : (imm6 - esize);
2138 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2142 // Imm4 = Inst{11-8}
2143 static unsigned decodeN3VImm(uint32_t insn) {
2144 return (insn >> 8) & 0xF;
2148 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2150 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2152 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2154 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2156 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2157 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2158 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2161 const TargetInstrDesc &TID = ARMInsts[Opcode];
2162 const TargetOperandInfo *OpInfo = TID.OpInfo;
2164 // At least one DPR register plus addressing mode #6.
2165 assert(NumOps >= 3 && "Expect >= 3 operands");
2167 unsigned &OpIdx = NumOpsAdded;
2171 // We have homogeneous NEON registers for Load/Store.
2172 unsigned RegClass = 0;
2174 // Double-spaced registers have increments of 2.
2175 unsigned Inc = DblSpaced ? 2 : 1;
2177 unsigned Rn = decodeRn(insn);
2178 unsigned Rm = decodeRm(insn);
2179 unsigned Rd = decodeNEONRd(insn);
2181 // A7.7.1 Advanced SIMD addressing mode.
2184 // LLVM Addressing Mode #6.
2185 unsigned RmEnum = 0;
2187 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2190 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2191 // then possible lane index.
2192 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2193 "Reg operand expected");
2196 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2201 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2202 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2203 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2205 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2209 MI.addOperand(MCOperand::CreateReg(RmEnum));
2213 assert(OpIdx < NumOps &&
2214 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2215 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2216 "Reg operand expected");
2218 RegClass = OpInfo[OpIdx].RegClass;
2219 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2220 MI.addOperand(MCOperand::CreateReg(
2221 getRegisterEnum(B, RegClass, Rd)));
2226 // Handle possible lane index.
2227 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2228 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2229 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2234 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2235 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2236 RegClass = OpInfo[0].RegClass;
2238 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2239 MI.addOperand(MCOperand::CreateReg(
2240 getRegisterEnum(B, RegClass, Rd)));
2246 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2251 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2252 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2253 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2255 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2259 MI.addOperand(MCOperand::CreateReg(RmEnum));
2263 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2264 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2265 "Tied to operand expected");
2266 MI.addOperand(MCOperand::CreateReg(0));
2270 // Handle possible lane index.
2271 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2272 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2273 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2278 // Accessing registers past the end of the NEON register file is not
2287 // If L (Inst{21}) == 0, store instructions.
2288 // Find out about double-spaced-ness of the Opcode and pass it on to
2289 // DisassembleNLdSt0().
2290 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2291 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2293 const StringRef Name = ARMInsts[Opcode].Name;
2294 bool DblSpaced = false;
2296 if (Name.find("LN") != std::string::npos) {
2297 // To one lane instructions.
2298 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2300 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2301 if (Name.endswith("16") || Name.endswith("16_UPD"))
2302 DblSpaced = slice(insn, 5, 5) == 1;
2304 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2305 if (Name.endswith("32") || Name.endswith("32_UPD"))
2306 DblSpaced = slice(insn, 6, 6) == 1;
2309 // Multiple n-element structures with type encoded as Inst{11-8}.
2310 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2312 // n == 2 && type == 0b1001 -> DblSpaced = true
2313 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2314 DblSpaced = slice(insn, 11, 8) == 9;
2316 // n == 3 && type == 0b0101 -> DblSpaced = true
2317 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2318 DblSpaced = slice(insn, 11, 8) == 5;
2320 // n == 4 && type == 0b0001 -> DblSpaced = true
2321 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2322 DblSpaced = slice(insn, 11, 8) == 1;
2325 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2326 slice(insn, 21, 21) == 0, DblSpaced, B);
2333 // Qd/Dd imm src(=Qd/Dd)
2334 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2335 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2337 const TargetInstrDesc &TID = ARMInsts[Opcode];
2338 const TargetOperandInfo *OpInfo = TID.OpInfo;
2340 assert(NumOps >= 2 &&
2341 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2342 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2343 (OpInfo[1].RegClass < 0) &&
2344 "Expect 1 reg operand followed by 1 imm operand");
2346 // Qd/Dd = Inst{22:15-12} => NEON Rd
2347 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2348 decodeNEONRd(insn))));
2350 ElemSize esize = ESizeNA;
2353 case ARM::VMOVv16i8:
2356 case ARM::VMOVv4i16:
2357 case ARM::VMOVv8i16:
2358 case ARM::VMVNv4i16:
2359 case ARM::VMVNv8i16:
2360 case ARM::VBICiv4i16:
2361 case ARM::VBICiv8i16:
2362 case ARM::VORRiv4i16:
2363 case ARM::VORRiv8i16:
2366 case ARM::VMOVv2i32:
2367 case ARM::VMOVv4i32:
2368 case ARM::VMVNv2i32:
2369 case ARM::VMVNv4i32:
2370 case ARM::VBICiv2i32:
2371 case ARM::VBICiv4i32:
2372 case ARM::VORRiv2i32:
2373 case ARM::VORRiv4i32:
2376 case ARM::VMOVv1i64:
2377 case ARM::VMOVv2i64:
2381 assert(0 && "Unexpected opcode!");
2385 // One register and a modified immediate value.
2386 // Add the imm operand.
2387 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2391 // VBIC/VORRiv*i* variants have an extra $src = $Vd to be filled in.
2393 (OpInfo[2].RegClass == ARM::DPRRegClassID ||
2394 OpInfo[2].RegClass == ARM::QPRRegClassID)) {
2395 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2396 decodeNEONRd(insn))));
2407 N2V_VectorConvert_Between_Float_Fixed
2409 } // End of unnamed namespace
2411 // Vector Convert [between floating-point and fixed-point]
2412 // Qd/Dd Qm/Dm [fbits]
2414 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2415 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2418 // Vector Move Long:
2421 // Vector Move Narrow:
2425 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2426 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2428 const TargetInstrDesc &TID = ARMInsts[Opc];
2429 const TargetOperandInfo *OpInfo = TID.OpInfo;
2431 assert(NumOps >= 2 &&
2432 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2433 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2434 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2435 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2436 "Expect >= 2 operands and first 2 as reg operands");
2438 unsigned &OpIdx = NumOpsAdded;
2442 ElemSize esize = ESizeNA;
2443 if (Flag == N2V_VectorDupLane) {
2444 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2445 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2446 "Unexpected Opcode");
2447 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2448 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2452 // Qd/Dd = Inst{22:15-12} => NEON Rd
2453 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2454 decodeNEONRd(insn))));
2458 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2460 MI.addOperand(MCOperand::CreateReg(0));
2464 // Dm = Inst{5:3-0} => NEON Rm
2465 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2466 decodeNEONRm(insn))));
2469 // VZIP and others have two TIED_TO reg operands.
2471 while (OpIdx < NumOps &&
2472 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2473 // Add TIED_TO operand.
2474 MI.addOperand(MI.getOperand(Idx));
2478 // Add the imm operand, if required.
2479 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2480 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2482 unsigned imm = 0xFFFFFFFF;
2484 if (Flag == N2V_VectorDupLane)
2485 imm = decodeNVLaneDupIndex(insn, esize);
2486 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2487 imm = decodeVCVTFractionBits(insn);
2489 assert(imm != 0xFFFFFFFF && "Internal error");
2490 MI.addOperand(MCOperand::CreateImm(imm));
2497 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2498 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2500 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2503 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2504 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2506 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2507 N2V_VectorConvert_Between_Float_Fixed, B);
2509 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2510 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2512 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2513 N2V_VectorDupLane, B);
2516 // Vector Shift [Accumulate] Instructions.
2517 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2519 // Vector Shift Left Long (with maximum shift count) Instructions.
2520 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2522 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2523 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2525 const TargetInstrDesc &TID = ARMInsts[Opcode];
2526 const TargetOperandInfo *OpInfo = TID.OpInfo;
2528 assert(NumOps >= 3 &&
2529 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2530 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2531 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2532 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2533 "Expect >= 3 operands and first 2 as reg operands");
2535 unsigned &OpIdx = NumOpsAdded;
2539 // Qd/Dd = Inst{22:15-12} => NEON Rd
2540 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2541 decodeNEONRd(insn))));
2544 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2546 MI.addOperand(MCOperand::CreateReg(0));
2550 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2551 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2552 "Reg operand expected");
2554 // Qm/Dm = Inst{5:3-0} => NEON Rm
2555 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2556 decodeNEONRm(insn))));
2559 assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
2561 // Add the imm operand.
2563 // VSHLL has maximum shift count as the imm, inferred from its size.
2567 Imm = decodeNVSAmt(insn, LeftShift);
2579 MI.addOperand(MCOperand::CreateImm(Imm));
2585 // Left shift instructions.
2586 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2587 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2589 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2592 // Right shift instructions have different shift amount interpretation.
2593 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2594 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2596 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2605 N3V_Multiply_By_Scalar
2607 } // End of unnamed namespace
2609 // NEON Three Register Instructions with Optional Immediate Operand
2611 // Vector Extract Instructions.
2612 // Qd/Dd Qn/Dn Qm/Dm imm4
2614 // Vector Shift (Register) Instructions.
2615 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2617 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2618 // Qd/Dd Qn/Dn RestrictedDm index
2621 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2622 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2624 const TargetInstrDesc &TID = ARMInsts[Opcode];
2625 const TargetOperandInfo *OpInfo = TID.OpInfo;
2627 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2628 assert(NumOps >= 3 &&
2629 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2630 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2631 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2632 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2633 "Expect >= 3 operands and first 2 as reg operands");
2635 unsigned &OpIdx = NumOpsAdded;
2639 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2640 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2641 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2642 ElemSize esize = ESizeNA;
2643 if (Flag == N3V_Multiply_By_Scalar) {
2644 unsigned size = (insn >> 20) & 3;
2645 if (size == 1) esize = ESize16;
2646 if (size == 2) esize = ESize32;
2647 assert (esize == ESize16 || esize == ESize32);
2650 // Qd/Dd = Inst{22:15-12} => NEON Rd
2651 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2652 decodeNEONRd(insn))));
2655 // VABA, VABAL, VBSLd, VBSLq, ...
2656 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2658 MI.addOperand(MCOperand::CreateReg(0));
2662 // Dn = Inst{7:19-16} => NEON Rn
2664 // Dm = Inst{5:3-0} => NEON Rm
2665 MI.addOperand(MCOperand::CreateReg(
2666 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2667 VdVnVm ? decodeNEONRn(insn)
2668 : decodeNEONRm(insn))));
2671 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2673 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2676 // Dm = Inst{5:3-0} => NEON Rm
2678 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2680 // Dn = Inst{7:19-16} => NEON Rn
2681 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2682 : decodeNEONRm(insn))
2683 : decodeNEONRn(insn);
2685 MI.addOperand(MCOperand::CreateReg(
2686 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2689 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2690 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2691 // Add the imm operand.
2694 Imm = decodeN3VImm(insn);
2695 else if (IsDmRestricted)
2696 Imm = decodeRestrictedDmIndex(insn, esize);
2698 assert(0 && "Internal error: unreachable code!");
2702 MI.addOperand(MCOperand::CreateImm(Imm));
2709 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2710 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2712 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2715 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2716 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2718 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2719 N3V_VectorShift, B);
2721 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode,
2722 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2724 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2725 N3V_VectorExtract, B);
2727 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2728 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2730 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2731 N3V_Multiply_By_Scalar, B);
2734 // Vector Table Lookup
2736 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2737 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2738 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2739 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2740 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2741 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2743 const TargetInstrDesc &TID = ARMInsts[Opcode];
2744 const TargetOperandInfo *OpInfo = TID.OpInfo;
2745 if (!OpInfo) return false;
2747 assert(NumOps >= 3 &&
2748 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2749 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2750 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2751 "Expect >= 3 operands and first 3 as reg operands");
2753 unsigned &OpIdx = NumOpsAdded;
2757 unsigned Rn = decodeNEONRn(insn);
2759 // {Dn} encoded as len = 0b00
2760 // {Dn Dn+1} encoded as len = 0b01
2761 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2762 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2763 unsigned Len = slice(insn, 9, 8) + 1;
2765 // Dd (the destination vector)
2766 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2767 decodeNEONRd(insn))));
2770 // Process tied_to operand constraint.
2772 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2773 MI.addOperand(MI.getOperand(Idx));
2777 // Do the <list> now.
2778 for (unsigned i = 0; i < Len; ++i) {
2779 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2780 "Reg operand expected");
2781 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2786 // Dm (the index vector)
2787 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2788 "Reg operand (index vector) expected");
2789 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2790 decodeNEONRm(insn))));
2796 // Vector Get Lane (move scalar to ARM core register) Instructions.
2797 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2798 static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2799 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2801 const TargetInstrDesc &TID = ARMInsts[Opcode];
2802 const TargetOperandInfo *OpInfo = TID.OpInfo;
2803 if (!OpInfo) return false;
2805 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2806 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2807 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2808 OpInfo[2].RegClass < 0 &&
2809 "Expect >= 3 operands with one dst operand");
2812 Opcode == ARM::VGETLNi32 ? ESize32
2813 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2816 // Rt = Inst{15-12} => ARM Rd
2817 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2820 // Dn = Inst{7:19-16} => NEON Rn
2821 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2822 decodeNEONRn(insn))));
2824 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2830 // Vector Set Lane (move ARM core register to scalar) Instructions.
2831 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2832 static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2833 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2835 const TargetInstrDesc &TID = ARMInsts[Opcode];
2836 const TargetOperandInfo *OpInfo = TID.OpInfo;
2837 if (!OpInfo) return false;
2839 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2840 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2841 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2842 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2843 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2844 OpInfo[3].RegClass < 0 &&
2845 "Expect >= 3 operands with one dst operand");
2848 Opcode == ARM::VSETLNi8 ? ESize8
2849 : (Opcode == ARM::VSETLNi16 ? ESize16
2852 // Dd = Inst{7:19-16} => NEON Rn
2853 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2854 decodeNEONRn(insn))));
2857 MI.addOperand(MCOperand::CreateReg(0));
2859 // Rt = Inst{15-12} => ARM Rd
2860 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2863 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2869 // Vector Duplicate Instructions (from ARM core register to all elements).
2870 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2871 static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2872 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2874 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2876 assert(NumOps >= 2 &&
2877 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2878 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2879 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2880 "Expect >= 2 operands and first 2 as reg operand");
2882 unsigned RegClass = OpInfo[0].RegClass;
2884 // Qd/Dd = Inst{7:19-16} => NEON Rn
2885 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2886 decodeNEONRn(insn))));
2888 // Rt = Inst{15-12} => ARM Rd
2889 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2899 static inline bool MemBarrierInstr(uint32_t insn) {
2900 unsigned op7_4 = slice(insn, 7, 4);
2901 if (slice(insn, 31, 8) == 0xf57ff0 && (op7_4 >= 4 && op7_4 <= 6))
2907 static inline bool PreLoadOpcode(unsigned Opcode) {
2909 case ARM::PLDi12: case ARM::PLDrs:
2910 case ARM::PLDWi12: case ARM::PLDWrs:
2911 case ARM::PLIi12: case ARM::PLIrs:
2918 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2919 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2921 // Preload Data/Instruction requires either 2 or 3 operands.
2922 // PLDi12, PLDWi12, PLIi12: addrmode_imm12
2923 // PLDrs, PLDWrs, PLIrs: ldst_so_reg
2925 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2928 if (Opcode == ARM::PLDi12 || Opcode == ARM::PLDWi12
2929 || Opcode == ARM::PLIi12) {
2930 unsigned Imm12 = slice(insn, 11, 0);
2931 bool Negative = getUBit(insn) == 0;
2933 // A8.6.118 PLD (literal) PLDWi12 with Rn=PC is transformed to PLDi12.
2934 if (Opcode == ARM::PLDWi12 && slice(insn, 19, 16) == 0xF) {
2935 DEBUG(errs() << "Rn == '1111': PLDWi12 morphed to PLDi12\n");
2936 MI.setOpcode(ARM::PLDi12);
2939 // -0 is represented specially. All other values are as normal.
2940 int Offset = Negative ? -1 * Imm12 : Imm12;
2941 if (Imm12 == 0 && Negative)
2944 MI.addOperand(MCOperand::CreateImm(Offset));
2947 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2950 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
2952 // Inst{6-5} encodes the shift opcode.
2953 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
2954 // Inst{11-7} encodes the imm5 shift amount.
2955 unsigned ShImm = slice(insn, 11, 7);
2957 // A8.4.1. Possible rrx or shift amount of 32...
2958 getImmShiftSE(ShOp, ShImm);
2959 MI.addOperand(MCOperand::CreateImm(
2960 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
2967 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2968 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2970 if (MemBarrierInstr(insn)) {
2971 // DMBsy, DSBsy, and ISBsy instructions have zero operand and are taken care
2972 // of within the generic ARMBasicMCBuilder::BuildIt() method.
2974 // Inst{3-0} encodes the memory barrier option for the variants.
2975 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
2991 // SWP, SWPB: Rd Rm Rn
2992 // Delegate to DisassembleLdStExFrm()....
2993 return DisassembleLdStExFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2998 if (Opcode == ARM::SETEND) {
3000 MI.addOperand(MCOperand::CreateImm(slice(insn, 9, 9)));
3004 // FIXME: To enable correct asm parsing and disasm of CPS we need 3 different
3005 // opcodes which match the same real instruction. This is needed since there's
3006 // no current handling of optional arguments. Fix here when a better handling
3007 // of optional arguments is implemented.
3008 if (Opcode == ARM::CPS3p) { // M = 1
3009 // Let's reject these impossible imod values by returning false:
3012 // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an
3013 // invalid combination, so we just check for imod=0b00 here.
3014 if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
3016 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
3017 MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
3018 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
3022 if (Opcode == ARM::CPS2p) { // mode = 0, M = 0
3023 // Let's reject these impossible imod values by returning false:
3024 // 1. (imod=0b00,M=0)
3026 if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
3028 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
3029 MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
3033 if (Opcode == ARM::CPS1p) { // imod = 0, iflags = 0, M = 1
3034 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
3039 // DBG has its option specified in Inst{3-0}.
3040 if (Opcode == ARM::DBG) {
3041 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3046 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
3047 if (Opcode == ARM::BKPT) {
3048 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
3049 slice(insn, 3, 0)));
3054 if (PreLoadOpcode(Opcode))
3055 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
3057 assert(0 && "Unexpected misc instruction!");
3061 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
3062 /// We divide the disassembly task into different categories, with each one
3063 /// corresponding to a specific instruction encoding format. There could be
3064 /// exceptions when handling a specific format, and that is why the Opcode is
3065 /// also present in the function prototype.
3066 static const DisassembleFP FuncPtrs[] = {
3070 &DisassembleBrMiscFrm,
3072 &DisassembleDPSoRegFrm,
3075 &DisassembleLdMiscFrm,
3076 &DisassembleStMiscFrm,
3077 &DisassembleLdStMulFrm,
3078 &DisassembleLdStExFrm,
3079 &DisassembleArithMiscFrm,
3082 &DisassembleVFPUnaryFrm,
3083 &DisassembleVFPBinaryFrm,
3084 &DisassembleVFPConv1Frm,
3085 &DisassembleVFPConv2Frm,
3086 &DisassembleVFPConv3Frm,
3087 &DisassembleVFPConv4Frm,
3088 &DisassembleVFPConv5Frm,
3089 &DisassembleVFPLdStFrm,
3090 &DisassembleVFPLdStMulFrm,
3091 &DisassembleVFPMiscFrm,
3092 &DisassembleThumbFrm,
3093 &DisassembleMiscFrm,
3094 &DisassembleNGetLnFrm,
3095 &DisassembleNSetLnFrm,
3096 &DisassembleNDupFrm,
3098 // VLD and VST (including one lane) Instructions.
3101 // A7.4.6 One register and a modified immediate value
3102 // 1-Register Instructions with imm.
3103 // LLVM only defines VMOVv instructions.
3104 &DisassembleN1RegModImmFrm,
3106 // 2-Register Instructions with no imm.
3107 &DisassembleN2RegFrm,
3109 // 2-Register Instructions with imm (vector convert float/fixed point).
3110 &DisassembleNVCVTFrm,
3112 // 2-Register Instructions with imm (vector dup lane).
3113 &DisassembleNVecDupLnFrm,
3115 // Vector Shift Left Instructions.
3116 &DisassembleN2RegVecShLFrm,
3118 // Vector Shift Righ Instructions, which has different interpretation of the
3119 // shift amount from the imm6 field.
3120 &DisassembleN2RegVecShRFrm,
3122 // 3-Register Data-Processing Instructions.
3123 &DisassembleN3RegFrm,
3125 // Vector Shift (Register) Instructions.
3126 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3127 &DisassembleN3RegVecShFrm,
3129 // Vector Extract Instructions.
3130 &DisassembleNVecExtractFrm,
3132 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3133 // By Scalar Instructions.
3134 &DisassembleNVecMulScalarFrm,
3136 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3137 // values in a table and generate a new vector.
3138 &DisassembleNVTBLFrm,
3143 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3144 /// The general idea is to set the Opcode for the MCInst, followed by adding
3145 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3146 /// to the Format-specific disassemble function for disassembly, followed by
3147 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3148 /// which follow the Dst/Src Operands.
3149 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3150 // Stage 1 sets the Opcode.
3151 MI.setOpcode(Opcode);
3152 // If the number of operands is zero, we're done!
3156 // Stage 2 calls the format-specific disassemble function to build the operand
3160 unsigned NumOpsAdded = 0;
3161 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3163 if (!OK || this->Err != 0) return false;
3164 if (NumOpsAdded >= NumOps)
3167 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3168 // FIXME: Should this be done selectively?
3169 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3172 // A8.3 Conditional execution
3173 // A8.3.1 Pseudocode details of conditional execution
3174 // Condition bits '111x' indicate the instruction is always executed.
3175 static uint32_t CondCode(uint32_t CondField) {
3176 if (CondField == 0xF)
3181 /// DoPredicateOperands - DoPredicateOperands process the predicate operands
3182 /// of some Thumb instructions which come before the reglist operands. It
3183 /// returns true if the two predicate operands have been processed.
3184 bool ARMBasicMCBuilder::DoPredicateOperands(MCInst& MI, unsigned Opcode,
3185 uint32_t /* insn */, unsigned short NumOpsRemaining) {
3187 assert(NumOpsRemaining > 0 && "Invalid argument");
3189 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3190 unsigned Idx = MI.getNumOperands();
3192 // First, we check whether this instr specifies the PredicateOperand through
3193 // a pair of TargetOperandInfos with isPredicate() property.
3194 if (NumOpsRemaining >= 2 &&
3195 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3196 OpInfo[Idx].RegClass < 0 &&
3197 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3199 // If we are inside an IT block, get the IT condition bits maintained via
3200 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3203 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3205 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3206 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3213 /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
3214 /// the possible Predicate and SBitModifier, to build the remaining MCOperand
3216 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3217 uint32_t insn, unsigned short NumOpsRemaining) {
3219 assert(NumOpsRemaining > 0 && "Invalid argument");
3221 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3222 const std::string &Name = ARMInsts[Opcode].Name;
3223 unsigned Idx = MI.getNumOperands();
3225 // First, we check whether this instr specifies the PredicateOperand through
3226 // a pair of TargetOperandInfos with isPredicate() property.
3227 if (NumOpsRemaining >= 2 &&
3228 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3229 OpInfo[Idx].RegClass < 0 &&
3230 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3232 // If we are inside an IT block, get the IT condition bits maintained via
3233 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3236 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3238 if (Name.length() > 1 && Name[0] == 't') {
3239 // Thumb conditional branch instructions have their cond field embedded,
3243 if (Name == "t2Bcc")
3244 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22))));
3245 else if (Name == "tBcc")
3246 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8))));
3248 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3250 // ARM instructions get their condition field from Inst{31-28}.
3251 MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
3254 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3256 NumOpsRemaining -= 2;
3259 if (NumOpsRemaining == 0)
3262 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3263 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3264 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3268 if (NumOpsRemaining == 0)
3274 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3275 /// after BuildIt is finished.
3276 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3279 if (!SP) return Status;
3281 if (Opcode == ARM::t2IT)
3282 Status = SP->InitIT(slice(insn, 7, 0)) ? Status : false;
3283 else if (InITBlock())
3289 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3290 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3292 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3293 unsigned Idx = (unsigned)format;
3294 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3295 Disasm = FuncPtrs[Idx];
3298 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3299 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3300 /// Return NULL if it fails to create/return a proper builder. API clients
3301 /// are responsible for freeing up of the allocated memory. Cacheing can be
3302 /// performed by the API clients to improve performance.
3303 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3304 // For "Unknown format", fail by returning a NULL pointer.
3305 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1)) {
3306 DEBUG(errs() << "Unknown format\n");
3310 return new ARMBasicMCBuilder(Opcode, Format,
3311 ARMInsts[Opcode].getNumOperands());