1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassemblerCore.h"
19 #include "ARMAddressingModes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
23 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
24 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
25 /// describing the operand info for each ARMInsts[i].
27 /// Together with an instruction's encoding format, we can take advantage of the
28 /// NumOperands and the OpInfo fields of the target instruction description in
29 /// the quest to build out the MCOperand list for an MCInst.
31 /// The general guideline is that with a known format, the number of dst and src
32 /// operands are well-known. The dst is built first, followed by the src
33 /// operand(s). The operands not yet used at this point are for the Implicit
34 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
35 /// defined with two components:
37 /// def pred { // Operand PredicateOperand
38 /// ValueType Type = OtherVT;
39 /// string PrintMethod = "printPredicateOperand";
40 /// string AsmOperandLowerMethod = ?;
41 /// dag MIOperandInfo = (ops i32imm, CCR);
42 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
43 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
46 /// which is manifested by the TargetOperandInfo[] of:
48 /// { 0, 0|(1<<TOI::Predicate), 0 },
49 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
51 /// So the first predicate MCOperand corresponds to the immediate part of the
52 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
53 /// corresponds to a register kind of ARM::CPSR.
55 /// For the Defs part, in the simple case of only cc_out:$s, we have:
57 /// def cc_out { // Operand OptionalDefOperand
58 /// ValueType Type = OtherVT;
59 /// string PrintMethod = "printSBitModifierOperand";
60 /// string AsmOperandLowerMethod = ?;
61 /// dag MIOperandInfo = (ops CCR);
62 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
63 /// dag DefaultOps = (ops (i32 zero_reg));
66 /// which is manifested by the one TargetOperandInfo of:
68 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
70 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
71 #include "ARMGenInstrInfo.inc"
75 const char *ARMUtils::OpcodeName(unsigned Opcode) {
76 return ARMInsts[Opcode].Name;
79 // Return the register enum Based on RegClass and the raw register number.
80 // For DRegPair, see comments below.
82 static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister,
83 bool DRegPair = false) {
85 if (DRegPair && RegClassID == ARM::QPRRegClassID) {
86 // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified
87 // in the ARM Architecture Manual as far as I understand it (A8.6.307).
88 // Therefore, we morph the RegClassID to be the sub register class and don't
89 // subsequently transform the RawRegister encoding when calculating RegNum.
91 // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part
92 // where this workaround is meant for.
93 RegClassID = ARM::DPRRegClassID;
96 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
98 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
104 switch (RegClassID) {
105 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
106 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
107 case ARM::DPR_VFP2RegClassID:
109 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
110 case ARM::QPR_VFP2RegClassID:
112 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
116 switch (RegClassID) {
117 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
118 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
119 case ARM::DPR_VFP2RegClassID:
121 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
122 case ARM::QPR_VFP2RegClassID:
124 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
128 switch (RegClassID) {
129 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
130 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
131 case ARM::DPR_VFP2RegClassID:
133 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
134 case ARM::QPR_VFP2RegClassID:
136 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
140 switch (RegClassID) {
141 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
142 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
143 case ARM::DPR_VFP2RegClassID:
145 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
146 case ARM::QPR_VFP2RegClassID:
148 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
152 switch (RegClassID) {
153 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
154 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
155 case ARM::DPR_VFP2RegClassID:
157 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
158 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
162 switch (RegClassID) {
163 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
164 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
165 case ARM::DPR_VFP2RegClassID:
167 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
168 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
172 switch (RegClassID) {
173 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
174 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
175 case ARM::DPR_VFP2RegClassID:
177 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
178 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
182 switch (RegClassID) {
183 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
184 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
185 case ARM::DPR_VFP2RegClassID:
187 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
188 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
192 switch (RegClassID) {
193 case ARM::GPRRegClassID: return ARM::R8;
194 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
195 case ARM::QPRRegClassID: return ARM::Q8;
196 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
200 switch (RegClassID) {
201 case ARM::GPRRegClassID: return ARM::R9;
202 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
203 case ARM::QPRRegClassID: return ARM::Q9;
204 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
208 switch (RegClassID) {
209 case ARM::GPRRegClassID: return ARM::R10;
210 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
211 case ARM::QPRRegClassID: return ARM::Q10;
212 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
216 switch (RegClassID) {
217 case ARM::GPRRegClassID: return ARM::R11;
218 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
219 case ARM::QPRRegClassID: return ARM::Q11;
220 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
224 switch (RegClassID) {
225 case ARM::GPRRegClassID: return ARM::R12;
226 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
227 case ARM::QPRRegClassID: return ARM::Q12;
228 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
232 switch (RegClassID) {
233 case ARM::GPRRegClassID: return ARM::SP;
234 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
235 case ARM::QPRRegClassID: return ARM::Q13;
236 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
240 switch (RegClassID) {
241 case ARM::GPRRegClassID: return ARM::LR;
242 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
243 case ARM::QPRRegClassID: return ARM::Q14;
244 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
248 switch (RegClassID) {
249 case ARM::GPRRegClassID: return ARM::PC;
250 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
251 case ARM::QPRRegClassID: return ARM::Q15;
252 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
256 switch (RegClassID) {
257 case ARM::DPRRegClassID: return ARM::D16;
258 case ARM::SPRRegClassID: return ARM::S16;
262 switch (RegClassID) {
263 case ARM::DPRRegClassID: return ARM::D17;
264 case ARM::SPRRegClassID: return ARM::S17;
268 switch (RegClassID) {
269 case ARM::DPRRegClassID: return ARM::D18;
270 case ARM::SPRRegClassID: return ARM::S18;
274 switch (RegClassID) {
275 case ARM::DPRRegClassID: return ARM::D19;
276 case ARM::SPRRegClassID: return ARM::S19;
280 switch (RegClassID) {
281 case ARM::DPRRegClassID: return ARM::D20;
282 case ARM::SPRRegClassID: return ARM::S20;
286 switch (RegClassID) {
287 case ARM::DPRRegClassID: return ARM::D21;
288 case ARM::SPRRegClassID: return ARM::S21;
292 switch (RegClassID) {
293 case ARM::DPRRegClassID: return ARM::D22;
294 case ARM::SPRRegClassID: return ARM::S22;
298 switch (RegClassID) {
299 case ARM::DPRRegClassID: return ARM::D23;
300 case ARM::SPRRegClassID: return ARM::S23;
304 switch (RegClassID) {
305 case ARM::DPRRegClassID: return ARM::D24;
306 case ARM::SPRRegClassID: return ARM::S24;
310 switch (RegClassID) {
311 case ARM::DPRRegClassID: return ARM::D25;
312 case ARM::SPRRegClassID: return ARM::S25;
316 switch (RegClassID) {
317 case ARM::DPRRegClassID: return ARM::D26;
318 case ARM::SPRRegClassID: return ARM::S26;
322 switch (RegClassID) {
323 case ARM::DPRRegClassID: return ARM::D27;
324 case ARM::SPRRegClassID: return ARM::S27;
328 switch (RegClassID) {
329 case ARM::DPRRegClassID: return ARM::D28;
330 case ARM::SPRRegClassID: return ARM::S28;
334 switch (RegClassID) {
335 case ARM::DPRRegClassID: return ARM::D29;
336 case ARM::SPRRegClassID: return ARM::S29;
340 switch (RegClassID) {
341 case ARM::DPRRegClassID: return ARM::D30;
342 case ARM::SPRRegClassID: return ARM::S30;
346 switch (RegClassID) {
347 case ARM::DPRRegClassID: return ARM::D31;
348 case ARM::SPRRegClassID: return ARM::S31;
352 DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
353 // Encoding error. Mark the builder with error code != 0.
358 ///////////////////////////////
360 // Utility Functions //
362 ///////////////////////////////
364 // Extract/Decode Rd: Inst{15-12}.
365 static inline unsigned decodeRd(uint32_t insn) {
366 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
369 // Extract/Decode Rn: Inst{19-16}.
370 static inline unsigned decodeRn(uint32_t insn) {
371 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
374 // Extract/Decode Rm: Inst{3-0}.
375 static inline unsigned decodeRm(uint32_t insn) {
376 return (insn & ARMII::GPRRegMask);
379 // Extract/Decode Rs: Inst{11-8}.
380 static inline unsigned decodeRs(uint32_t insn) {
381 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
384 static inline unsigned getCondField(uint32_t insn) {
385 return (insn >> ARMII::CondShift);
388 static inline unsigned getIBit(uint32_t insn) {
389 return (insn >> ARMII::I_BitShift) & 1;
392 static inline unsigned getAM3IBit(uint32_t insn) {
393 return (insn >> ARMII::AM3_I_BitShift) & 1;
396 static inline unsigned getPBit(uint32_t insn) {
397 return (insn >> ARMII::P_BitShift) & 1;
400 static inline unsigned getUBit(uint32_t insn) {
401 return (insn >> ARMII::U_BitShift) & 1;
404 static inline unsigned getPUBits(uint32_t insn) {
405 return (insn >> ARMII::U_BitShift) & 3;
408 static inline unsigned getSBit(uint32_t insn) {
409 return (insn >> ARMII::S_BitShift) & 1;
412 static inline unsigned getWBit(uint32_t insn) {
413 return (insn >> ARMII::W_BitShift) & 1;
416 static inline unsigned getDBit(uint32_t insn) {
417 return (insn >> ARMII::D_BitShift) & 1;
420 static inline unsigned getNBit(uint32_t insn) {
421 return (insn >> ARMII::N_BitShift) & 1;
424 static inline unsigned getMBit(uint32_t insn) {
425 return (insn >> ARMII::M_BitShift) & 1;
428 // See A8.4 Shifts applied to a register.
429 // A8.4.2 Register controlled shifts.
431 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
432 // into llvm enums for shift opcode. The API clients should pass in the value
433 // encoded with two bits, so the assert stays to signal a wrong API usage.
435 // A8-12: DecodeRegShift()
436 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
438 default: assert(0 && "No such value"); return ARM_AM::no_shift;
439 case 0: return ARM_AM::lsl;
440 case 1: return ARM_AM::lsr;
441 case 2: return ARM_AM::asr;
442 case 3: return ARM_AM::ror;
446 // See A8.4 Shifts applied to a register.
447 // A8.4.1 Constant shifts.
449 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
450 // encodings into the intended ShiftOpc and shift amount.
452 // A8-11: DecodeImmShift()
453 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
454 // If type == 0b11 and imm5 == 0, we have an rrx, instead.
455 if (ShOp == ARM_AM::ror && ShImm == 0)
457 // If (lsr or asr) and imm5 == 0, shift amount is 32.
458 if ((ShOp == ARM_AM::lsr || ShOp == ARM_AM::asr) && ShImm == 0)
462 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
463 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
464 // clients should pass in the value encoded with two bits, so the assert stays
465 // to signal a wrong API usage.
466 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
468 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
469 case 1: return ARM_AM::ia; // P=0 U=1
470 case 3: return ARM_AM::ib; // P=1 U=1
471 case 0: return ARM_AM::da; // P=0 U=0
472 case 2: return ARM_AM::db; // P=1 U=0
476 ////////////////////////////////////////////
478 // Disassemble function definitions //
480 ////////////////////////////////////////////
482 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
483 /// instr into a list of MCOperands in the appropriate order, with possible dst,
484 /// followed by possible src(s).
486 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
487 /// the CPSR, is factored into ARMBasicMCBuilder's method named
488 /// TryPredicateAndSBitModifier.
490 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
491 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
493 if (Opcode == ARM::Int_MemBarrierV7 || Opcode == ARM::Int_SyncBarrierV7)
496 assert(0 && "Unexpected pseudo instruction!");
500 // Multiply Instructions.
501 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
502 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
504 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
505 // Rd{19-16} Rn{3-0} Rm{11-8}
507 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
508 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
510 // The mapping of the multiply registers to the "regular" ARM registers, where
511 // there are convenience decoder functions, is:
517 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
518 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
520 const TargetInstrDesc &TID = ARMInsts[Opcode];
521 unsigned short NumDefs = TID.getNumDefs();
522 const TargetOperandInfo *OpInfo = TID.OpInfo;
523 unsigned &OpIdx = NumOpsAdded;
527 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
529 && OpInfo[0].RegClass == ARM::GPRRegClassID
530 && OpInfo[1].RegClass == ARM::GPRRegClassID
531 && OpInfo[2].RegClass == ARM::GPRRegClassID
532 && "Expect three register operands");
534 // Instructions with two destination registers have RdLo{15-12} first.
536 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
537 "Expect 4th register operand");
538 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
543 // The destination register: RdHi{19-16} or Rd{19-16}.
544 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
547 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
548 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
550 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
554 // Many multiply instructions (e.g., MLA) have three src registers.
555 // The third register operand is Ra{15-12}.
556 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
557 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
565 // Helper routines for disassembly of coprocessor instructions.
567 static bool LdStCopOpcode(unsigned Opcode) {
568 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
569 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
573 static bool CoprocessorOpcode(unsigned Opcode) {
574 if (LdStCopOpcode(Opcode))
580 case ARM::CDP: case ARM::CDP2:
581 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
582 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
586 static inline unsigned GetCoprocessor(uint32_t insn) {
587 return slice(insn, 11, 8);
589 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
590 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
592 static inline unsigned GetCopOpc2(uint32_t insn) {
593 return slice(insn, 7, 5);
595 static inline unsigned GetCopOpc(uint32_t insn) {
596 return slice(insn, 7, 4);
598 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
601 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
603 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
605 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
607 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
609 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
613 // LDC_OPTION: cop CRd Rn imm8
615 // STC_OPTION: cop CRd Rn imm8
618 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
619 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
621 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
623 unsigned &OpIdx = NumOpsAdded;
624 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
625 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
626 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
627 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
628 bool LdStCop = LdStCopOpcode(Opcode);
632 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
635 // Unindex if P:W = 0b00 --> _OPTION variant
636 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
638 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
640 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
644 MI.addOperand(MCOperand::CreateReg(0));
645 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
646 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
648 MI.addOperand(MCOperand::CreateImm(Offset));
651 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
655 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
656 : GetCopOpc1(insn, NoGPR)));
658 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
659 : MCOperand::CreateReg(
660 getRegisterEnum(B, ARM::GPRRegClassID,
663 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
664 getRegisterEnum(B, ARM::GPRRegClassID,
666 : MCOperand::CreateImm(decodeRn(insn)));
668 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
673 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
681 // Branch Instructions.
682 // BLr9: SignExtend(Imm24:'00', 32)
683 // Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
684 // SMC: ZeroExtend(imm4, 32)
685 // SVC: ZeroExtend(Imm24, 32)
687 // Various coprocessor instructions are assigned BrFrm arbitrarily.
688 // Delegates to DisassembleCoprocessor() helper function.
691 // MSR/MSRsys: Rm mask=Inst{19-16}
693 // MSRi/MSRsysi: so_imm
694 // SRSW/SRS: addrmode4:$addr mode_imm
695 // RFEW/RFE: addrmode4:$addr Rn
696 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
697 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
699 if (CoprocessorOpcode(Opcode))
700 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
702 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
703 if (!OpInfo) return false;
705 // MRS and MRSsys take one GPR reg Rd.
706 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
707 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
708 "Reg operand expected");
709 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
714 // BXJ takes one GPR reg Rm.
715 if (Opcode == ARM::BXJ) {
716 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
717 "Reg operand expected");
718 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
723 // MSR and MSRsys take one GPR reg Rm, followed by the mask.
724 if (Opcode == ARM::MSR || Opcode == ARM::MSRsys) {
725 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
726 "Reg operand expected");
727 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
729 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
733 // MSRi and MSRsysi take one so_imm operand, followed by the mask.
734 if (Opcode == ARM::MSRi || Opcode == ARM::MSRsysi) {
735 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
736 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
737 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
738 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
739 unsigned Imm = insn & 0xFF;
740 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
741 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
745 // SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the
746 // mode immediate (Inst{4-0}).
747 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
748 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
749 // ARMInstPrinter::printAddrMode4Operand() prints special mode string
750 // if the base register is SP; so don't set ARM::SP.
751 MI.addOperand(MCOperand::CreateReg(0));
752 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
753 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
755 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
756 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
758 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
764 assert((Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred
765 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
766 "Unexpected Opcode");
768 assert(NumOps >= 1 && OpInfo[0].RegClass == 0 && "Reg operand expected");
771 if (Opcode == ARM::SMC) {
772 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
773 Imm32 = slice(insn, 3, 0);
774 } else if (Opcode == ARM::SVC) {
775 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
776 Imm32 = slice(insn, 23, 0);
778 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
779 unsigned Imm26 = slice(insn, 23, 0) << 2;
780 //Imm32 = signextend<signed int, 26>(Imm26);
781 Imm32 = SignExtend32<26>(Imm26);
783 // When executing an ARM instruction, PC reads as the address of the current
784 // instruction plus 8. The assembler subtracts 8 from the difference
785 // between the branch instruction and the target address, disassembler has
786 // to add 8 to compensate.
790 MI.addOperand(MCOperand::CreateImm(Imm32));
796 // Misc. Branch Instructions.
797 // BR_JTadd, BR_JTr, BR_JTm
800 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
801 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
803 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
804 if (!OpInfo) return false;
806 unsigned &OpIdx = NumOpsAdded;
810 // BX_RET has only two predicate operands, do an early return.
811 if (Opcode == ARM::BX_RET)
814 // BLXr9 and BRIND take one GPR reg.
815 if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
816 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
817 "Reg operand expected");
818 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
824 // BR_JTadd is an ADD with Rd = PC, (Rn, Rm) as the target and index regs.
825 if (Opcode == ARM::BR_JTadd) {
826 // InOperandList with GPR:$target and GPR:$idx regs.
828 assert(NumOps == 4 && "Expect 4 operands");
829 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
831 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
834 // Fill in the two remaining imm operands to signify build completion.
835 MI.addOperand(MCOperand::CreateImm(0));
836 MI.addOperand(MCOperand::CreateImm(0));
842 // BR_JTr is a MOV with Rd = PC, and Rm as the source register.
843 if (Opcode == ARM::BR_JTr) {
844 // InOperandList with GPR::$target reg.
846 assert(NumOps == 3 && "Expect 3 operands");
847 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
850 // Fill in the two remaining imm operands to signify build completion.
851 MI.addOperand(MCOperand::CreateImm(0));
852 MI.addOperand(MCOperand::CreateImm(0));
858 // BR_JTm is an LDR with Rt = PC.
859 if (Opcode == ARM::BR_JTm) {
860 // This is the reg/reg form, with base reg followed by +/- reg shop imm.
861 // See also ARMAddressingModes.h (Addressing Mode #2).
863 assert(NumOps == 5 && getIBit(insn) == 1 && "Expect 5 operands && I-bit=1");
864 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
867 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
869 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
870 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
872 // Inst{6-5} encodes the shift opcode.
873 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
874 // Inst{11-7} encodes the imm5 shift amount.
875 unsigned ShImm = slice(insn, 11, 7);
877 // A8.4.1. Possible rrx or shift amount of 32...
878 getImmShiftSE(ShOp, ShImm);
879 MI.addOperand(MCOperand::CreateImm(
880 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
882 // Fill in the two remaining imm operands to signify build completion.
883 MI.addOperand(MCOperand::CreateImm(0));
884 MI.addOperand(MCOperand::CreateImm(0));
890 assert(0 && "Unexpected BrMiscFrm Opcode");
894 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
895 uint32_t lsb = slice(insn, 11, 7);
896 uint32_t msb = slice(insn, 20, 16);
899 DEBUG(errs() << "Encoding error: msb < lsb\n");
903 for (uint32_t i = lsb; i <= msb; ++i)
909 static inline bool SaturateOpcode(unsigned Opcode) {
911 case ARM::SSATlsl: case ARM::SSATasr: case ARM::SSAT16:
912 case ARM::USATlsl: case ARM::USATasr: case ARM::USAT16:
919 static inline unsigned decodeSaturatePos(unsigned Opcode, uint32_t insn) {
923 return slice(insn, 20, 16) + 1;
925 return slice(insn, 19, 16) + 1;
928 return slice(insn, 20, 16);
930 return slice(insn, 19, 16);
932 assert(0 && "Invalid opcode passed in");
937 // A major complication is the fact that some of the saturating add/subtract
938 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
939 // They are QADD, QDADD, QDSUB, and QSUB.
940 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
941 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
943 const TargetInstrDesc &TID = ARMInsts[Opcode];
944 unsigned short NumDefs = TID.getNumDefs();
945 bool isUnary = isUnaryDP(TID.TSFlags);
946 const TargetOperandInfo *OpInfo = TID.OpInfo;
947 unsigned &OpIdx = NumOpsAdded;
951 // Disassemble register def if there is one.
952 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
953 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
958 // Now disassemble the src operands.
962 // SSAT/SSAT16/USAT/USAT16 has imm operand after Rd.
963 if (SaturateOpcode(Opcode)) {
964 MI.addOperand(MCOperand::CreateImm(decodeSaturatePos(Opcode, insn)));
966 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
969 if (Opcode == ARM::SSAT16 || Opcode == ARM::USAT16) {
974 // For SSAT operand reg (Rm) has been disassembled above.
975 // Now disassemble the shift amount.
977 // Inst{11-7} encodes the imm5 shift amount.
978 unsigned ShAmt = slice(insn, 11, 7);
980 // A8.6.183. Possible ASR shift amount of 32...
981 if (Opcode == ARM::SSATasr && ShAmt == 0)
984 MI.addOperand(MCOperand::CreateImm(ShAmt));
990 // Special-case handling of BFC/BFI/SBFX/UBFX.
991 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
992 // TIED_TO operand skipped for BFC and Inst{3-0} (Reg) for BFI.
993 MI.addOperand(MCOperand::CreateReg(Opcode == ARM::BFC ? 0
994 : getRegisterEnum(B, ARM::GPRRegClassID,
997 if (!getBFCInvMask(insn, mask))
1000 MI.addOperand(MCOperand::CreateImm(mask));
1004 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
1005 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1007 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
1008 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
1013 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
1014 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
1016 // BinaryDP has an Rn operand.
1018 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1019 "Reg operand expected");
1020 MI.addOperand(MCOperand::CreateReg(
1021 getRegisterEnum(B, ARM::GPRRegClassID,
1022 RmRn ? decodeRm(insn) : decodeRn(insn))));
1026 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
1027 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1028 MI.addOperand(MCOperand::CreateReg(0));
1032 // Now disassemble operand 2.
1033 if (OpIdx >= NumOps)
1036 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
1037 // We have a reg/reg form.
1038 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
1039 // routed here as well.
1040 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
1041 MI.addOperand(MCOperand::CreateReg(
1042 getRegisterEnum(B, ARM::GPRRegClassID,
1043 RmRn? decodeRn(insn) : decodeRm(insn))));
1045 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
1046 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
1047 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1048 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
1049 MI.addOperand(MCOperand::CreateImm(Imm16));
1052 // We have a reg/imm form.
1053 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
1054 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
1055 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
1056 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1057 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
1058 unsigned Imm = insn & 0xFF;
1059 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
1066 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1067 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1069 const TargetInstrDesc &TID = ARMInsts[Opcode];
1070 unsigned short NumDefs = TID.getNumDefs();
1071 bool isUnary = isUnaryDP(TID.TSFlags);
1072 const TargetOperandInfo *OpInfo = TID.OpInfo;
1073 unsigned &OpIdx = NumOpsAdded;
1077 // Disassemble register def if there is one.
1078 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
1079 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1084 // Disassemble the src operands.
1085 if (OpIdx >= NumOps)
1088 // BinaryDP has an Rn operand.
1090 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1091 "Reg operand expected");
1092 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1097 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
1098 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1099 MI.addOperand(MCOperand::CreateReg(0));
1103 // Disassemble operand 2, which consists of three components.
1104 if (OpIdx + 2 >= NumOps)
1107 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1108 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
1109 (OpInfo[OpIdx+2].RegClass == 0) &&
1110 "Expect 3 reg operands");
1112 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
1113 unsigned Rs = slice(insn, 4, 4);
1115 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1118 // Register-controlled shifts: [Rm, Rs, shift].
1119 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1121 // Inst{6-5} encodes the shift opcode.
1122 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1123 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
1125 // Constant shifts: [Rm, reg0, shift_imm].
1126 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
1127 // Inst{6-5} encodes the shift opcode.
1128 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1129 // Inst{11-7} encodes the imm5 shift amount.
1130 unsigned ShImm = slice(insn, 11, 7);
1132 // A8.4.1. Possible rrx or shift amount of 32...
1133 getImmShiftSE(ShOp, ShImm);
1134 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1141 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1142 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1144 const TargetInstrDesc &TID = ARMInsts[Opcode];
1145 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1146 const TargetOperandInfo *OpInfo = TID.OpInfo;
1147 if (!OpInfo) return false;
1149 unsigned &OpIdx = NumOpsAdded;
1153 assert(((!isStore && TID.getNumDefs() > 0) ||
1154 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1155 && "Invalid arguments");
1157 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1158 if (isPrePost && isStore) {
1159 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1160 "Reg operand expected");
1161 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1166 // Disassemble the dst/src operand.
1167 if (OpIdx >= NumOps)
1170 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1171 "Reg operand expected");
1172 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1176 // After dst of a pre- and post-indexed load is the address base writeback.
1177 if (isPrePost && !isStore) {
1178 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1179 "Reg operand expected");
1180 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1185 // Disassemble the base operand.
1186 if (OpIdx >= NumOps)
1189 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1190 "Reg operand expected");
1191 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1192 && "Index mode or tied_to operand expected");
1193 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1197 // For reg/reg form, base reg is followed by +/- reg shop imm.
1198 // For immediate form, it is followed by +/- imm12.
1199 // See also ARMAddressingModes.h (Addressing Mode #2).
1200 if (OpIdx + 1 >= NumOps)
1203 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1204 (OpInfo[OpIdx+1].RegClass == 0) &&
1205 "Expect 1 reg operand followed by 1 imm operand");
1207 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1208 if (getIBit(insn) == 0) {
1209 MI.addOperand(MCOperand::CreateReg(0));
1211 // Disassemble the 12-bit immediate offset.
1212 unsigned Imm12 = slice(insn, 11, 0);
1213 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
1214 MI.addOperand(MCOperand::CreateImm(Offset));
1216 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1217 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1219 // Inst{6-5} encodes the shift opcode.
1220 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1221 // Inst{11-7} encodes the imm5 shift amount.
1222 unsigned ShImm = slice(insn, 11, 7);
1224 // A8.4.1. Possible rrx or shift amount of 32...
1225 getImmShiftSE(ShOp, ShImm);
1226 MI.addOperand(MCOperand::CreateImm(
1227 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
1234 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1235 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1236 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1239 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1240 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1241 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1244 static bool HasDualReg(unsigned Opcode) {
1248 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1249 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1254 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1255 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1257 const TargetInstrDesc &TID = ARMInsts[Opcode];
1258 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1259 const TargetOperandInfo *OpInfo = TID.OpInfo;
1260 if (!OpInfo) return false;
1262 unsigned &OpIdx = NumOpsAdded;
1266 assert(((!isStore && TID.getNumDefs() > 0) ||
1267 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1268 && "Invalid arguments");
1270 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1271 if (isPrePost && isStore) {
1272 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1273 "Reg operand expected");
1274 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1279 bool DualReg = HasDualReg(Opcode);
1281 // Disassemble the dst/src operand.
1282 if (OpIdx >= NumOps)
1285 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1286 "Reg operand expected");
1287 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1291 // Fill in LDRD and STRD's second operand.
1293 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1294 decodeRd(insn) + 1)));
1298 // After dst of a pre- and post-indexed load is the address base writeback.
1299 if (isPrePost && !isStore) {
1300 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1301 "Reg operand expected");
1302 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1307 // Disassemble the base operand.
1308 if (OpIdx >= NumOps)
1311 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1312 "Reg operand expected");
1313 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1314 && "Index mode or tied_to operand expected");
1315 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1319 // For reg/reg form, base reg is followed by +/- reg.
1320 // For immediate form, it is followed by +/- imm8.
1321 // See also ARMAddressingModes.h (Addressing Mode #3).
1322 if (OpIdx + 1 >= NumOps)
1325 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1326 (OpInfo[OpIdx+1].RegClass == 0) &&
1327 "Expect 1 reg operand followed by 1 imm operand");
1329 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1330 if (getAM3IBit(insn) == 1) {
1331 MI.addOperand(MCOperand::CreateReg(0));
1333 // Disassemble the 8-bit immediate offset.
1334 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1335 unsigned Imm4L = insn & 0xF;
1336 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1337 MI.addOperand(MCOperand::CreateImm(Offset));
1339 // Disassemble the offset reg (Rm).
1340 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1342 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1343 MI.addOperand(MCOperand::CreateImm(Offset));
1350 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1351 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1352 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1356 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1357 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1358 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1361 // The algorithm for disassembly of LdStMulFrm is different from others because
1362 // it explicitly populates the two predicate operands after operand 0 (the base)
1363 // and operand 1 (the AM4 mode imm). After operand 3, we need to populate the
1364 // reglist with each affected register encoded as an MCOperand.
1365 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1366 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1368 assert(NumOps >= 5 && "LdStMulFrm expects NumOps >= 5");
1370 unsigned &OpIdx = NumOpsAdded;
1374 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1376 // Writeback to base, if necessary.
1377 if (Opcode == ARM::LDM_UPD || Opcode == ARM::STM_UPD) {
1378 MI.addOperand(MCOperand::CreateReg(Base));
1382 MI.addOperand(MCOperand::CreateReg(Base));
1384 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1385 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
1387 // Handling the two predicate operands before the reglist.
1388 int64_t CondVal = insn >> ARMII::CondShift;
1389 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1390 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1394 // Fill the variadic part of reglist.
1395 unsigned RegListBits = insn & ((1 << 16) - 1);
1396 for (unsigned i = 0; i < 16; ++i) {
1397 if ((RegListBits >> i) & 1) {
1398 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1407 // LDREX, LDREXB, LDREXH: Rd Rn
1408 // LDREXD: Rd Rd+1 Rn
1409 // STREX, STREXB, STREXH: Rd Rm Rn
1410 // STREXD: Rd Rm Rm+1 Rn
1412 // SWP, SWPB: Rd Rm Rn
1413 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1414 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1416 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1417 if (!OpInfo) return false;
1419 unsigned &OpIdx = NumOpsAdded;
1424 && OpInfo[0].RegClass == ARM::GPRRegClassID
1425 && OpInfo[1].RegClass == ARM::GPRRegClassID
1426 && "Expect 2 reg operands");
1428 bool isStore = slice(insn, 20, 20) == 0;
1429 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1431 // Add the destination operand.
1432 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1436 // Store register Exclusive needs a source operand.
1438 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1443 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1444 decodeRm(insn)+1)));
1448 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1449 decodeRd(insn)+1)));
1453 // Finally add the pointer operand.
1454 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1461 // Misc. Arithmetic Instructions.
1463 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1464 // RBIT, REV, REV16, REVSH: Rd Rm
1465 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1466 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1468 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1469 unsigned &OpIdx = NumOpsAdded;
1474 && OpInfo[0].RegClass == ARM::GPRRegClassID
1475 && OpInfo[1].RegClass == ARM::GPRRegClassID
1476 && "Expect 2 reg operands");
1478 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1480 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1485 assert(NumOps >= 4 && "Expect >= 4 operands");
1486 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1491 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1495 // If there is still an operand info left which is an immediate operand, add
1496 // an additional imm5 LSL/ASR operand.
1497 if (ThreeReg && OpInfo[OpIdx].RegClass == 0
1498 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1499 // Extract the 5-bit immediate field Inst{11-7}.
1500 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1501 MI.addOperand(MCOperand::CreateImm(ShiftAmt));
1508 // Extend instructions.
1509 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1510 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1511 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1512 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1513 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1515 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1516 unsigned &OpIdx = NumOpsAdded;
1521 && OpInfo[0].RegClass == ARM::GPRRegClassID
1522 && OpInfo[1].RegClass == ARM::GPRRegClassID
1523 && "Expect 2 reg operands");
1525 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1527 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1532 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1537 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1541 // If there is still an operand info left which is an immediate operand, add
1542 // an additional rotate immediate operand.
1543 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
1544 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1545 // Extract the 2-bit rotate field Inst{11-10}.
1546 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1547 // Rotation by 8, 16, or 24 bits.
1548 MI.addOperand(MCOperand::CreateImm(rot << 3));
1555 /////////////////////////////////////
1557 // Utility Functions For VFP //
1559 /////////////////////////////////////
1561 // Extract/Decode Dd/Sd:
1563 // SP => d = UInt(Vd:D)
1564 // DP => d = UInt(D:Vd)
1565 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1566 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1567 : (decodeRd(insn) | getDBit(insn) << 4);
1570 // Extract/Decode Dn/Sn:
1572 // SP => n = UInt(Vn:N)
1573 // DP => n = UInt(N:Vn)
1574 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1575 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1576 : (decodeRn(insn) | getNBit(insn) << 4);
1579 // Extract/Decode Dm/Sm:
1581 // SP => m = UInt(Vm:M)
1582 // DP => m = UInt(M:Vm)
1583 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1584 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1585 : (decodeRm(insn) | getMBit(insn) << 4);
1590 static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
1591 assert(N == 32 || N == 64);
1594 unsigned bit6 = slice(byte, 6, 6);
1596 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1598 Result |= 0x1f << 25;
1600 Result |= 0x1 << 30;
1602 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1603 (uint64_t)slice(byte, 5, 0) << 48;
1605 Result |= 0xffL << 54;
1607 Result |= 0x1L << 62;
1613 // VFP Unary Format Instructions:
1615 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1616 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1617 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1618 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1619 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1621 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1623 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1624 unsigned &OpIdx = NumOpsAdded;
1628 unsigned RegClass = OpInfo[OpIdx].RegClass;
1629 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1630 "Reg operand expected");
1631 bool isSP = (RegClass == ARM::SPRRegClassID);
1633 MI.addOperand(MCOperand::CreateReg(
1634 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1637 // Early return for compare with zero instructions.
1638 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1639 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1642 RegClass = OpInfo[OpIdx].RegClass;
1643 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1644 "Reg operand expected");
1645 isSP = (RegClass == ARM::SPRRegClassID);
1647 MI.addOperand(MCOperand::CreateReg(
1648 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1654 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1655 // Some of them have operand constraints which tie the first operand in the
1656 // InOperandList to that of the dst. As far as asm printing is concerned, this
1657 // tied_to operand is simply skipped.
1658 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1659 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1661 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1663 const TargetInstrDesc &TID = ARMInsts[Opcode];
1664 const TargetOperandInfo *OpInfo = TID.OpInfo;
1665 unsigned &OpIdx = NumOpsAdded;
1669 unsigned RegClass = OpInfo[OpIdx].RegClass;
1670 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1671 "Reg operand expected");
1672 bool isSP = (RegClass == ARM::SPRRegClassID);
1674 MI.addOperand(MCOperand::CreateReg(
1675 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1678 // Skip tied_to operand constraint.
1679 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1680 assert(NumOps >= 4 && "Expect >=4 operands");
1681 MI.addOperand(MCOperand::CreateReg(0));
1685 MI.addOperand(MCOperand::CreateReg(
1686 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1689 MI.addOperand(MCOperand::CreateReg(
1690 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1696 // A8.6.295 vcvt (floating-point <-> integer)
1697 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1698 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1700 // A8.6.297 vcvt (floating-point and fixed-point)
1701 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1702 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1703 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1705 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1707 const TargetInstrDesc &TID = ARMInsts[Opcode];
1708 const TargetOperandInfo *OpInfo = TID.OpInfo;
1709 if (!OpInfo) return false;
1711 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1712 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1713 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1717 assert(NumOps >= 3 && "Expect >= 3 operands");
1718 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1719 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1720 MI.addOperand(MCOperand::CreateReg(
1721 getRegisterEnum(B, RegClassID,
1722 decodeVFPRd(insn, SP))));
1724 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1725 "Tied to operand expected");
1726 MI.addOperand(MI.getOperand(0));
1728 assert(OpInfo[2].RegClass == 0 && !OpInfo[2].isPredicate() &&
1729 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1730 MI.addOperand(MCOperand::CreateImm(fbits));
1735 // The Rd (destination) and Rm (source) bits have different interpretations
1736 // depending on their single-precisonness.
1738 if (slice(insn, 18, 18) == 1) { // to_integer operation
1739 d = decodeVFPRd(insn, true /* Is Single Precision */);
1740 MI.addOperand(MCOperand::CreateReg(
1741 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1742 m = decodeVFPRm(insn, SP);
1743 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1745 d = decodeVFPRd(insn, SP);
1746 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1747 m = decodeVFPRm(insn, true /* Is Single Precision */);
1748 MI.addOperand(MCOperand::CreateReg(
1749 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1757 // VMOVRS - A8.6.330
1758 // Rt => Rd; Sn => UInt(Vn:N)
1759 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1760 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1762 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1764 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1766 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1767 decodeVFPRn(insn, true))));
1772 // VMOVRRD - A8.6.332
1773 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1775 // VMOVRRS - A8.6.331
1776 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1777 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1778 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1780 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1782 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1783 unsigned &OpIdx = NumOpsAdded;
1785 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1787 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1791 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1792 unsigned Sm = decodeVFPRm(insn, true);
1793 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1795 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1799 MI.addOperand(MCOperand::CreateReg(
1800 getRegisterEnum(B, ARM::DPRRegClassID,
1801 decodeVFPRm(insn, false))));
1807 // VMOVSR - A8.6.330
1808 // Rt => Rd; Sn => UInt(Vn:N)
1809 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1810 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1812 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1814 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1815 decodeVFPRn(insn, true))));
1816 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1822 // VMOVDRR - A8.6.332
1823 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1825 // VMOVRRS - A8.6.331
1826 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1827 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1828 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1830 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1832 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1833 unsigned &OpIdx = NumOpsAdded;
1837 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1838 unsigned Sm = decodeVFPRm(insn, true);
1839 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1841 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1845 MI.addOperand(MCOperand::CreateReg(
1846 getRegisterEnum(B, ARM::DPRRegClassID,
1847 decodeVFPRm(insn, false))));
1851 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1853 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1859 // VFP Load/Store Instructions.
1860 // VLDRD, VLDRS, VSTRD, VSTRS
1861 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1862 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1864 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1866 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS) ? true : false;
1867 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1869 // Extract Dd/Sd for operand 0.
1870 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1872 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1874 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1875 MI.addOperand(MCOperand::CreateReg(Base));
1877 // Next comes the AM5 Opcode.
1878 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1879 unsigned char Imm8 = insn & 0xFF;
1880 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1887 // VFP Load/Store Multiple Instructions.
1888 // This is similar to the algorithm for LDM/STM in that operand 0 (the base) and
1889 // operand 1 (the AM5 mode imm) is followed by two predicate operands. It is
1890 // followed by a reglist of either DPR(s) or SPR(s).
1892 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1893 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1894 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1896 assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
1898 unsigned &OpIdx = NumOpsAdded;
1902 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1904 // Writeback to base, if necessary.
1905 if (Opcode == ARM::VLDMD_UPD || Opcode == ARM::VLDMS_UPD ||
1906 Opcode == ARM::VSTMD_UPD || Opcode == ARM::VSTMS_UPD) {
1907 MI.addOperand(MCOperand::CreateReg(Base));
1911 MI.addOperand(MCOperand::CreateReg(Base));
1913 // Next comes the AM5 Opcode.
1914 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1915 // Must be either "ia" or "db" submode.
1916 if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) {
1917 DEBUG(errs() << "Illegal addressing mode 5 sub-mode!\n");
1921 unsigned char Imm8 = insn & 0xFF;
1922 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(SubMode, Imm8)));
1924 // Handling the two predicate operands before the reglist.
1925 int64_t CondVal = insn >> ARMII::CondShift;
1926 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1927 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1931 bool isSPVFP = (Opcode == ARM::VLDMS || Opcode == ARM::VLDMS_UPD ||
1932 Opcode == ARM::VSTMS || Opcode == ARM::VSTMS_UPD) ? true : false;
1933 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1936 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1938 // Fill the variadic part of reglist.
1939 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1940 for (unsigned i = 0; i < Regs; ++i) {
1941 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1949 // Misc. VFP Instructions.
1950 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1951 // FCONSTD (DPR and a VFPf64Imm operand)
1952 // FCONSTS (SPR and a VFPf32Imm operand)
1953 // VMRS/VMSR (GPR operand)
1954 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1955 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1957 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1958 unsigned &OpIdx = NumOpsAdded;
1962 if (Opcode == ARM::FMSTAT)
1965 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1967 unsigned RegEnum = 0;
1968 switch (OpInfo[0].RegClass) {
1969 case ARM::DPRRegClassID:
1970 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1972 case ARM::SPRRegClassID:
1973 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1975 case ARM::GPRRegClassID:
1976 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1979 assert(0 && "Invalid reg class id");
1983 MI.addOperand(MCOperand::CreateReg(RegEnum));
1986 // Extract/decode the f64/f32 immediate.
1987 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
1988 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1989 // The asm syntax specifies the before-expanded <imm>.
1990 // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1991 // Opcode == ARM::FCONSTD ? 64 : 32)
1992 MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0)));
1999 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
2000 #include "ThumbDisassemblerCore.h"
2002 /////////////////////////////////////////////////////
2004 // Utility Functions For ARM Advanced SIMD //
2006 /////////////////////////////////////////////////////
2008 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
2009 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
2011 // A7.3 Register encoding
2013 // Extract/Decode NEON D/Vd:
2015 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
2016 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
2017 // handling it in the getRegisterEnum() utility function.
2018 // D = Inst{22}, Vd = Inst{15-12}
2019 static unsigned decodeNEONRd(uint32_t insn) {
2020 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
2021 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
2024 // Extract/Decode NEON N/Vn:
2026 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
2027 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
2028 // handling it in the getRegisterEnum() utility function.
2029 // N = Inst{7}, Vn = Inst{19-16}
2030 static unsigned decodeNEONRn(uint32_t insn) {
2031 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
2032 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
2035 // Extract/Decode NEON M/Vm:
2037 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
2038 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
2039 // handling it in the getRegisterEnum() utility function.
2040 // M = Inst{5}, Vm = Inst{3-0}
2041 static unsigned decodeNEONRm(uint32_t insn) {
2042 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
2043 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
2054 } // End of unnamed namespace
2056 // size field -> Inst{11-10}
2057 // index_align field -> Inst{7-4}
2059 // The Lane Index interpretation depends on the Data Size:
2060 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
2061 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
2062 // 32 (encoded as size = 0b10) -> Index = index_align[3]
2064 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
2065 static unsigned decodeLaneIndex(uint32_t insn) {
2066 unsigned size = insn >> 10 & 3;
2067 assert((size == 0 || size == 1 || size == 2) &&
2068 "Encoding error: size should be either 0, 1, or 2");
2070 unsigned index_align = insn >> 4 & 0xF;
2071 return (index_align >> 1) >> size;
2074 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
2075 // op = Inst{5}, cmode = Inst{11-8}
2076 // i = Inst{24} (ARM architecture)
2077 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
2078 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
2079 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
2080 unsigned char cmode = (insn >> 8) & 0xF;
2081 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
2082 ((insn >> 16) & 7) << 4 |
2091 Imm64 = Imm8 << 8*(cmode >> 1 & 1);
2095 Imm64 = (Imm8 << 8) | 0xFF;
2096 else if (cmode == 13)
2097 Imm64 = (Imm8 << 16) | 0xFFFF;
2099 // Imm8 to be shifted left by how many bytes...
2100 Imm64 = Imm8 << 8*(cmode >> 1 & 3);
2105 for (unsigned i = 0; i < 8; ++i)
2106 if ((Imm8 >> i) & 1)
2107 Imm64 |= 0xFF << 8*i;
2111 assert(0 && "Unreachable code!");
2118 // A8.6.339 VMUL, VMULL (by scalar)
2119 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2120 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2121 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2128 assert(0 && "Unreachable code!");
2133 // A8.6.339 VMUL, VMULL (by scalar)
2134 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2135 // ESize32 => index = Inst{5} (M) D0-D15
2136 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2139 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2141 return (insn >> 5) & 1;
2143 assert(0 && "Unreachable code!");
2148 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2149 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2150 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2151 return 64 - ((insn >> 16) & 0x3F);
2154 // A8.6.302 VDUP (scalar)
2155 // ESize8 => index = Inst{19-17}
2156 // ESize16 => index = Inst{19-18}
2157 // ESize32 => index = Inst{19}
2158 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2161 return (insn >> 17) & 7;
2163 return (insn >> 18) & 3;
2165 return (insn >> 19) & 1;
2167 assert(0 && "Unspecified element size!");
2172 // A8.6.328 VMOV (ARM core register to scalar)
2173 // A8.6.329 VMOV (scalar to ARM core register)
2174 // ESize8 => index = Inst{21:6-5}
2175 // ESize16 => index = Inst{21:6}
2176 // ESize32 => index = Inst{21}
2177 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2180 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2182 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2184 return ((insn >> 21) & 1);
2186 assert(0 && "Unspecified element size!");
2191 // Imm6 = Inst{21-16}, L = Inst{7}
2193 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2195 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2196 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2197 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2198 // '1xxxxxx' => esize = 64; shift_amount = imm6
2200 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2202 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2203 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2204 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2205 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2207 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2208 ElemSize esize = ESizeNA;
2209 unsigned L = (insn >> 7) & 1;
2210 unsigned imm6 = (insn >> 16) & 0x3F;
2214 else if (imm6 >> 4 == 1)
2216 else if (imm6 >> 5 == 1)
2219 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2224 return esize == ESize64 ? imm6 : (imm6 - esize);
2226 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2230 // Imm4 = Inst{11-8}
2231 static unsigned decodeN3VImm(uint32_t insn) {
2232 return (insn >> 8) & 0xF;
2236 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2238 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2240 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2242 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2244 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2245 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2246 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2249 const TargetInstrDesc &TID = ARMInsts[Opcode];
2250 const TargetOperandInfo *OpInfo = TID.OpInfo;
2252 // At least one DPR register plus addressing mode #6.
2253 assert(NumOps >= 3 && "Expect >= 3 operands");
2255 unsigned &OpIdx = NumOpsAdded;
2259 // We have homogeneous NEON registers for Load/Store.
2260 unsigned RegClass = 0;
2262 // Double-spaced registers have increments of 2.
2263 unsigned Inc = DblSpaced ? 2 : 1;
2265 unsigned Rn = decodeRn(insn);
2266 unsigned Rm = decodeRm(insn);
2267 unsigned Rd = decodeNEONRd(insn);
2269 // A7.7.1 Advanced SIMD addressing mode.
2272 // LLVM Addressing Mode #6.
2273 unsigned RmEnum = 0;
2275 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2278 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2279 // then possible lane index.
2280 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2281 "Reg operand expected");
2284 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2289 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2290 OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected");
2291 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2293 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2297 MI.addOperand(MCOperand::CreateReg(RmEnum));
2301 assert(OpIdx < NumOps &&
2302 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2303 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2304 "Reg operand expected");
2306 RegClass = OpInfo[OpIdx].RegClass;
2307 while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
2308 if (Opcode >= ARM::VST1q16 && Opcode <= ARM::VST1q8)
2309 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
2312 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,Rd)));
2317 // Handle possible lane index.
2318 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2319 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2320 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2325 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2326 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2327 RegClass = OpInfo[0].RegClass;
2329 while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
2330 if (Opcode >= ARM::VLD1q16 && Opcode <= ARM::VLD1q8)
2331 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
2334 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd)));
2340 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2345 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2346 OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected");
2347 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2349 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2353 MI.addOperand(MCOperand::CreateReg(RmEnum));
2357 while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
2358 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2359 "Tied to operand expected");
2360 MI.addOperand(MCOperand::CreateReg(0));
2364 // Handle possible lane index.
2365 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2366 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2367 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2376 // If L (Inst{21}) == 0, store instructions.
2377 // Find out about double-spaced-ness of the Opcode and pass it on to
2378 // DisassembleNLdSt0().
2379 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2380 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2382 const StringRef Name = ARMInsts[Opcode].Name;
2383 bool DblSpaced = false;
2385 if (Name.find("LN") != std::string::npos) {
2386 // To one lane instructions.
2387 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2389 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2390 if (Name.endswith("16") || Name.endswith("16_UPD"))
2391 DblSpaced = slice(insn, 5, 5) == 1;
2393 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2394 if (Name.endswith("32") || Name.endswith("32_UPD"))
2395 DblSpaced = slice(insn, 6, 6) == 1;
2398 // Multiple n-element structures with type encoded as Inst{11-8}.
2399 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2401 // n == 2 && type == 0b1001 -> DblSpaced = true
2402 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2403 DblSpaced = slice(insn, 11, 8) == 9;
2405 // n == 3 && type == 0b0101 -> DblSpaced = true
2406 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2407 DblSpaced = slice(insn, 11, 8) == 5;
2409 // n == 4 && type == 0b0001 -> DblSpaced = true
2410 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2411 DblSpaced = slice(insn, 11, 8) == 1;
2414 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2415 slice(insn, 21, 21) == 0, DblSpaced, B);
2420 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2421 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2423 const TargetInstrDesc &TID = ARMInsts[Opcode];
2424 const TargetOperandInfo *OpInfo = TID.OpInfo;
2426 assert(NumOps >= 2 &&
2427 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2428 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2429 (OpInfo[1].RegClass == 0) &&
2430 "Expect 1 reg operand followed by 1 imm operand");
2432 // Qd/Dd = Inst{22:15-12} => NEON Rd
2433 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2434 decodeNEONRd(insn))));
2436 ElemSize esize = ESizeNA;
2439 case ARM::VMOVv16i8:
2442 case ARM::VMOVv4i16:
2443 case ARM::VMOVv8i16:
2446 case ARM::VMOVv2i32:
2447 case ARM::VMOVv4i32:
2450 case ARM::VMOVv1i64:
2451 case ARM::VMOVv2i64:
2454 assert(0 && "Unreachable code!");
2458 // One register and a modified immediate value.
2459 // Add the imm operand.
2460 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2470 N2V_VectorConvert_Between_Float_Fixed
2472 } // End of unnamed namespace
2474 // Vector Convert [between floating-point and fixed-point]
2475 // Qd/Dd Qm/Dm [fbits]
2477 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2478 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2481 // Vector Move Long:
2484 // Vector Move Narrow:
2488 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2489 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2491 const TargetInstrDesc &TID = ARMInsts[Opc];
2492 const TargetOperandInfo *OpInfo = TID.OpInfo;
2494 assert(NumOps >= 2 &&
2495 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2496 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2497 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2498 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2499 "Expect >= 2 operands and first 2 as reg operands");
2501 unsigned &OpIdx = NumOpsAdded;
2505 ElemSize esize = ESizeNA;
2506 if (Flag == N2V_VectorDupLane) {
2507 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2508 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2509 "Unexpected Opcode");
2510 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2511 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2515 // Qd/Dd = Inst{22:15-12} => NEON Rd
2516 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2517 decodeNEONRd(insn))));
2521 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2523 MI.addOperand(MCOperand::CreateReg(0));
2527 // Dm = Inst{5:3-0} => NEON Rm
2528 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2529 decodeNEONRm(insn))));
2532 // VZIP and others have two TIED_TO reg operands.
2534 while (OpIdx < NumOps &&
2535 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2536 // Add TIED_TO operand.
2537 MI.addOperand(MI.getOperand(Idx));
2541 // Add the imm operand, if required.
2542 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2543 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2545 unsigned imm = 0xFFFFFFFF;
2547 if (Flag == N2V_VectorDupLane)
2548 imm = decodeNVLaneDupIndex(insn, esize);
2549 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2550 imm = decodeVCVTFractionBits(insn);
2552 assert(imm != 0xFFFFFFFF && "Internal error");
2553 MI.addOperand(MCOperand::CreateImm(imm));
2560 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2561 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2563 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2566 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2567 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2569 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2570 N2V_VectorConvert_Between_Float_Fixed, B);
2572 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2573 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2575 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2576 N2V_VectorDupLane, B);
2579 // Vector Shift [Accumulate] Instructions.
2580 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2582 // Vector Shift Left Long (with maximum shift count) Instructions.
2583 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2585 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2586 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2588 const TargetInstrDesc &TID = ARMInsts[Opcode];
2589 const TargetOperandInfo *OpInfo = TID.OpInfo;
2591 assert(NumOps >= 3 &&
2592 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2593 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2594 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2595 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2596 "Expect >= 3 operands and first 2 as reg operands");
2598 unsigned &OpIdx = NumOpsAdded;
2602 // Qd/Dd = Inst{22:15-12} => NEON Rd
2603 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2604 decodeNEONRd(insn))));
2607 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2609 MI.addOperand(MCOperand::CreateReg(0));
2613 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2614 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2615 "Reg operand expected");
2617 // Qm/Dm = Inst{5:3-0} => NEON Rm
2618 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2619 decodeNEONRm(insn))));
2622 assert(OpInfo[OpIdx].RegClass == 0 && "Imm operand expected");
2624 // Add the imm operand.
2626 // VSHLL has maximum shift count as the imm, inferred from its size.
2630 Imm = decodeNVSAmt(insn, LeftShift);
2642 MI.addOperand(MCOperand::CreateImm(Imm));
2648 // Left shift instructions.
2649 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2650 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2652 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2655 // Right shift instructions have different shift amount interpretation.
2656 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2657 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2659 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2668 N3V_Multiply_By_Scalar
2670 } // End of unnamed namespace
2672 // NEON Three Register Instructions with Optional Immediate Operand
2674 // Vector Extract Instructions.
2675 // Qd/Dd Qn/Dn Qm/Dm imm4
2677 // Vector Shift (Register) Instructions.
2678 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2680 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2681 // Qd/Dd Qn/Dn RestrictedDm index
2684 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2685 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2687 const TargetInstrDesc &TID = ARMInsts[Opcode];
2688 const TargetOperandInfo *OpInfo = TID.OpInfo;
2690 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2691 assert(NumOps >= 3 &&
2692 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2693 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2694 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2695 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2696 "Expect >= 3 operands and first 2 as reg operands");
2698 unsigned &OpIdx = NumOpsAdded;
2702 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2703 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2704 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2705 ElemSize esize = ESizeNA;
2706 if (Flag == N3V_Multiply_By_Scalar) {
2707 unsigned size = (insn >> 20) & 3;
2708 if (size == 1) esize = ESize16;
2709 if (size == 2) esize = ESize32;
2710 assert (esize == ESize16 || esize == ESize32);
2713 // Qd/Dd = Inst{22:15-12} => NEON Rd
2714 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2715 decodeNEONRd(insn))));
2718 // VABA, VABAL, VBSLd, VBSLq, ...
2719 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2721 MI.addOperand(MCOperand::CreateReg(0));
2725 // Dn = Inst{7:19-16} => NEON Rn
2727 // Dm = Inst{5:3-0} => NEON Rm
2728 MI.addOperand(MCOperand::CreateReg(
2729 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2730 VdVnVm ? decodeNEONRn(insn)
2731 : decodeNEONRm(insn))));
2734 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2736 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2739 // Dm = Inst{5:3-0} => NEON Rm
2741 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2743 // Dn = Inst{7:19-16} => NEON Rn
2744 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2745 : decodeNEONRm(insn))
2746 : decodeNEONRn(insn);
2748 MI.addOperand(MCOperand::CreateReg(
2749 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2752 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2753 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2754 // Add the imm operand.
2757 Imm = decodeN3VImm(insn);
2758 else if (IsDmRestricted)
2759 Imm = decodeRestrictedDmIndex(insn, esize);
2761 assert(0 && "Internal error: unreachable code!");
2765 MI.addOperand(MCOperand::CreateImm(Imm));
2772 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2773 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2775 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2778 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2779 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2781 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2782 N3V_VectorShift, B);
2784 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2785 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2787 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2788 N3V_VectorExtract, B);
2790 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2791 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2793 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2794 N3V_Multiply_By_Scalar, B);
2797 // Vector Table Lookup
2799 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2800 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2801 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2802 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2803 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2804 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2806 const TargetInstrDesc &TID = ARMInsts[Opcode];
2807 const TargetOperandInfo *OpInfo = TID.OpInfo;
2808 if (!OpInfo) return false;
2810 assert(NumOps >= 3 &&
2811 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2812 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2813 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2814 "Expect >= 3 operands and first 3 as reg operands");
2816 unsigned &OpIdx = NumOpsAdded;
2820 unsigned Rn = decodeNEONRn(insn);
2822 // {Dn} encoded as len = 0b00
2823 // {Dn Dn+1} encoded as len = 0b01
2824 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2825 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2826 unsigned Len = slice(insn, 9, 8) + 1;
2828 // Dd (the destination vector)
2829 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2830 decodeNEONRd(insn))));
2833 // Process tied_to operand constraint.
2835 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2836 MI.addOperand(MI.getOperand(Idx));
2840 // Do the <list> now.
2841 for (unsigned i = 0; i < Len; ++i) {
2842 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2843 "Reg operand expected");
2844 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2849 // Dm (the index vector)
2850 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2851 "Reg operand (index vector) expected");
2852 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2853 decodeNEONRm(insn))));
2859 static bool DisassembleNEONFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2860 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
2861 assert(0 && "Unreachable code!");
2865 // Vector Get Lane (move scalar to ARM core register) Instructions.
2866 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2867 static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2868 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2870 const TargetInstrDesc &TID = ARMInsts[Opcode];
2871 const TargetOperandInfo *OpInfo = TID.OpInfo;
2872 if (!OpInfo) return false;
2874 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2875 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2876 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2877 OpInfo[2].RegClass == 0 &&
2878 "Expect >= 3 operands with one dst operand");
2881 Opcode == ARM::VGETLNi32 ? ESize32
2882 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2885 // Rt = Inst{15-12} => ARM Rd
2886 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2889 // Dn = Inst{7:19-16} => NEON Rn
2890 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2891 decodeNEONRn(insn))));
2893 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2899 // Vector Set Lane (move ARM core register to scalar) Instructions.
2900 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2901 static bool DisassembleNEONSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2902 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2904 const TargetInstrDesc &TID = ARMInsts[Opcode];
2905 const TargetOperandInfo *OpInfo = TID.OpInfo;
2906 if (!OpInfo) return false;
2908 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2909 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2910 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2911 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2912 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2913 OpInfo[3].RegClass == 0 &&
2914 "Expect >= 3 operands with one dst operand");
2917 Opcode == ARM::VSETLNi8 ? ESize8
2918 : (Opcode == ARM::VSETLNi16 ? ESize16
2921 // Dd = Inst{7:19-16} => NEON Rn
2922 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2923 decodeNEONRn(insn))));
2926 MI.addOperand(MCOperand::CreateReg(0));
2928 // Rt = Inst{15-12} => ARM Rd
2929 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2932 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2938 // Vector Duplicate Instructions (from ARM core register to all elements).
2939 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2940 static bool DisassembleNEONDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2941 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2943 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2945 assert(NumOps >= 2 &&
2946 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2947 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2948 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2949 "Expect >= 2 operands and first 2 as reg operand");
2951 unsigned RegClass = OpInfo[0].RegClass;
2953 // Qd/Dd = Inst{7:19-16} => NEON Rn
2954 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2955 decodeNEONRn(insn))));
2957 // Rt = Inst{15-12} => ARM Rd
2958 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2968 static inline bool MemBarrierInstr(uint32_t insn) {
2969 unsigned op7_4 = slice(insn, 7, 4);
2970 if (slice(insn, 31, 20) == 0xf57 && (op7_4 >= 4 && op7_4 <= 6))
2976 static inline bool PreLoadOpcode(unsigned Opcode) {
2978 case ARM::PLDi: case ARM::PLDr:
2979 case ARM::PLDWi: case ARM::PLDWr:
2980 case ARM::PLIi: case ARM::PLIr:
2987 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2988 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2990 // Preload Data/Instruction requires either 2 or 4 operands.
2991 // PLDi, PLDWi, PLIi: Rn [+/-]imm12 add = (U == '1')
2992 // PLDr[a|m], PLDWr[a|m], PLIr[a|m]: Rn Rm addrmode2_opc
2994 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2997 if (Opcode == ARM::PLDi || Opcode == ARM::PLDWi || Opcode == ARM::PLIi) {
2998 unsigned Imm12 = slice(insn, 11, 0);
2999 bool Negative = getUBit(insn) == 0;
3000 int Offset = Negative ? -1 - Imm12 : 1 * Imm12;
3001 MI.addOperand(MCOperand::CreateImm(Offset));
3004 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
3007 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
3009 // Inst{6-5} encodes the shift opcode.
3010 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
3011 // Inst{11-7} encodes the imm5 shift amount.
3012 unsigned ShImm = slice(insn, 11, 7);
3014 // A8.4.1. Possible rrx or shift amount of 32...
3015 getImmShiftSE(ShOp, ShImm);
3016 MI.addOperand(MCOperand::CreateImm(
3017 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
3024 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
3025 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
3027 if (MemBarrierInstr(insn))
3045 // CPS has a singleton $opt operand that contains the following information:
3046 // opt{4-0} = mode from Inst{4-0}
3047 // opt{5} = changemode from Inst{17}
3048 // opt{8-6} = AIF from Inst{8-6}
3049 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3050 if (Opcode == ARM::CPS) {
3051 unsigned Option = slice(insn, 4, 0) | slice(insn, 17, 17) << 5 |
3052 slice(insn, 8, 6) << 6 | slice(insn, 19, 18) << 9;
3053 MI.addOperand(MCOperand::CreateImm(Option));
3058 // DBG has its option specified in Inst{3-0}.
3059 if (Opcode == ARM::DBG) {
3060 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3065 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
3066 if (Opcode == ARM::BKPT) {
3067 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
3068 slice(insn, 3, 0)));
3073 if (PreLoadOpcode(Opcode))
3074 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
3076 assert(0 && "Unexpected misc instruction!");
3080 static bool DisassembleThumbMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
3081 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
3083 assert(0 && "Unexpected thumb misc. instruction!");
3087 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
3088 /// We divide the disassembly task into different categories, with each one
3089 /// corresponding to a specific instruction encoding format. There could be
3090 /// exceptions when handling a specific format, and that is why the Opcode is
3091 /// also present in the function prototype.
3092 static const DisassembleFP FuncPtrs[] = {
3096 &DisassembleBrMiscFrm,
3098 &DisassembleDPSoRegFrm,
3101 &DisassembleLdMiscFrm,
3102 &DisassembleStMiscFrm,
3103 &DisassembleLdStMulFrm,
3104 &DisassembleLdStExFrm,
3105 &DisassembleArithMiscFrm,
3107 &DisassembleVFPUnaryFrm,
3108 &DisassembleVFPBinaryFrm,
3109 &DisassembleVFPConv1Frm,
3110 &DisassembleVFPConv2Frm,
3111 &DisassembleVFPConv3Frm,
3112 &DisassembleVFPConv4Frm,
3113 &DisassembleVFPConv5Frm,
3114 &DisassembleVFPLdStFrm,
3115 &DisassembleVFPLdStMulFrm,
3116 &DisassembleVFPMiscFrm,
3117 &DisassembleThumbFrm,
3118 &DisassembleNEONFrm,
3119 &DisassembleNEONGetLnFrm,
3120 &DisassembleNEONSetLnFrm,
3121 &DisassembleNEONDupFrm,
3122 &DisassembleMiscFrm,
3123 &DisassembleThumbMiscFrm,
3125 // VLD and VST (including one lane) Instructions.
3128 // A7.4.6 One register and a modified immediate value
3129 // 1-Register Instructions with imm.
3130 // LLVM only defines VMOVv instructions.
3131 &DisassembleN1RegModImmFrm,
3133 // 2-Register Instructions with no imm.
3134 &DisassembleN2RegFrm,
3136 // 2-Register Instructions with imm (vector convert float/fixed point).
3137 &DisassembleNVCVTFrm,
3139 // 2-Register Instructions with imm (vector dup lane).
3140 &DisassembleNVecDupLnFrm,
3142 // Vector Shift Left Instructions.
3143 &DisassembleN2RegVecShLFrm,
3145 // Vector Shift Righ Instructions, which has different interpretation of the
3146 // shift amount from the imm6 field.
3147 &DisassembleN2RegVecShRFrm,
3149 // 3-Register Data-Processing Instructions.
3150 &DisassembleN3RegFrm,
3152 // Vector Shift (Register) Instructions.
3153 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3154 &DisassembleN3RegVecShFrm,
3156 // Vector Extract Instructions.
3157 &DisassembleNVecExtractFrm,
3159 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3160 // By Scalar Instructions.
3161 &DisassembleNVecMulScalarFrm,
3163 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3164 // values in a table and generate a new vector.
3165 &DisassembleNVTBLFrm,
3170 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3171 /// The general idea is to set the Opcode for the MCInst, followed by adding
3172 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3173 /// to the Format-specific disassemble function for disassembly, followed by
3174 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3175 /// which follow the Dst/Src Operands.
3176 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3177 // Stage 1 sets the Opcode.
3178 MI.setOpcode(Opcode);
3179 // If the number of operands is zero, we're done!
3183 // Stage 2 calls the format-specific disassemble function to build the operand
3187 unsigned NumOpsAdded = 0;
3188 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3190 if (!OK || this->Err != 0) return false;
3191 if (NumOpsAdded >= NumOps)
3194 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3195 // FIXME: Should this be done selectively?
3196 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3199 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3200 uint32_t insn, unsigned short NumOpsRemaining) {
3202 assert(NumOpsRemaining > 0 && "Invalid argument");
3204 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3205 const std::string &Name = ARMInsts[Opcode].Name;
3206 unsigned Idx = MI.getNumOperands();
3208 // First, we check whether this instr specifies the PredicateOperand through
3209 // a pair of TargetOperandInfos with isPredicate() property.
3210 if (NumOpsRemaining >= 2 &&
3211 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3212 OpInfo[Idx].RegClass == 0 && OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3214 // If we are inside an IT block, get the IT condition bits maintained via
3215 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3218 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3220 if (Name.length() > 1 && Name[0] == 't') {
3221 // Thumb conditional branch instructions have their cond field embedded,
3225 if (Name == "t2Bcc")
3226 MI.addOperand(MCOperand::CreateImm(slice(insn, 25, 22)));
3227 else if (Name == "tBcc")
3228 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 8)));
3230 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3232 // ARM Instructions. Check condition field.
3233 int64_t CondVal = getCondField(insn);
3235 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3237 MI.addOperand(MCOperand::CreateImm(CondVal));
3240 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3242 NumOpsRemaining -= 2;
3243 if (NumOpsRemaining == 0)
3247 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3248 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3249 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3253 if (NumOpsRemaining == 0)
3259 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3260 /// after BuildIt is finished.
3261 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3264 if (!SP) return Status;
3266 if (Opcode == ARM::t2IT)
3267 SP->InitIT(slice(insn, 7, 0));
3268 else if (InITBlock())
3274 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3275 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3277 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3278 unsigned Idx = (unsigned)format;
3279 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3280 Disasm = FuncPtrs[Idx];
3283 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3284 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3285 /// Return NULL if it fails to create/return a proper builder. API clients
3286 /// are responsible for freeing up of the allocated memory. Cacheing can be
3287 /// performed by the API clients to improve performance.
3288 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3289 // For "Unknown format", fail by returning a NULL pointer.
3290 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1))
3293 return new ARMBasicMCBuilder(Opcode, Format,
3294 ARMInsts[Opcode].getNumOperands());