1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassemblerCore.h"
19 #include "ARMAddressingModes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
23 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
24 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
25 /// describing the operand info for each ARMInsts[i].
27 /// Together with an instruction's encoding format, we can take advantage of the
28 /// NumOperands and the OpInfo fields of the target instruction description in
29 /// the quest to build out the MCOperand list for an MCInst.
31 /// The general guideline is that with a known format, the number of dst and src
32 /// operands are well-known. The dst is built first, followed by the src
33 /// operand(s). The operands not yet used at this point are for the Implicit
34 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
35 /// defined with two components:
37 /// def pred { // Operand PredicateOperand
38 /// ValueType Type = OtherVT;
39 /// string PrintMethod = "printPredicateOperand";
40 /// string AsmOperandLowerMethod = ?;
41 /// dag MIOperandInfo = (ops i32imm, CCR);
42 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
43 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
46 /// which is manifested by the TargetOperandInfo[] of:
48 /// { 0, 0|(1<<TOI::Predicate), 0 },
49 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
51 /// So the first predicate MCOperand corresponds to the immediate part of the
52 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
53 /// corresponds to a register kind of ARM::CPSR.
55 /// For the Defs part, in the simple case of only cc_out:$s, we have:
57 /// def cc_out { // Operand OptionalDefOperand
58 /// ValueType Type = OtherVT;
59 /// string PrintMethod = "printSBitModifierOperand";
60 /// string AsmOperandLowerMethod = ?;
61 /// dag MIOperandInfo = (ops CCR);
62 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
63 /// dag DefaultOps = (ops (i32 zero_reg));
66 /// which is manifested by the one TargetOperandInfo of:
68 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
70 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
71 #include "ARMGenInstrInfo.inc"
75 const char *ARMUtils::OpcodeName(unsigned Opcode) {
76 return ARMInsts[Opcode].Name;
79 // Return the register enum Based on RegClass and the raw register number.
80 // For DRegPair, see comments below.
82 static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister,
83 bool DRegPair = false) {
85 if (DRegPair && RegClassID == ARM::QPRRegClassID) {
86 // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified
87 // in the ARM Architecture Manual as far as I understand it (A8.6.307).
88 // Therefore, we morph the RegClassID to be the sub register class and don't
89 // subsequently transform the RawRegister encoding when calculating RegNum.
91 // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part
92 // where this workaround is meant for.
93 RegClassID = ARM::DPRRegClassID;
96 // For this purpose, we can treat rGPR as if it were GPR.
97 if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
99 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
101 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
107 switch (RegClassID) {
108 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
109 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
110 case ARM::DPR_VFP2RegClassID:
112 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
113 case ARM::QPR_VFP2RegClassID:
115 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
119 switch (RegClassID) {
120 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
121 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
122 case ARM::DPR_VFP2RegClassID:
124 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
125 case ARM::QPR_VFP2RegClassID:
127 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
131 switch (RegClassID) {
132 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
133 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
134 case ARM::DPR_VFP2RegClassID:
136 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
137 case ARM::QPR_VFP2RegClassID:
139 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
143 switch (RegClassID) {
144 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
145 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
146 case ARM::DPR_VFP2RegClassID:
148 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
149 case ARM::QPR_VFP2RegClassID:
151 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
155 switch (RegClassID) {
156 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
157 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
158 case ARM::DPR_VFP2RegClassID:
160 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
161 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
165 switch (RegClassID) {
166 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
167 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
168 case ARM::DPR_VFP2RegClassID:
170 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
171 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
175 switch (RegClassID) {
176 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
177 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
178 case ARM::DPR_VFP2RegClassID:
180 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
181 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
185 switch (RegClassID) {
186 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
187 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
188 case ARM::DPR_VFP2RegClassID:
190 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
191 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
195 switch (RegClassID) {
196 case ARM::GPRRegClassID: return ARM::R8;
197 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
198 case ARM::QPRRegClassID: return ARM::Q8;
199 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
203 switch (RegClassID) {
204 case ARM::GPRRegClassID: return ARM::R9;
205 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
206 case ARM::QPRRegClassID: return ARM::Q9;
207 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
211 switch (RegClassID) {
212 case ARM::GPRRegClassID: return ARM::R10;
213 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
214 case ARM::QPRRegClassID: return ARM::Q10;
215 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
219 switch (RegClassID) {
220 case ARM::GPRRegClassID: return ARM::R11;
221 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
222 case ARM::QPRRegClassID: return ARM::Q11;
223 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
227 switch (RegClassID) {
228 case ARM::GPRRegClassID: return ARM::R12;
229 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
230 case ARM::QPRRegClassID: return ARM::Q12;
231 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
235 switch (RegClassID) {
236 case ARM::GPRRegClassID: return ARM::SP;
237 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
238 case ARM::QPRRegClassID: return ARM::Q13;
239 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
243 switch (RegClassID) {
244 case ARM::GPRRegClassID: return ARM::LR;
245 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
246 case ARM::QPRRegClassID: return ARM::Q14;
247 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
251 switch (RegClassID) {
252 case ARM::GPRRegClassID: return ARM::PC;
253 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
254 case ARM::QPRRegClassID: return ARM::Q15;
255 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
259 switch (RegClassID) {
260 case ARM::DPRRegClassID: return ARM::D16;
261 case ARM::SPRRegClassID: return ARM::S16;
265 switch (RegClassID) {
266 case ARM::DPRRegClassID: return ARM::D17;
267 case ARM::SPRRegClassID: return ARM::S17;
271 switch (RegClassID) {
272 case ARM::DPRRegClassID: return ARM::D18;
273 case ARM::SPRRegClassID: return ARM::S18;
277 switch (RegClassID) {
278 case ARM::DPRRegClassID: return ARM::D19;
279 case ARM::SPRRegClassID: return ARM::S19;
283 switch (RegClassID) {
284 case ARM::DPRRegClassID: return ARM::D20;
285 case ARM::SPRRegClassID: return ARM::S20;
289 switch (RegClassID) {
290 case ARM::DPRRegClassID: return ARM::D21;
291 case ARM::SPRRegClassID: return ARM::S21;
295 switch (RegClassID) {
296 case ARM::DPRRegClassID: return ARM::D22;
297 case ARM::SPRRegClassID: return ARM::S22;
301 switch (RegClassID) {
302 case ARM::DPRRegClassID: return ARM::D23;
303 case ARM::SPRRegClassID: return ARM::S23;
307 switch (RegClassID) {
308 case ARM::DPRRegClassID: return ARM::D24;
309 case ARM::SPRRegClassID: return ARM::S24;
313 switch (RegClassID) {
314 case ARM::DPRRegClassID: return ARM::D25;
315 case ARM::SPRRegClassID: return ARM::S25;
319 switch (RegClassID) {
320 case ARM::DPRRegClassID: return ARM::D26;
321 case ARM::SPRRegClassID: return ARM::S26;
325 switch (RegClassID) {
326 case ARM::DPRRegClassID: return ARM::D27;
327 case ARM::SPRRegClassID: return ARM::S27;
331 switch (RegClassID) {
332 case ARM::DPRRegClassID: return ARM::D28;
333 case ARM::SPRRegClassID: return ARM::S28;
337 switch (RegClassID) {
338 case ARM::DPRRegClassID: return ARM::D29;
339 case ARM::SPRRegClassID: return ARM::S29;
343 switch (RegClassID) {
344 case ARM::DPRRegClassID: return ARM::D30;
345 case ARM::SPRRegClassID: return ARM::S30;
349 switch (RegClassID) {
350 case ARM::DPRRegClassID: return ARM::D31;
351 case ARM::SPRRegClassID: return ARM::S31;
355 DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
356 // Encoding error. Mark the builder with error code != 0.
361 ///////////////////////////////
363 // Utility Functions //
365 ///////////////////////////////
367 // Extract/Decode Rd: Inst{15-12}.
368 static inline unsigned decodeRd(uint32_t insn) {
369 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
372 // Extract/Decode Rn: Inst{19-16}.
373 static inline unsigned decodeRn(uint32_t insn) {
374 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
377 // Extract/Decode Rm: Inst{3-0}.
378 static inline unsigned decodeRm(uint32_t insn) {
379 return (insn & ARMII::GPRRegMask);
382 // Extract/Decode Rs: Inst{11-8}.
383 static inline unsigned decodeRs(uint32_t insn) {
384 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
387 static inline unsigned getCondField(uint32_t insn) {
388 return (insn >> ARMII::CondShift);
391 static inline unsigned getIBit(uint32_t insn) {
392 return (insn >> ARMII::I_BitShift) & 1;
395 static inline unsigned getAM3IBit(uint32_t insn) {
396 return (insn >> ARMII::AM3_I_BitShift) & 1;
399 static inline unsigned getPBit(uint32_t insn) {
400 return (insn >> ARMII::P_BitShift) & 1;
403 static inline unsigned getUBit(uint32_t insn) {
404 return (insn >> ARMII::U_BitShift) & 1;
407 static inline unsigned getPUBits(uint32_t insn) {
408 return (insn >> ARMII::U_BitShift) & 3;
411 static inline unsigned getSBit(uint32_t insn) {
412 return (insn >> ARMII::S_BitShift) & 1;
415 static inline unsigned getWBit(uint32_t insn) {
416 return (insn >> ARMII::W_BitShift) & 1;
419 static inline unsigned getDBit(uint32_t insn) {
420 return (insn >> ARMII::D_BitShift) & 1;
423 static inline unsigned getNBit(uint32_t insn) {
424 return (insn >> ARMII::N_BitShift) & 1;
427 static inline unsigned getMBit(uint32_t insn) {
428 return (insn >> ARMII::M_BitShift) & 1;
431 // See A8.4 Shifts applied to a register.
432 // A8.4.2 Register controlled shifts.
434 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
435 // into llvm enums for shift opcode. The API clients should pass in the value
436 // encoded with two bits, so the assert stays to signal a wrong API usage.
438 // A8-12: DecodeRegShift()
439 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
441 default: assert(0 && "No such value"); return ARM_AM::no_shift;
442 case 0: return ARM_AM::lsl;
443 case 1: return ARM_AM::lsr;
444 case 2: return ARM_AM::asr;
445 case 3: return ARM_AM::ror;
449 // See A8.4 Shifts applied to a register.
450 // A8.4.1 Constant shifts.
452 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
453 // encodings into the intended ShiftOpc and shift amount.
455 // A8-11: DecodeImmShift()
456 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
457 // If type == 0b11 and imm5 == 0, we have an rrx, instead.
458 if (ShOp == ARM_AM::ror && ShImm == 0)
460 // If (lsr or asr) and imm5 == 0, shift amount is 32.
461 if ((ShOp == ARM_AM::lsr || ShOp == ARM_AM::asr) && ShImm == 0)
465 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
466 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
467 // clients should pass in the value encoded with two bits, so the assert stays
468 // to signal a wrong API usage.
469 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
471 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
472 case 1: return ARM_AM::ia; // P=0 U=1
473 case 3: return ARM_AM::ib; // P=1 U=1
474 case 0: return ARM_AM::da; // P=0 U=0
475 case 2: return ARM_AM::db; // P=1 U=0
479 ////////////////////////////////////////////
481 // Disassemble function definitions //
483 ////////////////////////////////////////////
485 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
486 /// instr into a list of MCOperands in the appropriate order, with possible dst,
487 /// followed by possible src(s).
489 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
490 /// the CPSR, is factored into ARMBasicMCBuilder's method named
491 /// TryPredicateAndSBitModifier.
493 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
494 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
496 if (Opcode == ARM::Int_MemBarrierV7 || Opcode == ARM::Int_SyncBarrierV7)
499 assert(0 && "Unexpected pseudo instruction!");
503 // Multiply Instructions.
504 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
505 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
507 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
508 // Rd{19-16} Rn{3-0} Rm{11-8}
510 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
511 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
513 // The mapping of the multiply registers to the "regular" ARM registers, where
514 // there are convenience decoder functions, is:
520 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
521 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
523 const TargetInstrDesc &TID = ARMInsts[Opcode];
524 unsigned short NumDefs = TID.getNumDefs();
525 const TargetOperandInfo *OpInfo = TID.OpInfo;
526 unsigned &OpIdx = NumOpsAdded;
530 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
532 && OpInfo[0].RegClass == ARM::GPRRegClassID
533 && OpInfo[1].RegClass == ARM::GPRRegClassID
534 && OpInfo[2].RegClass == ARM::GPRRegClassID
535 && "Expect three register operands");
537 // Instructions with two destination registers have RdLo{15-12} first.
539 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
540 "Expect 4th register operand");
541 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
546 // The destination register: RdHi{19-16} or Rd{19-16}.
547 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
550 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
551 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
553 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
557 // Many multiply instructions (e.g., MLA) have three src registers.
558 // The third register operand is Ra{15-12}.
559 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
560 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
568 // Helper routines for disassembly of coprocessor instructions.
570 static bool LdStCopOpcode(unsigned Opcode) {
571 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
572 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
576 static bool CoprocessorOpcode(unsigned Opcode) {
577 if (LdStCopOpcode(Opcode))
583 case ARM::CDP: case ARM::CDP2:
584 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
585 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
589 static inline unsigned GetCoprocessor(uint32_t insn) {
590 return slice(insn, 11, 8);
592 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
593 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
595 static inline unsigned GetCopOpc2(uint32_t insn) {
596 return slice(insn, 7, 5);
598 static inline unsigned GetCopOpc(uint32_t insn) {
599 return slice(insn, 7, 4);
601 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
604 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
606 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
608 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
610 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
612 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
616 // LDC_OPTION: cop CRd Rn imm8
618 // STC_OPTION: cop CRd Rn imm8
621 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
622 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
624 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
626 unsigned &OpIdx = NumOpsAdded;
627 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
628 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
629 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
630 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
631 bool LdStCop = LdStCopOpcode(Opcode);
635 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
638 // Unindex if P:W = 0b00 --> _OPTION variant
639 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
641 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
643 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
647 MI.addOperand(MCOperand::CreateReg(0));
648 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
649 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
651 MI.addOperand(MCOperand::CreateImm(Offset));
654 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
658 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
659 : GetCopOpc1(insn, NoGPR)));
661 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
662 : MCOperand::CreateReg(
663 getRegisterEnum(B, ARM::GPRRegClassID,
666 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
667 getRegisterEnum(B, ARM::GPRRegClassID,
669 : MCOperand::CreateImm(decodeRn(insn)));
671 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
676 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
684 // Branch Instructions.
685 // BLr9: SignExtend(Imm24:'00', 32)
686 // Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
687 // SMC: ZeroExtend(imm4, 32)
688 // SVC: ZeroExtend(Imm24, 32)
690 // Various coprocessor instructions are assigned BrFrm arbitrarily.
691 // Delegates to DisassembleCoprocessor() helper function.
694 // MSR/MSRsys: Rm mask=Inst{19-16}
696 // MSRi/MSRsysi: so_imm
697 // SRSW/SRS: addrmode4:$addr mode_imm
698 // RFEW/RFE: addrmode4:$addr Rn
699 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
700 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
702 if (CoprocessorOpcode(Opcode))
703 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
705 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
706 if (!OpInfo) return false;
708 // MRS and MRSsys take one GPR reg Rd.
709 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
710 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
711 "Reg operand expected");
712 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
717 // BXJ takes one GPR reg Rm.
718 if (Opcode == ARM::BXJ) {
719 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
720 "Reg operand expected");
721 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
726 // MSR and MSRsys take one GPR reg Rm, followed by the mask.
727 if (Opcode == ARM::MSR || Opcode == ARM::MSRsys) {
728 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
729 "Reg operand expected");
730 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
732 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
736 // MSRi and MSRsysi take one so_imm operand, followed by the mask.
737 if (Opcode == ARM::MSRi || Opcode == ARM::MSRsysi) {
738 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
739 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
740 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
741 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
742 unsigned Imm = insn & 0xFF;
743 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
744 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
748 // SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the
749 // mode immediate (Inst{4-0}).
750 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
751 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
752 // ARMInstPrinter::printAddrMode4Operand() prints special mode string
753 // if the base register is SP; so don't set ARM::SP.
754 MI.addOperand(MCOperand::CreateReg(0));
755 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
756 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
758 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
759 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
761 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
767 assert((Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred
768 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
769 "Unexpected Opcode");
771 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected");
774 if (Opcode == ARM::SMC) {
775 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
776 Imm32 = slice(insn, 3, 0);
777 } else if (Opcode == ARM::SVC) {
778 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
779 Imm32 = slice(insn, 23, 0);
781 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
782 unsigned Imm26 = slice(insn, 23, 0) << 2;
783 //Imm32 = signextend<signed int, 26>(Imm26);
784 Imm32 = SignExtend32<26>(Imm26);
786 // When executing an ARM instruction, PC reads as the address of the current
787 // instruction plus 8. The assembler subtracts 8 from the difference
788 // between the branch instruction and the target address, disassembler has
789 // to add 8 to compensate.
793 MI.addOperand(MCOperand::CreateImm(Imm32));
799 // Misc. Branch Instructions.
800 // BR_JTadd, BR_JTr, BR_JTm
803 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
804 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
806 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
807 if (!OpInfo) return false;
809 unsigned &OpIdx = NumOpsAdded;
813 // BX_RET has only two predicate operands, do an early return.
814 if (Opcode == ARM::BX_RET)
817 // BLXr9 and BRIND take one GPR reg.
818 if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
819 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
820 "Reg operand expected");
821 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
827 // BR_JTadd is an ADD with Rd = PC, (Rn, Rm) as the target and index regs.
828 if (Opcode == ARM::BR_JTadd) {
829 // InOperandList with GPR:$target and GPR:$idx regs.
831 assert(NumOps == 4 && "Expect 4 operands");
832 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
834 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
837 // Fill in the two remaining imm operands to signify build completion.
838 MI.addOperand(MCOperand::CreateImm(0));
839 MI.addOperand(MCOperand::CreateImm(0));
845 // BR_JTr is a MOV with Rd = PC, and Rm as the source register.
846 if (Opcode == ARM::BR_JTr) {
847 // InOperandList with GPR::$target reg.
849 assert(NumOps == 3 && "Expect 3 operands");
850 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
853 // Fill in the two remaining imm operands to signify build completion.
854 MI.addOperand(MCOperand::CreateImm(0));
855 MI.addOperand(MCOperand::CreateImm(0));
861 // BR_JTm is an LDR with Rt = PC.
862 if (Opcode == ARM::BR_JTm) {
863 // This is the reg/reg form, with base reg followed by +/- reg shop imm.
864 // See also ARMAddressingModes.h (Addressing Mode #2).
866 assert(NumOps == 5 && getIBit(insn) == 1 && "Expect 5 operands && I-bit=1");
867 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
870 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
872 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
873 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
875 // Inst{6-5} encodes the shift opcode.
876 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
877 // Inst{11-7} encodes the imm5 shift amount.
878 unsigned ShImm = slice(insn, 11, 7);
880 // A8.4.1. Possible rrx or shift amount of 32...
881 getImmShiftSE(ShOp, ShImm);
882 MI.addOperand(MCOperand::CreateImm(
883 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
885 // Fill in the two remaining imm operands to signify build completion.
886 MI.addOperand(MCOperand::CreateImm(0));
887 MI.addOperand(MCOperand::CreateImm(0));
896 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
897 uint32_t lsb = slice(insn, 11, 7);
898 uint32_t msb = slice(insn, 20, 16);
901 DEBUG(errs() << "Encoding error: msb < lsb\n");
905 for (uint32_t i = lsb; i <= msb; ++i)
911 static inline bool SaturateOpcode(unsigned Opcode) {
913 case ARM::SSATlsl: case ARM::SSATasr: case ARM::SSAT16:
914 case ARM::USATlsl: case ARM::USATasr: case ARM::USAT16:
921 static inline unsigned decodeSaturatePos(unsigned Opcode, uint32_t insn) {
925 return slice(insn, 20, 16) + 1;
927 return slice(insn, 19, 16) + 1;
930 return slice(insn, 20, 16);
932 return slice(insn, 19, 16);
934 assert(0 && "Invalid opcode passed in");
939 // A major complication is the fact that some of the saturating add/subtract
940 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
941 // They are QADD, QDADD, QDSUB, and QSUB.
942 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
943 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
945 const TargetInstrDesc &TID = ARMInsts[Opcode];
946 unsigned short NumDefs = TID.getNumDefs();
947 bool isUnary = isUnaryDP(TID.TSFlags);
948 const TargetOperandInfo *OpInfo = TID.OpInfo;
949 unsigned &OpIdx = NumOpsAdded;
953 // Disassemble register def if there is one.
954 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
955 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
960 // Now disassemble the src operands.
964 // SSAT/SSAT16/USAT/USAT16 has imm operand after Rd.
965 if (SaturateOpcode(Opcode)) {
966 MI.addOperand(MCOperand::CreateImm(decodeSaturatePos(Opcode, insn)));
968 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
971 if (Opcode == ARM::SSAT16 || Opcode == ARM::USAT16) {
976 // For SSAT operand reg (Rm) has been disassembled above.
977 // Now disassemble the shift amount.
979 // Inst{11-7} encodes the imm5 shift amount.
980 unsigned ShAmt = slice(insn, 11, 7);
982 // A8.6.183. Possible ASR shift amount of 32...
983 if (Opcode == ARM::SSATasr && ShAmt == 0)
986 MI.addOperand(MCOperand::CreateImm(ShAmt));
992 // Special-case handling of BFC/BFI/SBFX/UBFX.
993 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
994 MI.addOperand(MCOperand::CreateReg(0));
995 if (Opcode == ARM::BFI) {
996 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1001 if (!getBFCInvMask(insn, mask))
1004 MI.addOperand(MCOperand::CreateImm(mask));
1008 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
1009 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1011 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
1012 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
1017 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
1018 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
1020 // BinaryDP has an Rn operand.
1022 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1023 "Reg operand expected");
1024 MI.addOperand(MCOperand::CreateReg(
1025 getRegisterEnum(B, ARM::GPRRegClassID,
1026 RmRn ? decodeRm(insn) : decodeRn(insn))));
1030 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
1031 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1032 MI.addOperand(MCOperand::CreateReg(0));
1036 // Now disassemble operand 2.
1037 if (OpIdx >= NumOps)
1040 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
1041 // We have a reg/reg form.
1042 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
1043 // routed here as well.
1044 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
1045 MI.addOperand(MCOperand::CreateReg(
1046 getRegisterEnum(B, ARM::GPRRegClassID,
1047 RmRn? decodeRn(insn) : decodeRm(insn))));
1049 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
1050 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
1051 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1052 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
1053 MI.addOperand(MCOperand::CreateImm(Imm16));
1056 // We have a reg/imm form.
1057 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
1058 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
1059 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
1060 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1061 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
1062 unsigned Imm = insn & 0xFF;
1063 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
1070 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1071 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1073 const TargetInstrDesc &TID = ARMInsts[Opcode];
1074 unsigned short NumDefs = TID.getNumDefs();
1075 bool isUnary = isUnaryDP(TID.TSFlags);
1076 const TargetOperandInfo *OpInfo = TID.OpInfo;
1077 unsigned &OpIdx = NumOpsAdded;
1081 // Disassemble register def if there is one.
1082 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
1083 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1088 // Disassemble the src operands.
1089 if (OpIdx >= NumOps)
1092 // BinaryDP has an Rn operand.
1094 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1095 "Reg operand expected");
1096 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1101 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
1102 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1103 MI.addOperand(MCOperand::CreateReg(0));
1107 // Disassemble operand 2, which consists of three components.
1108 if (OpIdx + 2 >= NumOps)
1111 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1112 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
1113 (OpInfo[OpIdx+2].RegClass < 0) &&
1114 "Expect 3 reg operands");
1116 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
1117 unsigned Rs = slice(insn, 4, 4);
1119 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1122 // Register-controlled shifts: [Rm, Rs, shift].
1123 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1125 // Inst{6-5} encodes the shift opcode.
1126 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1127 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
1129 // Constant shifts: [Rm, reg0, shift_imm].
1130 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
1131 // Inst{6-5} encodes the shift opcode.
1132 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1133 // Inst{11-7} encodes the imm5 shift amount.
1134 unsigned ShImm = slice(insn, 11, 7);
1136 // A8.4.1. Possible rrx or shift amount of 32...
1137 getImmShiftSE(ShOp, ShImm);
1138 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1145 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1146 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1148 const TargetInstrDesc &TID = ARMInsts[Opcode];
1149 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1150 const TargetOperandInfo *OpInfo = TID.OpInfo;
1151 if (!OpInfo) return false;
1153 unsigned &OpIdx = NumOpsAdded;
1157 assert(((!isStore && TID.getNumDefs() > 0) ||
1158 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1159 && "Invalid arguments");
1161 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1162 if (isPrePost && isStore) {
1163 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1164 "Reg operand expected");
1165 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1170 // Disassemble the dst/src operand.
1171 if (OpIdx >= NumOps)
1174 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1175 "Reg operand expected");
1176 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1180 // After dst of a pre- and post-indexed load is the address base writeback.
1181 if (isPrePost && !isStore) {
1182 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1183 "Reg operand expected");
1184 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1189 // Disassemble the base operand.
1190 if (OpIdx >= NumOps)
1193 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1194 "Reg operand expected");
1195 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1196 && "Index mode or tied_to operand expected");
1197 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1201 // For reg/reg form, base reg is followed by +/- reg shop imm.
1202 // For immediate form, it is followed by +/- imm12.
1203 // See also ARMAddressingModes.h (Addressing Mode #2).
1204 if (OpIdx + 1 >= NumOps)
1207 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1208 (OpInfo[OpIdx+1].RegClass < 0) &&
1209 "Expect 1 reg operand followed by 1 imm operand");
1211 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1212 if (getIBit(insn) == 0) {
1213 MI.addOperand(MCOperand::CreateReg(0));
1215 // Disassemble the 12-bit immediate offset.
1216 unsigned Imm12 = slice(insn, 11, 0);
1217 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
1218 MI.addOperand(MCOperand::CreateImm(Offset));
1220 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1221 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1223 // Inst{6-5} encodes the shift opcode.
1224 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1225 // Inst{11-7} encodes the imm5 shift amount.
1226 unsigned ShImm = slice(insn, 11, 7);
1228 // A8.4.1. Possible rrx or shift amount of 32...
1229 getImmShiftSE(ShOp, ShImm);
1230 MI.addOperand(MCOperand::CreateImm(
1231 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
1238 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1239 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1240 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1243 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1244 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1245 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1248 static bool HasDualReg(unsigned Opcode) {
1252 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1253 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1258 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1259 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1261 const TargetInstrDesc &TID = ARMInsts[Opcode];
1262 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1263 const TargetOperandInfo *OpInfo = TID.OpInfo;
1264 if (!OpInfo) return false;
1266 unsigned &OpIdx = NumOpsAdded;
1270 assert(((!isStore && TID.getNumDefs() > 0) ||
1271 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1272 && "Invalid arguments");
1274 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1275 if (isPrePost && isStore) {
1276 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1277 "Reg operand expected");
1278 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1283 bool DualReg = HasDualReg(Opcode);
1285 // Disassemble the dst/src operand.
1286 if (OpIdx >= NumOps)
1289 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1290 "Reg operand expected");
1291 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1295 // Fill in LDRD and STRD's second operand.
1297 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1298 decodeRd(insn) + 1)));
1302 // After dst of a pre- and post-indexed load is the address base writeback.
1303 if (isPrePost && !isStore) {
1304 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1305 "Reg operand expected");
1306 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1311 // Disassemble the base operand.
1312 if (OpIdx >= NumOps)
1315 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1316 "Reg operand expected");
1317 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1318 && "Index mode or tied_to operand expected");
1319 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1323 // For reg/reg form, base reg is followed by +/- reg.
1324 // For immediate form, it is followed by +/- imm8.
1325 // See also ARMAddressingModes.h (Addressing Mode #3).
1326 if (OpIdx + 1 >= NumOps)
1329 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1330 (OpInfo[OpIdx+1].RegClass < 0) &&
1331 "Expect 1 reg operand followed by 1 imm operand");
1333 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1334 if (getAM3IBit(insn) == 1) {
1335 MI.addOperand(MCOperand::CreateReg(0));
1337 // Disassemble the 8-bit immediate offset.
1338 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1339 unsigned Imm4L = insn & 0xF;
1340 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1341 MI.addOperand(MCOperand::CreateImm(Offset));
1343 // Disassemble the offset reg (Rm).
1344 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1346 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1347 MI.addOperand(MCOperand::CreateImm(Offset));
1354 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1355 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1356 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1360 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1361 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1362 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1365 // The algorithm for disassembly of LdStMulFrm is different from others because
1366 // it explicitly populates the two predicate operands after operand 0 (the base)
1367 // and operand 1 (the AM4 mode imm). After operand 3, we need to populate the
1368 // reglist with each affected register encoded as an MCOperand.
1369 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1370 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1372 assert(NumOps >= 5 && "LdStMulFrm expects NumOps >= 5");
1374 unsigned &OpIdx = NumOpsAdded;
1378 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1380 // Writeback to base, if necessary.
1381 if (Opcode == ARM::LDM_UPD || Opcode == ARM::STM_UPD) {
1382 MI.addOperand(MCOperand::CreateReg(Base));
1386 MI.addOperand(MCOperand::CreateReg(Base));
1388 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1389 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
1391 // Handling the two predicate operands before the reglist.
1392 int64_t CondVal = insn >> ARMII::CondShift;
1393 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1394 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1398 // Fill the variadic part of reglist.
1399 unsigned RegListBits = insn & ((1 << 16) - 1);
1400 for (unsigned i = 0; i < 16; ++i) {
1401 if ((RegListBits >> i) & 1) {
1402 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1411 // LDREX, LDREXB, LDREXH: Rd Rn
1412 // LDREXD: Rd Rd+1 Rn
1413 // STREX, STREXB, STREXH: Rd Rm Rn
1414 // STREXD: Rd Rm Rm+1 Rn
1416 // SWP, SWPB: Rd Rm Rn
1417 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1418 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1420 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1421 if (!OpInfo) return false;
1423 unsigned &OpIdx = NumOpsAdded;
1428 && OpInfo[0].RegClass == ARM::GPRRegClassID
1429 && OpInfo[1].RegClass == ARM::GPRRegClassID
1430 && "Expect 2 reg operands");
1432 bool isStore = slice(insn, 20, 20) == 0;
1433 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1435 // Add the destination operand.
1436 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1440 // Store register Exclusive needs a source operand.
1442 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1447 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1448 decodeRm(insn)+1)));
1452 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1453 decodeRd(insn)+1)));
1457 // Finally add the pointer operand.
1458 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1465 // Misc. Arithmetic Instructions.
1467 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1468 // RBIT, REV, REV16, REVSH: Rd Rm
1469 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1470 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1472 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1473 unsigned &OpIdx = NumOpsAdded;
1478 && OpInfo[0].RegClass == ARM::GPRRegClassID
1479 && OpInfo[1].RegClass == ARM::GPRRegClassID
1480 && "Expect 2 reg operands");
1482 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1484 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1489 assert(NumOps >= 4 && "Expect >= 4 operands");
1490 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1495 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1499 // If there is still an operand info left which is an immediate operand, add
1500 // an additional imm5 LSL/ASR operand.
1501 if (ThreeReg && OpInfo[OpIdx].RegClass < 0
1502 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1503 // Extract the 5-bit immediate field Inst{11-7}.
1504 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1505 MI.addOperand(MCOperand::CreateImm(ShiftAmt));
1512 // Extend instructions.
1513 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1514 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1515 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1516 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1517 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1519 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1520 unsigned &OpIdx = NumOpsAdded;
1525 && OpInfo[0].RegClass == ARM::GPRRegClassID
1526 && OpInfo[1].RegClass == ARM::GPRRegClassID
1527 && "Expect 2 reg operands");
1529 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1531 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1536 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1541 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1545 // If there is still an operand info left which is an immediate operand, add
1546 // an additional rotate immediate operand.
1547 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1548 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1549 // Extract the 2-bit rotate field Inst{11-10}.
1550 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1551 // Rotation by 8, 16, or 24 bits.
1552 MI.addOperand(MCOperand::CreateImm(rot << 3));
1559 /////////////////////////////////////
1561 // Utility Functions For VFP //
1563 /////////////////////////////////////
1565 // Extract/Decode Dd/Sd:
1567 // SP => d = UInt(Vd:D)
1568 // DP => d = UInt(D:Vd)
1569 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1570 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1571 : (decodeRd(insn) | getDBit(insn) << 4);
1574 // Extract/Decode Dn/Sn:
1576 // SP => n = UInt(Vn:N)
1577 // DP => n = UInt(N:Vn)
1578 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1579 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1580 : (decodeRn(insn) | getNBit(insn) << 4);
1583 // Extract/Decode Dm/Sm:
1585 // SP => m = UInt(Vm:M)
1586 // DP => m = UInt(M:Vm)
1587 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1588 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1589 : (decodeRm(insn) | getMBit(insn) << 4);
1594 static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
1595 assert(N == 32 || N == 64);
1598 unsigned bit6 = slice(byte, 6, 6);
1600 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1602 Result |= 0x1f << 25;
1604 Result |= 0x1 << 30;
1606 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1607 (uint64_t)slice(byte, 5, 0) << 48;
1609 Result |= 0xffL << 54;
1611 Result |= 0x1L << 62;
1617 // VFP Unary Format Instructions:
1619 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1620 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1621 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1622 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1623 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1625 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1627 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1628 unsigned &OpIdx = NumOpsAdded;
1632 unsigned RegClass = OpInfo[OpIdx].RegClass;
1633 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1634 "Reg operand expected");
1635 bool isSP = (RegClass == ARM::SPRRegClassID);
1637 MI.addOperand(MCOperand::CreateReg(
1638 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1641 // Early return for compare with zero instructions.
1642 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1643 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1646 RegClass = OpInfo[OpIdx].RegClass;
1647 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1648 "Reg operand expected");
1649 isSP = (RegClass == ARM::SPRRegClassID);
1651 MI.addOperand(MCOperand::CreateReg(
1652 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1658 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1659 // Some of them have operand constraints which tie the first operand in the
1660 // InOperandList to that of the dst. As far as asm printing is concerned, this
1661 // tied_to operand is simply skipped.
1662 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1663 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1665 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1667 const TargetInstrDesc &TID = ARMInsts[Opcode];
1668 const TargetOperandInfo *OpInfo = TID.OpInfo;
1669 unsigned &OpIdx = NumOpsAdded;
1673 unsigned RegClass = OpInfo[OpIdx].RegClass;
1674 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1675 "Reg operand expected");
1676 bool isSP = (RegClass == ARM::SPRRegClassID);
1678 MI.addOperand(MCOperand::CreateReg(
1679 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1682 // Skip tied_to operand constraint.
1683 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1684 assert(NumOps >= 4 && "Expect >=4 operands");
1685 MI.addOperand(MCOperand::CreateReg(0));
1689 MI.addOperand(MCOperand::CreateReg(
1690 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1693 MI.addOperand(MCOperand::CreateReg(
1694 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1700 // A8.6.295 vcvt (floating-point <-> integer)
1701 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1702 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1704 // A8.6.297 vcvt (floating-point and fixed-point)
1705 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1706 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1707 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1709 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1711 const TargetInstrDesc &TID = ARMInsts[Opcode];
1712 const TargetOperandInfo *OpInfo = TID.OpInfo;
1713 if (!OpInfo) return false;
1715 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1716 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1717 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1721 assert(NumOps >= 3 && "Expect >= 3 operands");
1722 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1723 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1724 MI.addOperand(MCOperand::CreateReg(
1725 getRegisterEnum(B, RegClassID,
1726 decodeVFPRd(insn, SP))));
1728 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1729 "Tied to operand expected");
1730 MI.addOperand(MI.getOperand(0));
1732 assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() &&
1733 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1734 MI.addOperand(MCOperand::CreateImm(fbits));
1739 // The Rd (destination) and Rm (source) bits have different interpretations
1740 // depending on their single-precisonness.
1742 if (slice(insn, 18, 18) == 1) { // to_integer operation
1743 d = decodeVFPRd(insn, true /* Is Single Precision */);
1744 MI.addOperand(MCOperand::CreateReg(
1745 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1746 m = decodeVFPRm(insn, SP);
1747 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1749 d = decodeVFPRd(insn, SP);
1750 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1751 m = decodeVFPRm(insn, true /* Is Single Precision */);
1752 MI.addOperand(MCOperand::CreateReg(
1753 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1761 // VMOVRS - A8.6.330
1762 // Rt => Rd; Sn => UInt(Vn:N)
1763 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1764 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1766 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1768 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1770 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1771 decodeVFPRn(insn, true))));
1776 // VMOVRRD - A8.6.332
1777 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1779 // VMOVRRS - A8.6.331
1780 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1781 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1782 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1784 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1786 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1787 unsigned &OpIdx = NumOpsAdded;
1789 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1791 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1795 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1796 unsigned Sm = decodeVFPRm(insn, true);
1797 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1799 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1803 MI.addOperand(MCOperand::CreateReg(
1804 getRegisterEnum(B, ARM::DPRRegClassID,
1805 decodeVFPRm(insn, false))));
1811 // VMOVSR - A8.6.330
1812 // Rt => Rd; Sn => UInt(Vn:N)
1813 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1814 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1816 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1818 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1819 decodeVFPRn(insn, true))));
1820 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1826 // VMOVDRR - A8.6.332
1827 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1829 // VMOVRRS - A8.6.331
1830 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1831 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1832 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1834 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1836 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1837 unsigned &OpIdx = NumOpsAdded;
1841 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1842 unsigned Sm = decodeVFPRm(insn, true);
1843 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1845 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1849 MI.addOperand(MCOperand::CreateReg(
1850 getRegisterEnum(B, ARM::DPRRegClassID,
1851 decodeVFPRm(insn, false))));
1855 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1857 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1863 // VFP Load/Store Instructions.
1864 // VLDRD, VLDRS, VSTRD, VSTRS
1865 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1866 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1868 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1870 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS) ? true : false;
1871 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1873 // Extract Dd/Sd for operand 0.
1874 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1876 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1878 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1879 MI.addOperand(MCOperand::CreateReg(Base));
1881 // Next comes the AM5 Opcode.
1882 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1883 unsigned char Imm8 = insn & 0xFF;
1884 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1891 // VFP Load/Store Multiple Instructions.
1892 // This is similar to the algorithm for LDM/STM in that operand 0 (the base) and
1893 // operand 1 (the AM5 mode imm) is followed by two predicate operands. It is
1894 // followed by a reglist of either DPR(s) or SPR(s).
1896 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1897 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1898 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1900 assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
1902 unsigned &OpIdx = NumOpsAdded;
1906 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1908 // Writeback to base, if necessary.
1909 if (Opcode == ARM::VLDMD_UPD || Opcode == ARM::VLDMS_UPD ||
1910 Opcode == ARM::VSTMD_UPD || Opcode == ARM::VSTMS_UPD) {
1911 MI.addOperand(MCOperand::CreateReg(Base));
1915 MI.addOperand(MCOperand::CreateReg(Base));
1917 // Next comes the AM5 Opcode.
1918 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1919 // Must be either "ia" or "db" submode.
1920 if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) {
1921 DEBUG(errs() << "Illegal addressing mode 5 sub-mode!\n");
1925 unsigned char Imm8 = insn & 0xFF;
1926 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(SubMode, Imm8)));
1928 // Handling the two predicate operands before the reglist.
1929 int64_t CondVal = insn >> ARMII::CondShift;
1930 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1931 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1935 bool isSPVFP = (Opcode == ARM::VLDMS || Opcode == ARM::VLDMS_UPD ||
1936 Opcode == ARM::VSTMS || Opcode == ARM::VSTMS_UPD) ? true : false;
1937 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1940 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1942 // Fill the variadic part of reglist.
1943 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1944 for (unsigned i = 0; i < Regs; ++i) {
1945 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1953 // Misc. VFP Instructions.
1954 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1955 // FCONSTD (DPR and a VFPf64Imm operand)
1956 // FCONSTS (SPR and a VFPf32Imm operand)
1957 // VMRS/VMSR (GPR operand)
1958 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1959 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1961 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1962 unsigned &OpIdx = NumOpsAdded;
1966 if (Opcode == ARM::FMSTAT)
1969 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1971 unsigned RegEnum = 0;
1972 switch (OpInfo[0].RegClass) {
1973 case ARM::DPRRegClassID:
1974 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1976 case ARM::SPRRegClassID:
1977 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1979 case ARM::GPRRegClassID:
1980 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1983 assert(0 && "Invalid reg class id");
1987 MI.addOperand(MCOperand::CreateReg(RegEnum));
1990 // Extract/decode the f64/f32 immediate.
1991 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1992 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1993 // The asm syntax specifies the before-expanded <imm>.
1994 // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1995 // Opcode == ARM::FCONSTD ? 64 : 32)
1996 MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0)));
2003 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
2004 #include "ThumbDisassemblerCore.h"
2006 /////////////////////////////////////////////////////
2008 // Utility Functions For ARM Advanced SIMD //
2010 /////////////////////////////////////////////////////
2012 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
2013 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
2015 // A7.3 Register encoding
2017 // Extract/Decode NEON D/Vd:
2019 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
2020 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
2021 // handling it in the getRegisterEnum() utility function.
2022 // D = Inst{22}, Vd = Inst{15-12}
2023 static unsigned decodeNEONRd(uint32_t insn) {
2024 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
2025 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
2028 // Extract/Decode NEON N/Vn:
2030 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
2031 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
2032 // handling it in the getRegisterEnum() utility function.
2033 // N = Inst{7}, Vn = Inst{19-16}
2034 static unsigned decodeNEONRn(uint32_t insn) {
2035 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
2036 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
2039 // Extract/Decode NEON M/Vm:
2041 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
2042 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
2043 // handling it in the getRegisterEnum() utility function.
2044 // M = Inst{5}, Vm = Inst{3-0}
2045 static unsigned decodeNEONRm(uint32_t insn) {
2046 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
2047 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
2058 } // End of unnamed namespace
2060 // size field -> Inst{11-10}
2061 // index_align field -> Inst{7-4}
2063 // The Lane Index interpretation depends on the Data Size:
2064 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
2065 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
2066 // 32 (encoded as size = 0b10) -> Index = index_align[3]
2068 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
2069 static unsigned decodeLaneIndex(uint32_t insn) {
2070 unsigned size = insn >> 10 & 3;
2071 assert((size == 0 || size == 1 || size == 2) &&
2072 "Encoding error: size should be either 0, 1, or 2");
2074 unsigned index_align = insn >> 4 & 0xF;
2075 return (index_align >> 1) >> size;
2078 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
2079 // op = Inst{5}, cmode = Inst{11-8}
2080 // i = Inst{24} (ARM architecture)
2081 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
2082 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
2083 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
2084 unsigned char op = (insn >> 5) & 1;
2085 unsigned char cmode = (insn >> 8) & 0xF;
2086 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
2087 ((insn >> 16) & 7) << 4 |
2089 return (op << 12) | (cmode << 8) | Imm8;
2092 // A8.6.339 VMUL, VMULL (by scalar)
2093 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2094 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2095 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2102 assert(0 && "Unreachable code!");
2107 // A8.6.339 VMUL, VMULL (by scalar)
2108 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2109 // ESize32 => index = Inst{5} (M) D0-D15
2110 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2113 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2115 return (insn >> 5) & 1;
2117 assert(0 && "Unreachable code!");
2122 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2123 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2124 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2125 return 64 - ((insn >> 16) & 0x3F);
2128 // A8.6.302 VDUP (scalar)
2129 // ESize8 => index = Inst{19-17}
2130 // ESize16 => index = Inst{19-18}
2131 // ESize32 => index = Inst{19}
2132 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2135 return (insn >> 17) & 7;
2137 return (insn >> 18) & 3;
2139 return (insn >> 19) & 1;
2141 assert(0 && "Unspecified element size!");
2146 // A8.6.328 VMOV (ARM core register to scalar)
2147 // A8.6.329 VMOV (scalar to ARM core register)
2148 // ESize8 => index = Inst{21:6-5}
2149 // ESize16 => index = Inst{21:6}
2150 // ESize32 => index = Inst{21}
2151 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2154 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2156 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2158 return ((insn >> 21) & 1);
2160 assert(0 && "Unspecified element size!");
2165 // Imm6 = Inst{21-16}, L = Inst{7}
2167 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2169 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2170 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2171 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2172 // '1xxxxxx' => esize = 64; shift_amount = imm6
2174 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2176 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2177 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2178 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2179 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2181 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2182 ElemSize esize = ESizeNA;
2183 unsigned L = (insn >> 7) & 1;
2184 unsigned imm6 = (insn >> 16) & 0x3F;
2188 else if (imm6 >> 4 == 1)
2190 else if (imm6 >> 5 == 1)
2193 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2198 return esize == ESize64 ? imm6 : (imm6 - esize);
2200 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2204 // Imm4 = Inst{11-8}
2205 static unsigned decodeN3VImm(uint32_t insn) {
2206 return (insn >> 8) & 0xF;
2209 static bool UseDRegPair(unsigned Opcode) {
2213 case ARM::VLD1q8_UPD:
2214 case ARM::VLD1q16_UPD:
2215 case ARM::VLD1q32_UPD:
2216 case ARM::VLD1q64_UPD:
2217 case ARM::VST1q8_UPD:
2218 case ARM::VST1q16_UPD:
2219 case ARM::VST1q32_UPD:
2220 case ARM::VST1q64_UPD:
2226 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2228 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2230 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2232 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2234 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2235 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2236 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2239 const TargetInstrDesc &TID = ARMInsts[Opcode];
2240 const TargetOperandInfo *OpInfo = TID.OpInfo;
2242 // At least one DPR register plus addressing mode #6.
2243 assert(NumOps >= 3 && "Expect >= 3 operands");
2245 unsigned &OpIdx = NumOpsAdded;
2249 // We have homogeneous NEON registers for Load/Store.
2250 unsigned RegClass = 0;
2251 bool DRegPair = UseDRegPair(Opcode);
2253 // Double-spaced registers have increments of 2.
2254 unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1;
2256 unsigned Rn = decodeRn(insn);
2257 unsigned Rm = decodeRm(insn);
2258 unsigned Rd = decodeNEONRd(insn);
2260 // A7.7.1 Advanced SIMD addressing mode.
2263 // LLVM Addressing Mode #6.
2264 unsigned RmEnum = 0;
2266 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2269 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2270 // then possible lane index.
2271 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2272 "Reg operand expected");
2275 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2280 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2281 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2282 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2284 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2288 MI.addOperand(MCOperand::CreateReg(RmEnum));
2292 assert(OpIdx < NumOps &&
2293 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2294 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2295 "Reg operand expected");
2297 RegClass = OpInfo[OpIdx].RegClass;
2298 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2299 MI.addOperand(MCOperand::CreateReg(
2300 getRegisterEnum(B, RegClass, Rd, DRegPair)));
2305 // Handle possible lane index.
2306 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2307 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2308 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2313 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2314 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2315 RegClass = OpInfo[0].RegClass;
2317 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2318 MI.addOperand(MCOperand::CreateReg(
2319 getRegisterEnum(B, RegClass, Rd, DRegPair)));
2325 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2330 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2331 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2332 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2334 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2338 MI.addOperand(MCOperand::CreateReg(RmEnum));
2342 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2343 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2344 "Tied to operand expected");
2345 MI.addOperand(MCOperand::CreateReg(0));
2349 // Handle possible lane index.
2350 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2351 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2352 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2357 // Accessing registers past the end of the NEON register file is not
2366 // If L (Inst{21}) == 0, store instructions.
2367 // Find out about double-spaced-ness of the Opcode and pass it on to
2368 // DisassembleNLdSt0().
2369 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2370 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2372 const StringRef Name = ARMInsts[Opcode].Name;
2373 bool DblSpaced = false;
2375 if (Name.find("LN") != std::string::npos) {
2376 // To one lane instructions.
2377 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2379 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2380 if (Name.endswith("16") || Name.endswith("16_UPD"))
2381 DblSpaced = slice(insn, 5, 5) == 1;
2383 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2384 if (Name.endswith("32") || Name.endswith("32_UPD"))
2385 DblSpaced = slice(insn, 6, 6) == 1;
2388 // Multiple n-element structures with type encoded as Inst{11-8}.
2389 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2391 // n == 2 && type == 0b1001 -> DblSpaced = true
2392 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2393 DblSpaced = slice(insn, 11, 8) == 9;
2395 // n == 3 && type == 0b0101 -> DblSpaced = true
2396 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2397 DblSpaced = slice(insn, 11, 8) == 5;
2399 // n == 4 && type == 0b0001 -> DblSpaced = true
2400 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2401 DblSpaced = slice(insn, 11, 8) == 1;
2404 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2405 slice(insn, 21, 21) == 0, DblSpaced, B);
2410 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2411 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2413 const TargetInstrDesc &TID = ARMInsts[Opcode];
2414 const TargetOperandInfo *OpInfo = TID.OpInfo;
2416 assert(NumOps >= 2 &&
2417 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2418 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2419 (OpInfo[1].RegClass < 0) &&
2420 "Expect 1 reg operand followed by 1 imm operand");
2422 // Qd/Dd = Inst{22:15-12} => NEON Rd
2423 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2424 decodeNEONRd(insn))));
2426 ElemSize esize = ESizeNA;
2429 case ARM::VMOVv16i8:
2432 case ARM::VMOVv4i16:
2433 case ARM::VMOVv8i16:
2436 case ARM::VMOVv2i32:
2437 case ARM::VMOVv4i32:
2440 case ARM::VMOVv1i64:
2441 case ARM::VMOVv2i64:
2445 assert(0 && "Unreachable code!");
2449 // One register and a modified immediate value.
2450 // Add the imm operand.
2451 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2461 N2V_VectorConvert_Between_Float_Fixed
2463 } // End of unnamed namespace
2465 // Vector Convert [between floating-point and fixed-point]
2466 // Qd/Dd Qm/Dm [fbits]
2468 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2469 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2472 // Vector Move Long:
2475 // Vector Move Narrow:
2479 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2480 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2482 const TargetInstrDesc &TID = ARMInsts[Opc];
2483 const TargetOperandInfo *OpInfo = TID.OpInfo;
2485 assert(NumOps >= 2 &&
2486 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2487 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2488 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2489 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2490 "Expect >= 2 operands and first 2 as reg operands");
2492 unsigned &OpIdx = NumOpsAdded;
2496 ElemSize esize = ESizeNA;
2497 if (Flag == N2V_VectorDupLane) {
2498 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2499 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2500 "Unexpected Opcode");
2501 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2502 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2506 // Qd/Dd = Inst{22:15-12} => NEON Rd
2507 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2508 decodeNEONRd(insn))));
2512 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2514 MI.addOperand(MCOperand::CreateReg(0));
2518 // Dm = Inst{5:3-0} => NEON Rm
2519 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2520 decodeNEONRm(insn))));
2523 // VZIP and others have two TIED_TO reg operands.
2525 while (OpIdx < NumOps &&
2526 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2527 // Add TIED_TO operand.
2528 MI.addOperand(MI.getOperand(Idx));
2532 // Add the imm operand, if required.
2533 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2534 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2536 unsigned imm = 0xFFFFFFFF;
2538 if (Flag == N2V_VectorDupLane)
2539 imm = decodeNVLaneDupIndex(insn, esize);
2540 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2541 imm = decodeVCVTFractionBits(insn);
2543 assert(imm != 0xFFFFFFFF && "Internal error");
2544 MI.addOperand(MCOperand::CreateImm(imm));
2551 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2552 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2554 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2557 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2558 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2560 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2561 N2V_VectorConvert_Between_Float_Fixed, B);
2563 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2564 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2566 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2567 N2V_VectorDupLane, B);
2570 // Vector Shift [Accumulate] Instructions.
2571 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2573 // Vector Shift Left Long (with maximum shift count) Instructions.
2574 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2576 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2577 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2579 const TargetInstrDesc &TID = ARMInsts[Opcode];
2580 const TargetOperandInfo *OpInfo = TID.OpInfo;
2582 assert(NumOps >= 3 &&
2583 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2584 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2585 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2586 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2587 "Expect >= 3 operands and first 2 as reg operands");
2589 unsigned &OpIdx = NumOpsAdded;
2593 // Qd/Dd = Inst{22:15-12} => NEON Rd
2594 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2595 decodeNEONRd(insn))));
2598 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2600 MI.addOperand(MCOperand::CreateReg(0));
2604 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2605 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2606 "Reg operand expected");
2608 // Qm/Dm = Inst{5:3-0} => NEON Rm
2609 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2610 decodeNEONRm(insn))));
2613 assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
2615 // Add the imm operand.
2617 // VSHLL has maximum shift count as the imm, inferred from its size.
2621 Imm = decodeNVSAmt(insn, LeftShift);
2633 MI.addOperand(MCOperand::CreateImm(Imm));
2639 // Left shift instructions.
2640 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2641 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2643 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2646 // Right shift instructions have different shift amount interpretation.
2647 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2648 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2650 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2659 N3V_Multiply_By_Scalar
2661 } // End of unnamed namespace
2663 // NEON Three Register Instructions with Optional Immediate Operand
2665 // Vector Extract Instructions.
2666 // Qd/Dd Qn/Dn Qm/Dm imm4
2668 // Vector Shift (Register) Instructions.
2669 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2671 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2672 // Qd/Dd Qn/Dn RestrictedDm index
2675 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2676 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2678 const TargetInstrDesc &TID = ARMInsts[Opcode];
2679 const TargetOperandInfo *OpInfo = TID.OpInfo;
2681 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2682 assert(NumOps >= 3 &&
2683 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2684 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2685 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2686 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2687 "Expect >= 3 operands and first 2 as reg operands");
2689 unsigned &OpIdx = NumOpsAdded;
2693 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2694 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2695 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2696 ElemSize esize = ESizeNA;
2697 if (Flag == N3V_Multiply_By_Scalar) {
2698 unsigned size = (insn >> 20) & 3;
2699 if (size == 1) esize = ESize16;
2700 if (size == 2) esize = ESize32;
2701 assert (esize == ESize16 || esize == ESize32);
2704 // Qd/Dd = Inst{22:15-12} => NEON Rd
2705 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2706 decodeNEONRd(insn))));
2709 // VABA, VABAL, VBSLd, VBSLq, ...
2710 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2712 MI.addOperand(MCOperand::CreateReg(0));
2716 // Dn = Inst{7:19-16} => NEON Rn
2718 // Dm = Inst{5:3-0} => NEON Rm
2719 MI.addOperand(MCOperand::CreateReg(
2720 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2721 VdVnVm ? decodeNEONRn(insn)
2722 : decodeNEONRm(insn))));
2725 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2727 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2730 // Dm = Inst{5:3-0} => NEON Rm
2732 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2734 // Dn = Inst{7:19-16} => NEON Rn
2735 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2736 : decodeNEONRm(insn))
2737 : decodeNEONRn(insn);
2739 MI.addOperand(MCOperand::CreateReg(
2740 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2743 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2744 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2745 // Add the imm operand.
2748 Imm = decodeN3VImm(insn);
2749 else if (IsDmRestricted)
2750 Imm = decodeRestrictedDmIndex(insn, esize);
2752 assert(0 && "Internal error: unreachable code!");
2756 MI.addOperand(MCOperand::CreateImm(Imm));
2763 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2764 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2766 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2769 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2770 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2772 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2773 N3V_VectorShift, B);
2775 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2776 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2778 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2779 N3V_VectorExtract, B);
2781 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2782 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2784 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2785 N3V_Multiply_By_Scalar, B);
2788 // Vector Table Lookup
2790 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2791 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2792 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2793 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2794 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2795 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2797 const TargetInstrDesc &TID = ARMInsts[Opcode];
2798 const TargetOperandInfo *OpInfo = TID.OpInfo;
2799 if (!OpInfo) return false;
2801 assert(NumOps >= 3 &&
2802 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2803 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2804 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2805 "Expect >= 3 operands and first 3 as reg operands");
2807 unsigned &OpIdx = NumOpsAdded;
2811 unsigned Rn = decodeNEONRn(insn);
2813 // {Dn} encoded as len = 0b00
2814 // {Dn Dn+1} encoded as len = 0b01
2815 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2816 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2817 unsigned Len = slice(insn, 9, 8) + 1;
2819 // Dd (the destination vector)
2820 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2821 decodeNEONRd(insn))));
2824 // Process tied_to operand constraint.
2826 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2827 MI.addOperand(MI.getOperand(Idx));
2831 // Do the <list> now.
2832 for (unsigned i = 0; i < Len; ++i) {
2833 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2834 "Reg operand expected");
2835 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2840 // Dm (the index vector)
2841 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2842 "Reg operand (index vector) expected");
2843 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2844 decodeNEONRm(insn))));
2850 // Vector Get Lane (move scalar to ARM core register) Instructions.
2851 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2852 static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2853 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2855 const TargetInstrDesc &TID = ARMInsts[Opcode];
2856 const TargetOperandInfo *OpInfo = TID.OpInfo;
2857 if (!OpInfo) return false;
2859 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2860 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2861 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2862 OpInfo[2].RegClass < 0 &&
2863 "Expect >= 3 operands with one dst operand");
2866 Opcode == ARM::VGETLNi32 ? ESize32
2867 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2870 // Rt = Inst{15-12} => ARM Rd
2871 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2874 // Dn = Inst{7:19-16} => NEON Rn
2875 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2876 decodeNEONRn(insn))));
2878 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2884 // Vector Set Lane (move ARM core register to scalar) Instructions.
2885 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2886 static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2887 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2889 const TargetInstrDesc &TID = ARMInsts[Opcode];
2890 const TargetOperandInfo *OpInfo = TID.OpInfo;
2891 if (!OpInfo) return false;
2893 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2894 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2895 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2896 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2897 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2898 OpInfo[3].RegClass < 0 &&
2899 "Expect >= 3 operands with one dst operand");
2902 Opcode == ARM::VSETLNi8 ? ESize8
2903 : (Opcode == ARM::VSETLNi16 ? ESize16
2906 // Dd = Inst{7:19-16} => NEON Rn
2907 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2908 decodeNEONRn(insn))));
2911 MI.addOperand(MCOperand::CreateReg(0));
2913 // Rt = Inst{15-12} => ARM Rd
2914 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2917 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2923 // Vector Duplicate Instructions (from ARM core register to all elements).
2924 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2925 static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2926 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2928 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2930 assert(NumOps >= 2 &&
2931 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2932 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2933 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2934 "Expect >= 2 operands and first 2 as reg operand");
2936 unsigned RegClass = OpInfo[0].RegClass;
2938 // Qd/Dd = Inst{7:19-16} => NEON Rn
2939 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2940 decodeNEONRn(insn))));
2942 // Rt = Inst{15-12} => ARM Rd
2943 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2953 static inline bool MemBarrierInstr(uint32_t insn) {
2954 unsigned op7_4 = slice(insn, 7, 4);
2955 if (slice(insn, 31, 20) == 0xf57 && (op7_4 >= 4 && op7_4 <= 6))
2961 static inline bool PreLoadOpcode(unsigned Opcode) {
2963 case ARM::PLDi: case ARM::PLDr:
2964 case ARM::PLDWi: case ARM::PLDWr:
2965 case ARM::PLIi: case ARM::PLIr:
2972 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2973 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2975 // Preload Data/Instruction requires either 2 or 4 operands.
2976 // PLDi, PLDWi, PLIi: Rn [+/-]imm12 add = (U == '1')
2977 // PLDr[a|m], PLDWr[a|m], PLIr[a|m]: Rn Rm addrmode2_opc
2979 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2982 if (Opcode == ARM::PLDi || Opcode == ARM::PLDWi || Opcode == ARM::PLIi) {
2983 unsigned Imm12 = slice(insn, 11, 0);
2984 bool Negative = getUBit(insn) == 0;
2985 int Offset = Negative ? -1 - Imm12 : 1 * Imm12;
2986 MI.addOperand(MCOperand::CreateImm(Offset));
2989 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2992 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
2994 // Inst{6-5} encodes the shift opcode.
2995 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
2996 // Inst{11-7} encodes the imm5 shift amount.
2997 unsigned ShImm = slice(insn, 11, 7);
2999 // A8.4.1. Possible rrx or shift amount of 32...
3000 getImmShiftSE(ShOp, ShImm);
3001 MI.addOperand(MCOperand::CreateImm(
3002 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
3009 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
3010 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
3012 if (MemBarrierInstr(insn))
3030 // CPS has a singleton $opt operand that contains the following information:
3031 // opt{4-0} = mode from Inst{4-0}
3032 // opt{5} = changemode from Inst{17}
3033 // opt{8-6} = AIF from Inst{8-6}
3034 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3035 if (Opcode == ARM::CPS) {
3036 unsigned Option = slice(insn, 4, 0) | slice(insn, 17, 17) << 5 |
3037 slice(insn, 8, 6) << 6 | slice(insn, 19, 18) << 9;
3038 MI.addOperand(MCOperand::CreateImm(Option));
3043 // DBG has its option specified in Inst{3-0}.
3044 if (Opcode == ARM::DBG) {
3045 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3050 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
3051 if (Opcode == ARM::BKPT) {
3052 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
3053 slice(insn, 3, 0)));
3058 if (PreLoadOpcode(Opcode))
3059 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
3061 assert(0 && "Unexpected misc instruction!");
3065 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
3066 /// We divide the disassembly task into different categories, with each one
3067 /// corresponding to a specific instruction encoding format. There could be
3068 /// exceptions when handling a specific format, and that is why the Opcode is
3069 /// also present in the function prototype.
3070 static const DisassembleFP FuncPtrs[] = {
3074 &DisassembleBrMiscFrm,
3076 &DisassembleDPSoRegFrm,
3079 &DisassembleLdMiscFrm,
3080 &DisassembleStMiscFrm,
3081 &DisassembleLdStMulFrm,
3082 &DisassembleLdStExFrm,
3083 &DisassembleArithMiscFrm,
3085 &DisassembleVFPUnaryFrm,
3086 &DisassembleVFPBinaryFrm,
3087 &DisassembleVFPConv1Frm,
3088 &DisassembleVFPConv2Frm,
3089 &DisassembleVFPConv3Frm,
3090 &DisassembleVFPConv4Frm,
3091 &DisassembleVFPConv5Frm,
3092 &DisassembleVFPLdStFrm,
3093 &DisassembleVFPLdStMulFrm,
3094 &DisassembleVFPMiscFrm,
3095 &DisassembleThumbFrm,
3096 &DisassembleMiscFrm,
3097 &DisassembleNGetLnFrm,
3098 &DisassembleNSetLnFrm,
3099 &DisassembleNDupFrm,
3101 // VLD and VST (including one lane) Instructions.
3104 // A7.4.6 One register and a modified immediate value
3105 // 1-Register Instructions with imm.
3106 // LLVM only defines VMOVv instructions.
3107 &DisassembleN1RegModImmFrm,
3109 // 2-Register Instructions with no imm.
3110 &DisassembleN2RegFrm,
3112 // 2-Register Instructions with imm (vector convert float/fixed point).
3113 &DisassembleNVCVTFrm,
3115 // 2-Register Instructions with imm (vector dup lane).
3116 &DisassembleNVecDupLnFrm,
3118 // Vector Shift Left Instructions.
3119 &DisassembleN2RegVecShLFrm,
3121 // Vector Shift Righ Instructions, which has different interpretation of the
3122 // shift amount from the imm6 field.
3123 &DisassembleN2RegVecShRFrm,
3125 // 3-Register Data-Processing Instructions.
3126 &DisassembleN3RegFrm,
3128 // Vector Shift (Register) Instructions.
3129 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3130 &DisassembleN3RegVecShFrm,
3132 // Vector Extract Instructions.
3133 &DisassembleNVecExtractFrm,
3135 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3136 // By Scalar Instructions.
3137 &DisassembleNVecMulScalarFrm,
3139 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3140 // values in a table and generate a new vector.
3141 &DisassembleNVTBLFrm,
3146 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3147 /// The general idea is to set the Opcode for the MCInst, followed by adding
3148 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3149 /// to the Format-specific disassemble function for disassembly, followed by
3150 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3151 /// which follow the Dst/Src Operands.
3152 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3153 // Stage 1 sets the Opcode.
3154 MI.setOpcode(Opcode);
3155 // If the number of operands is zero, we're done!
3159 // Stage 2 calls the format-specific disassemble function to build the operand
3163 unsigned NumOpsAdded = 0;
3164 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3166 if (!OK || this->Err != 0) return false;
3167 if (NumOpsAdded >= NumOps)
3170 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3171 // FIXME: Should this be done selectively?
3172 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3175 // A8.3 Conditional execution
3176 // A8.3.1 Pseudocode details of conditional execution
3177 // Condition bits '111x' indicate the instruction is always executed.
3178 static uint32_t CondCode(uint32_t CondField) {
3179 if (CondField == 0xF)
3184 /// DoPredicateOperands - DoPredicateOperands process the predicate operands
3185 /// of some Thumb instructions which come before the reglist operands. It
3186 /// returns true if the two predicate operands have been processed.
3187 bool ARMBasicMCBuilder::DoPredicateOperands(MCInst& MI, unsigned Opcode,
3188 uint32_t /* insn */, unsigned short NumOpsRemaining) {
3190 assert(NumOpsRemaining > 0 && "Invalid argument");
3192 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3193 unsigned Idx = MI.getNumOperands();
3195 // First, we check whether this instr specifies the PredicateOperand through
3196 // a pair of TargetOperandInfos with isPredicate() property.
3197 if (NumOpsRemaining >= 2 &&
3198 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3199 OpInfo[Idx].RegClass < 0 &&
3200 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3202 // If we are inside an IT block, get the IT condition bits maintained via
3203 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3206 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3208 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3209 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3216 /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
3217 /// the possible Predicate and SBitModifier, to build the remaining MCOperand
3219 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3220 uint32_t insn, unsigned short NumOpsRemaining) {
3222 assert(NumOpsRemaining > 0 && "Invalid argument");
3224 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3225 const std::string &Name = ARMInsts[Opcode].Name;
3226 unsigned Idx = MI.getNumOperands();
3228 // First, we check whether this instr specifies the PredicateOperand through
3229 // a pair of TargetOperandInfos with isPredicate() property.
3230 if (NumOpsRemaining >= 2 &&
3231 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3232 OpInfo[Idx].RegClass < 0 &&
3233 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3235 // If we are inside an IT block, get the IT condition bits maintained via
3236 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3239 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3241 if (Name.length() > 1 && Name[0] == 't') {
3242 // Thumb conditional branch instructions have their cond field embedded,
3246 if (Name == "t2Bcc")
3247 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22))));
3248 else if (Name == "tBcc")
3249 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8))));
3251 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3253 // ARM instructions get their condition field from Inst{31-28}.
3254 MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
3257 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3259 NumOpsRemaining -= 2;
3262 if (NumOpsRemaining == 0)
3265 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3266 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3267 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3271 if (NumOpsRemaining == 0)
3277 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3278 /// after BuildIt is finished.
3279 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3282 if (!SP) return Status;
3284 if (Opcode == ARM::t2IT)
3285 Status = SP->InitIT(slice(insn, 7, 0)) ? Status : false;
3286 else if (InITBlock())
3292 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3293 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3295 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3296 unsigned Idx = (unsigned)format;
3297 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3298 Disasm = FuncPtrs[Idx];
3301 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3302 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3303 /// Return NULL if it fails to create/return a proper builder. API clients
3304 /// are responsible for freeing up of the allocated memory. Cacheing can be
3305 /// performed by the API clients to improve performance.
3306 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3307 // For "Unknown format", fail by returning a NULL pointer.
3308 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1)) {
3309 DEBUG(errs() << "Unknown format\n");
3313 return new ARMBasicMCBuilder(Opcode, Format,
3314 ARMInsts[Opcode].getNumOperands());