1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassemblerCore.h"
19 #include "ARMAddressingModes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
23 //#define DEBUG(X) do { X; } while (0)
25 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
26 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
27 /// describing the operand info for each ARMInsts[i].
29 /// Together with an instruction's encoding format, we can take advantage of the
30 /// NumOperands and the OpInfo fields of the target instruction description in
31 /// the quest to build out the MCOperand list for an MCInst.
33 /// The general guideline is that with a known format, the number of dst and src
34 /// operands are well-known. The dst is built first, followed by the src
35 /// operand(s). The operands not yet used at this point are for the Implicit
36 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
37 /// defined with two components:
39 /// def pred { // Operand PredicateOperand
40 /// ValueType Type = OtherVT;
41 /// string PrintMethod = "printPredicateOperand";
42 /// string AsmOperandLowerMethod = ?;
43 /// dag MIOperandInfo = (ops i32imm, CCR);
44 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
45 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
48 /// which is manifested by the TargetOperandInfo[] of:
50 /// { 0, 0|(1<<TOI::Predicate), 0 },
51 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
53 /// So the first predicate MCOperand corresponds to the immediate part of the
54 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
55 /// corresponds to a register kind of ARM::CPSR.
57 /// For the Defs part, in the simple case of only cc_out:$s, we have:
59 /// def cc_out { // Operand OptionalDefOperand
60 /// ValueType Type = OtherVT;
61 /// string PrintMethod = "printSBitModifierOperand";
62 /// string AsmOperandLowerMethod = ?;
63 /// dag MIOperandInfo = (ops CCR);
64 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
65 /// dag DefaultOps = (ops (i32 zero_reg));
68 /// which is manifested by the one TargetOperandInfo of:
70 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
72 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
73 #include "ARMGenInstrInfo.inc"
77 const char *ARMUtils::OpcodeName(unsigned Opcode) {
78 return ARMInsts[Opcode].Name;
81 // Return the register enum Based on RegClass and the raw register number.
84 getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
85 // For this purpose, we can treat rGPR as if it were GPR.
86 if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
88 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
90 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
97 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
98 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
99 case ARM::DPR_VFP2RegClassID:
101 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
102 case ARM::QPR_VFP2RegClassID:
104 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
108 switch (RegClassID) {
109 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
110 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
111 case ARM::DPR_VFP2RegClassID:
113 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
114 case ARM::QPR_VFP2RegClassID:
116 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
120 switch (RegClassID) {
121 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
122 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
123 case ARM::DPR_VFP2RegClassID:
125 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
126 case ARM::QPR_VFP2RegClassID:
128 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
132 switch (RegClassID) {
133 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
134 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
135 case ARM::DPR_VFP2RegClassID:
137 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
138 case ARM::QPR_VFP2RegClassID:
140 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
144 switch (RegClassID) {
145 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
146 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
147 case ARM::DPR_VFP2RegClassID:
149 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
150 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
154 switch (RegClassID) {
155 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
156 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
157 case ARM::DPR_VFP2RegClassID:
159 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
160 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
164 switch (RegClassID) {
165 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
166 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
167 case ARM::DPR_VFP2RegClassID:
169 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
170 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
174 switch (RegClassID) {
175 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
176 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
177 case ARM::DPR_VFP2RegClassID:
179 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
180 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
184 switch (RegClassID) {
185 case ARM::GPRRegClassID: return ARM::R8;
186 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
187 case ARM::QPRRegClassID: return ARM::Q8;
188 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
192 switch (RegClassID) {
193 case ARM::GPRRegClassID: return ARM::R9;
194 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
195 case ARM::QPRRegClassID: return ARM::Q9;
196 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
200 switch (RegClassID) {
201 case ARM::GPRRegClassID: return ARM::R10;
202 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
203 case ARM::QPRRegClassID: return ARM::Q10;
204 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
208 switch (RegClassID) {
209 case ARM::GPRRegClassID: return ARM::R11;
210 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
211 case ARM::QPRRegClassID: return ARM::Q11;
212 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
216 switch (RegClassID) {
217 case ARM::GPRRegClassID: return ARM::R12;
218 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
219 case ARM::QPRRegClassID: return ARM::Q12;
220 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
224 switch (RegClassID) {
225 case ARM::GPRRegClassID: return ARM::SP;
226 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
227 case ARM::QPRRegClassID: return ARM::Q13;
228 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
232 switch (RegClassID) {
233 case ARM::GPRRegClassID: return ARM::LR;
234 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
235 case ARM::QPRRegClassID: return ARM::Q14;
236 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
240 switch (RegClassID) {
241 case ARM::GPRRegClassID: return ARM::PC;
242 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
243 case ARM::QPRRegClassID: return ARM::Q15;
244 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
248 switch (RegClassID) {
249 case ARM::DPRRegClassID: return ARM::D16;
250 case ARM::SPRRegClassID: return ARM::S16;
254 switch (RegClassID) {
255 case ARM::DPRRegClassID: return ARM::D17;
256 case ARM::SPRRegClassID: return ARM::S17;
260 switch (RegClassID) {
261 case ARM::DPRRegClassID: return ARM::D18;
262 case ARM::SPRRegClassID: return ARM::S18;
266 switch (RegClassID) {
267 case ARM::DPRRegClassID: return ARM::D19;
268 case ARM::SPRRegClassID: return ARM::S19;
272 switch (RegClassID) {
273 case ARM::DPRRegClassID: return ARM::D20;
274 case ARM::SPRRegClassID: return ARM::S20;
278 switch (RegClassID) {
279 case ARM::DPRRegClassID: return ARM::D21;
280 case ARM::SPRRegClassID: return ARM::S21;
284 switch (RegClassID) {
285 case ARM::DPRRegClassID: return ARM::D22;
286 case ARM::SPRRegClassID: return ARM::S22;
290 switch (RegClassID) {
291 case ARM::DPRRegClassID: return ARM::D23;
292 case ARM::SPRRegClassID: return ARM::S23;
296 switch (RegClassID) {
297 case ARM::DPRRegClassID: return ARM::D24;
298 case ARM::SPRRegClassID: return ARM::S24;
302 switch (RegClassID) {
303 case ARM::DPRRegClassID: return ARM::D25;
304 case ARM::SPRRegClassID: return ARM::S25;
308 switch (RegClassID) {
309 case ARM::DPRRegClassID: return ARM::D26;
310 case ARM::SPRRegClassID: return ARM::S26;
314 switch (RegClassID) {
315 case ARM::DPRRegClassID: return ARM::D27;
316 case ARM::SPRRegClassID: return ARM::S27;
320 switch (RegClassID) {
321 case ARM::DPRRegClassID: return ARM::D28;
322 case ARM::SPRRegClassID: return ARM::S28;
326 switch (RegClassID) {
327 case ARM::DPRRegClassID: return ARM::D29;
328 case ARM::SPRRegClassID: return ARM::S29;
332 switch (RegClassID) {
333 case ARM::DPRRegClassID: return ARM::D30;
334 case ARM::SPRRegClassID: return ARM::S30;
338 switch (RegClassID) {
339 case ARM::DPRRegClassID: return ARM::D31;
340 case ARM::SPRRegClassID: return ARM::S31;
344 DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
345 // Encoding error. Mark the builder with error code != 0.
350 ///////////////////////////////
352 // Utility Functions //
354 ///////////////////////////////
356 // Extract/Decode Rd: Inst{15-12}.
357 static inline unsigned decodeRd(uint32_t insn) {
358 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
361 // Extract/Decode Rn: Inst{19-16}.
362 static inline unsigned decodeRn(uint32_t insn) {
363 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
366 // Extract/Decode Rm: Inst{3-0}.
367 static inline unsigned decodeRm(uint32_t insn) {
368 return (insn & ARMII::GPRRegMask);
371 // Extract/Decode Rs: Inst{11-8}.
372 static inline unsigned decodeRs(uint32_t insn) {
373 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
376 static inline unsigned getCondField(uint32_t insn) {
377 return (insn >> ARMII::CondShift);
380 static inline unsigned getIBit(uint32_t insn) {
381 return (insn >> ARMII::I_BitShift) & 1;
384 static inline unsigned getAM3IBit(uint32_t insn) {
385 return (insn >> ARMII::AM3_I_BitShift) & 1;
388 static inline unsigned getPBit(uint32_t insn) {
389 return (insn >> ARMII::P_BitShift) & 1;
392 static inline unsigned getUBit(uint32_t insn) {
393 return (insn >> ARMII::U_BitShift) & 1;
396 static inline unsigned getPUBits(uint32_t insn) {
397 return (insn >> ARMII::U_BitShift) & 3;
400 static inline unsigned getSBit(uint32_t insn) {
401 return (insn >> ARMII::S_BitShift) & 1;
404 static inline unsigned getWBit(uint32_t insn) {
405 return (insn >> ARMII::W_BitShift) & 1;
408 static inline unsigned getDBit(uint32_t insn) {
409 return (insn >> ARMII::D_BitShift) & 1;
412 static inline unsigned getNBit(uint32_t insn) {
413 return (insn >> ARMII::N_BitShift) & 1;
416 static inline unsigned getMBit(uint32_t insn) {
417 return (insn >> ARMII::M_BitShift) & 1;
420 // See A8.4 Shifts applied to a register.
421 // A8.4.2 Register controlled shifts.
423 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
424 // into llvm enums for shift opcode. The API clients should pass in the value
425 // encoded with two bits, so the assert stays to signal a wrong API usage.
427 // A8-12: DecodeRegShift()
428 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
430 default: assert(0 && "No such value"); return ARM_AM::no_shift;
431 case 0: return ARM_AM::lsl;
432 case 1: return ARM_AM::lsr;
433 case 2: return ARM_AM::asr;
434 case 3: return ARM_AM::ror;
438 // See A8.4 Shifts applied to a register.
439 // A8.4.1 Constant shifts.
441 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
442 // encodings into the intended ShiftOpc and shift amount.
444 // A8-11: DecodeImmShift()
445 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
449 case ARM_AM::no_shift:
453 ShOp = ARM_AM::no_shift;
465 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
466 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
467 // clients should pass in the value encoded with two bits, so the assert stays
468 // to signal a wrong API usage.
469 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
471 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
472 case 1: return ARM_AM::ia; // P=0 U=1
473 case 3: return ARM_AM::ib; // P=1 U=1
474 case 0: return ARM_AM::da; // P=0 U=0
475 case 2: return ARM_AM::db; // P=1 U=0
479 ////////////////////////////////////////////
481 // Disassemble function definitions //
483 ////////////////////////////////////////////
485 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
486 /// instr into a list of MCOperands in the appropriate order, with possible dst,
487 /// followed by possible src(s).
489 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
490 /// the CPSR, is factored into ARMBasicMCBuilder's method named
491 /// TryPredicateAndSBitModifier.
493 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
494 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
496 assert(0 && "Unexpected pseudo instruction!");
500 // Multiply Instructions.
501 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
502 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
504 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
505 // Rd{19-16} Rn{3-0} Rm{11-8}
507 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
508 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
510 // The mapping of the multiply registers to the "regular" ARM registers, where
511 // there are convenience decoder functions, is:
517 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
518 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
520 const TargetInstrDesc &TID = ARMInsts[Opcode];
521 unsigned short NumDefs = TID.getNumDefs();
522 const TargetOperandInfo *OpInfo = TID.OpInfo;
523 unsigned &OpIdx = NumOpsAdded;
527 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
529 && OpInfo[0].RegClass == ARM::GPRRegClassID
530 && OpInfo[1].RegClass == ARM::GPRRegClassID
531 && OpInfo[2].RegClass == ARM::GPRRegClassID
532 && "Expect three register operands");
534 // Instructions with two destination registers have RdLo{15-12} first.
536 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
537 "Expect 4th register operand");
538 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
543 // The destination register: RdHi{19-16} or Rd{19-16}.
544 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
547 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
548 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
550 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
554 // Many multiply instructions (e.g., MLA) have three src registers.
555 // The third register operand is Ra{15-12}.
556 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
557 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
565 // Helper routines for disassembly of coprocessor instructions.
567 static bool LdStCopOpcode(unsigned Opcode) {
568 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
569 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
573 static bool CoprocessorOpcode(unsigned Opcode) {
574 if (LdStCopOpcode(Opcode))
580 case ARM::CDP: case ARM::CDP2:
581 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
582 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
586 static inline unsigned GetCoprocessor(uint32_t insn) {
587 return slice(insn, 11, 8);
589 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
590 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
592 static inline unsigned GetCopOpc2(uint32_t insn) {
593 return slice(insn, 7, 5);
595 static inline unsigned GetCopOpc(uint32_t insn) {
596 return slice(insn, 7, 4);
598 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
601 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
603 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
605 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
607 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
609 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
613 // LDC_OPTION: cop CRd Rn imm8
615 // STC_OPTION: cop CRd Rn imm8
618 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
619 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
621 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
623 unsigned &OpIdx = NumOpsAdded;
624 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
625 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
626 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
627 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
628 bool LdStCop = LdStCopOpcode(Opcode);
632 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
635 // Unindex if P:W = 0b00 --> _OPTION variant
636 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
638 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
640 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
644 MI.addOperand(MCOperand::CreateReg(0));
645 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
646 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
648 MI.addOperand(MCOperand::CreateImm(Offset));
651 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
655 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
656 : GetCopOpc1(insn, NoGPR)));
658 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
659 : MCOperand::CreateReg(
660 getRegisterEnum(B, ARM::GPRRegClassID,
663 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
664 getRegisterEnum(B, ARM::GPRRegClassID,
666 : MCOperand::CreateImm(decodeRn(insn)));
668 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
673 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
681 // Branch Instructions.
682 // BL: SignExtend(Imm24:'00', 32)
683 // Bcc, BL_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
684 // SMC: ZeroExtend(imm4, 32)
685 // SVC: ZeroExtend(Imm24, 32)
687 // Various coprocessor instructions are assigned BrFrm arbitrarily.
688 // Delegates to DisassembleCoprocessor() helper function.
691 // MSR/MSRsys: Rm mask=Inst{19-16}
693 // MSRi/MSRsysi: so_imm
694 // SRSW/SRS: ldstm_mode:$amode mode_imm
695 // RFEW/RFE: ldstm_mode:$amode Rn
696 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
697 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
699 if (CoprocessorOpcode(Opcode))
700 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
702 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
703 if (!OpInfo) return false;
705 // MRS and MRSsys take one GPR reg Rd.
706 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
707 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
708 "Reg operand expected");
709 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
714 // BXJ takes one GPR reg Rm.
715 if (Opcode == ARM::BXJ) {
716 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
717 "Reg operand expected");
718 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
723 // MSR take a mask, followed by one GPR reg Rm. The mask contains the R Bit in
724 // bit 4, and the special register fields in bits 3-0.
725 if (Opcode == ARM::MSR) {
726 assert(NumOps >= 1 && OpInfo[1].RegClass == ARM::GPRRegClassID &&
727 "Reg operand expected");
728 MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
729 slice(insn, 19, 16) /* Special Reg */ ));
730 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
735 // MSRi take a mask, followed by one so_imm operand. The mask contains the
736 // R Bit in bit 4, and the special register fields in bits 3-0.
737 if (Opcode == ARM::MSRi) {
738 MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
739 slice(insn, 19, 16) /* Special Reg */ ));
740 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
741 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
742 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
743 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
744 unsigned Imm = insn & 0xFF;
745 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
749 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
750 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
751 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
752 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
754 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
755 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
757 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
763 assert((Opcode == ARM::Bcc || Opcode == ARM::BL || Opcode == ARM::BL_pred
764 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
765 "Unexpected Opcode");
767 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected");
770 if (Opcode == ARM::SMC) {
771 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
772 Imm32 = slice(insn, 3, 0);
773 } else if (Opcode == ARM::SVC) {
774 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
775 Imm32 = slice(insn, 23, 0);
777 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
778 unsigned Imm26 = slice(insn, 23, 0) << 2;
779 //Imm32 = signextend<signed int, 26>(Imm26);
780 Imm32 = SignExtend32<26>(Imm26);
783 MI.addOperand(MCOperand::CreateImm(Imm32));
789 // Misc. Branch Instructions.
792 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
793 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
795 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
796 if (!OpInfo) return false;
798 unsigned &OpIdx = NumOpsAdded;
802 // BX_RET and MOVPCLR have only two predicate operands; do an early return.
803 if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR)
806 // BLX and BX take one GPR reg.
807 if (Opcode == ARM::BLX || Opcode == ARM::BLX_pred ||
809 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
810 "Reg operand expected");
811 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
820 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
821 uint32_t lsb = slice(insn, 11, 7);
822 uint32_t msb = slice(insn, 20, 16);
825 DEBUG(errs() << "Encoding error: msb < lsb\n");
829 for (uint32_t i = lsb; i <= msb; ++i)
835 // A major complication is the fact that some of the saturating add/subtract
836 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
837 // They are QADD, QDADD, QDSUB, and QSUB.
838 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
839 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
841 const TargetInstrDesc &TID = ARMInsts[Opcode];
842 unsigned short NumDefs = TID.getNumDefs();
843 bool isUnary = isUnaryDP(TID.TSFlags);
844 const TargetOperandInfo *OpInfo = TID.OpInfo;
845 unsigned &OpIdx = NumOpsAdded;
849 // Disassemble register def if there is one.
850 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
851 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
856 // Now disassemble the src operands.
860 // Special-case handling of BFC/BFI/SBFX/UBFX.
861 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
862 MI.addOperand(MCOperand::CreateReg(0));
863 if (Opcode == ARM::BFI) {
864 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
869 if (!getBFCInvMask(insn, mask))
872 MI.addOperand(MCOperand::CreateImm(mask));
876 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
877 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
879 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
880 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
885 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
886 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
888 // BinaryDP has an Rn operand.
890 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
891 "Reg operand expected");
892 MI.addOperand(MCOperand::CreateReg(
893 getRegisterEnum(B, ARM::GPRRegClassID,
894 RmRn ? decodeRm(insn) : decodeRn(insn))));
898 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
899 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
900 MI.addOperand(MCOperand::CreateReg(0));
904 // Now disassemble operand 2.
908 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
909 // We have a reg/reg form.
910 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
911 // routed here as well.
912 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
913 MI.addOperand(MCOperand::CreateReg(
914 getRegisterEnum(B, ARM::GPRRegClassID,
915 RmRn? decodeRn(insn) : decodeRm(insn))));
917 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
918 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
919 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
920 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
921 MI.addOperand(MCOperand::CreateImm(Imm16));
924 // We have a reg/imm form.
925 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
926 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
927 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
928 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
929 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
930 unsigned Imm = insn & 0xFF;
931 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
938 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
939 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
941 const TargetInstrDesc &TID = ARMInsts[Opcode];
942 unsigned short NumDefs = TID.getNumDefs();
943 bool isUnary = isUnaryDP(TID.TSFlags);
944 const TargetOperandInfo *OpInfo = TID.OpInfo;
945 unsigned &OpIdx = NumOpsAdded;
949 // Disassemble register def if there is one.
950 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
951 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
956 // Disassemble the src operands.
960 // BinaryDP has an Rn operand.
962 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
963 "Reg operand expected");
964 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
969 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
970 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
971 MI.addOperand(MCOperand::CreateReg(0));
975 // Disassemble operand 2, which consists of three components.
976 if (OpIdx + 2 >= NumOps)
979 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
980 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
981 (OpInfo[OpIdx+2].RegClass < 0) &&
982 "Expect 3 reg operands");
984 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
985 unsigned Rs = slice(insn, 4, 4);
987 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
990 // Register-controlled shifts: [Rm, Rs, shift].
991 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
993 // Inst{6-5} encodes the shift opcode.
994 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
995 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
997 // Constant shifts: [Rm, reg0, shift_imm].
998 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
999 // Inst{6-5} encodes the shift opcode.
1000 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1001 // Inst{11-7} encodes the imm5 shift amount.
1002 unsigned ShImm = slice(insn, 11, 7);
1004 // A8.4.1. Possible rrx or shift amount of 32...
1005 getImmShiftSE(ShOp, ShImm);
1006 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1013 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1014 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1016 const TargetInstrDesc &TID = ARMInsts[Opcode];
1017 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1018 const TargetOperandInfo *OpInfo = TID.OpInfo;
1019 if (!OpInfo) return false;
1021 unsigned &OpIdx = NumOpsAdded;
1025 assert(((!isStore && TID.getNumDefs() > 0) ||
1026 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1027 && "Invalid arguments");
1029 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1030 if (isPrePost && isStore) {
1031 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1032 "Reg operand expected");
1033 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1038 // Disassemble the dst/src operand.
1039 if (OpIdx >= NumOps)
1042 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1043 "Reg operand expected");
1044 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1048 // After dst of a pre- and post-indexed load is the address base writeback.
1049 if (isPrePost && !isStore) {
1050 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1051 "Reg operand expected");
1052 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1057 // Disassemble the base operand.
1058 if (OpIdx >= NumOps)
1061 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1062 "Reg operand expected");
1063 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1064 && "Index mode or tied_to operand expected");
1065 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1069 // For reg/reg form, base reg is followed by +/- reg shop imm.
1070 // For immediate form, it is followed by +/- imm12.
1071 // See also ARMAddressingModes.h (Addressing Mode #2).
1072 if (OpIdx + 1 >= NumOps)
1075 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1076 if (getIBit(insn) == 0) {
1077 // For pre- and post-indexed case, add a reg0 operand (Addressing Mode #2).
1078 // Otherwise, skip the reg operand since for addrmode_imm12, Rn has already
1081 MI.addOperand(MCOperand::CreateReg(0));
1085 // Disassemble the 12-bit immediate offset.
1086 unsigned Imm12 = slice(insn, 11, 0);
1087 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
1088 MI.addOperand(MCOperand::CreateImm(Offset));
1091 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1092 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1094 // Inst{6-5} encodes the shift opcode.
1095 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1096 // Inst{11-7} encodes the imm5 shift amount.
1097 unsigned ShImm = slice(insn, 11, 7);
1099 // A8.4.1. Possible rrx or shift amount of 32...
1100 getImmShiftSE(ShOp, ShImm);
1101 MI.addOperand(MCOperand::CreateImm(
1102 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
1109 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1110 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1111 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1114 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1115 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1116 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1119 static bool HasDualReg(unsigned Opcode) {
1123 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1124 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1129 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1130 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1132 const TargetInstrDesc &TID = ARMInsts[Opcode];
1133 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1134 const TargetOperandInfo *OpInfo = TID.OpInfo;
1135 if (!OpInfo) return false;
1137 unsigned &OpIdx = NumOpsAdded;
1141 assert(((!isStore && TID.getNumDefs() > 0) ||
1142 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1143 && "Invalid arguments");
1145 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1146 if (isPrePost && isStore) {
1147 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1148 "Reg operand expected");
1149 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1154 bool DualReg = HasDualReg(Opcode);
1156 // Disassemble the dst/src operand.
1157 if (OpIdx >= NumOps)
1160 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1161 "Reg operand expected");
1162 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1166 // Fill in LDRD and STRD's second operand, but only if it's offset mode OR we
1167 // have a pre-or-post-indexed store operation.
1168 if (DualReg && (!isPrePost || isStore)) {
1169 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1170 decodeRd(insn) + 1)));
1174 // After dst of a pre- and post-indexed load is the address base writeback.
1175 if (isPrePost && !isStore) {
1176 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1177 "Reg operand expected");
1178 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1183 // Disassemble the base operand.
1184 if (OpIdx >= NumOps)
1187 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1188 "Reg operand expected");
1189 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1190 && "Offset mode or tied_to operand expected");
1191 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1195 // For reg/reg form, base reg is followed by +/- reg.
1196 // For immediate form, it is followed by +/- imm8.
1197 // See also ARMAddressingModes.h (Addressing Mode #3).
1198 if (OpIdx + 1 >= NumOps)
1201 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1202 (OpInfo[OpIdx+1].RegClass < 0) &&
1203 "Expect 1 reg operand followed by 1 imm operand");
1205 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1206 if (getAM3IBit(insn) == 1) {
1207 MI.addOperand(MCOperand::CreateReg(0));
1209 // Disassemble the 8-bit immediate offset.
1210 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1211 unsigned Imm4L = insn & 0xF;
1212 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1213 MI.addOperand(MCOperand::CreateImm(Offset));
1215 // Disassemble the offset reg (Rm).
1216 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1218 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1219 MI.addOperand(MCOperand::CreateImm(Offset));
1226 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1227 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1228 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1232 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1233 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1234 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1237 // The algorithm for disassembly of LdStMulFrm is different from others because
1238 // it explicitly populates the two predicate operands after the base register.
1239 // After that, we need to populate the reglist with each affected register
1240 // encoded as an MCOperand.
1241 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1242 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1244 assert(NumOps >= 4 && "LdStMulFrm expects NumOps >= 4");
1247 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1249 // Writeback to base, if necessary.
1250 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::STMIA_UPD ||
1251 Opcode == ARM::LDMDA_UPD || Opcode == ARM::STMDA_UPD ||
1252 Opcode == ARM::LDMDB_UPD || Opcode == ARM::STMDB_UPD ||
1253 Opcode == ARM::LDMIB_UPD || Opcode == ARM::STMIB_UPD) {
1254 MI.addOperand(MCOperand::CreateReg(Base));
1258 // Add the base register operand.
1259 MI.addOperand(MCOperand::CreateReg(Base));
1261 // Handling the two predicate operands before the reglist.
1262 int64_t CondVal = insn >> ARMII::CondShift;
1263 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1264 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1268 // Fill the variadic part of reglist.
1269 unsigned RegListBits = insn & ((1 << 16) - 1);
1270 for (unsigned i = 0; i < 16; ++i) {
1271 if ((RegListBits >> i) & 1) {
1272 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1281 // LDREX, LDREXB, LDREXH: Rd Rn
1282 // LDREXD: Rd Rd+1 Rn
1283 // STREX, STREXB, STREXH: Rd Rm Rn
1284 // STREXD: Rd Rm Rm+1 Rn
1286 // SWP, SWPB: Rd Rm Rn
1287 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1288 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1290 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1291 if (!OpInfo) return false;
1293 unsigned &OpIdx = NumOpsAdded;
1298 && OpInfo[0].RegClass == ARM::GPRRegClassID
1299 && OpInfo[1].RegClass == ARM::GPRRegClassID
1300 && "Expect 2 reg operands");
1302 bool isStore = slice(insn, 20, 20) == 0;
1303 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1305 // Add the destination operand.
1306 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1310 // Store register Exclusive needs a source operand.
1312 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1317 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1318 decodeRm(insn)+1)));
1322 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1323 decodeRd(insn)+1)));
1327 // Finally add the pointer operand.
1328 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1335 // Misc. Arithmetic Instructions.
1337 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1338 // RBIT, REV, REV16, REVSH: Rd Rm
1339 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1340 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1342 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1343 unsigned &OpIdx = NumOpsAdded;
1348 && OpInfo[0].RegClass == ARM::GPRRegClassID
1349 && OpInfo[1].RegClass == ARM::GPRRegClassID
1350 && "Expect 2 reg operands");
1352 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1354 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1359 assert(NumOps >= 4 && "Expect >= 4 operands");
1360 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1365 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1369 // If there is still an operand info left which is an immediate operand, add
1370 // an additional imm5 LSL/ASR operand.
1371 if (ThreeReg && OpInfo[OpIdx].RegClass < 0
1372 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1373 // Extract the 5-bit immediate field Inst{11-7}.
1374 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1375 ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
1376 if (Opcode == ARM::PKHBT)
1378 else if (Opcode == ARM::PKHBT)
1380 getImmShiftSE(Opc, ShiftAmt);
1381 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
1388 /// DisassembleSatFrm - Disassemble saturate instructions:
1389 /// SSAT, SSAT16, USAT, and USAT16.
1390 static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1391 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1393 const TargetInstrDesc &TID = ARMInsts[Opcode];
1394 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1396 // Disassemble register def.
1397 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1400 unsigned Pos = slice(insn, 20, 16);
1401 if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16)
1403 MI.addOperand(MCOperand::CreateImm(Pos));
1405 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1408 if (NumOpsAdded == 4) {
1409 ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
1410 // Inst{11-7} encodes the imm5 shift amount.
1411 unsigned ShAmt = slice(insn, 11, 7);
1413 // A8.6.183. Possible ASR shift amount of 32...
1414 if (Opc == ARM_AM::asr)
1417 Opc = ARM_AM::no_shift;
1419 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
1424 // Extend instructions.
1425 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1426 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1427 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1428 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1429 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1431 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1432 unsigned &OpIdx = NumOpsAdded;
1437 && OpInfo[0].RegClass == ARM::GPRRegClassID
1438 && OpInfo[1].RegClass == ARM::GPRRegClassID
1439 && "Expect 2 reg operands");
1441 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1443 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1448 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1453 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1457 // If there is still an operand info left which is an immediate operand, add
1458 // an additional rotate immediate operand.
1459 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1460 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1461 // Extract the 2-bit rotate field Inst{11-10}.
1462 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1463 // Rotation by 8, 16, or 24 bits.
1464 MI.addOperand(MCOperand::CreateImm(rot << 3));
1471 /////////////////////////////////////
1473 // Utility Functions For VFP //
1475 /////////////////////////////////////
1477 // Extract/Decode Dd/Sd:
1479 // SP => d = UInt(Vd:D)
1480 // DP => d = UInt(D:Vd)
1481 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1482 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1483 : (decodeRd(insn) | getDBit(insn) << 4);
1486 // Extract/Decode Dn/Sn:
1488 // SP => n = UInt(Vn:N)
1489 // DP => n = UInt(N:Vn)
1490 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1491 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1492 : (decodeRn(insn) | getNBit(insn) << 4);
1495 // Extract/Decode Dm/Sm:
1497 // SP => m = UInt(Vm:M)
1498 // DP => m = UInt(M:Vm)
1499 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1500 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1501 : (decodeRm(insn) | getMBit(insn) << 4);
1505 static APInt VFPExpandImm(unsigned char byte, unsigned N) {
1506 assert(N == 32 || N == 64);
1509 unsigned bit6 = slice(byte, 6, 6);
1511 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1513 Result |= 0x1f << 25;
1515 Result |= 0x1 << 30;
1517 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1518 (uint64_t)slice(byte, 5, 0) << 48;
1520 Result |= 0xffULL << 54;
1522 Result |= 0x1ULL << 62;
1524 return APInt(N, Result);
1527 // VFP Unary Format Instructions:
1529 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1530 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1531 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1532 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1533 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1535 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1537 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1538 unsigned &OpIdx = NumOpsAdded;
1542 unsigned RegClass = OpInfo[OpIdx].RegClass;
1543 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1544 "Reg operand expected");
1545 bool isSP = (RegClass == ARM::SPRRegClassID);
1547 MI.addOperand(MCOperand::CreateReg(
1548 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1551 // Early return for compare with zero instructions.
1552 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1553 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1556 RegClass = OpInfo[OpIdx].RegClass;
1557 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1558 "Reg operand expected");
1559 isSP = (RegClass == ARM::SPRRegClassID);
1561 MI.addOperand(MCOperand::CreateReg(
1562 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1568 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1569 // Some of them have operand constraints which tie the first operand in the
1570 // InOperandList to that of the dst. As far as asm printing is concerned, this
1571 // tied_to operand is simply skipped.
1572 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1573 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1575 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1577 const TargetInstrDesc &TID = ARMInsts[Opcode];
1578 const TargetOperandInfo *OpInfo = TID.OpInfo;
1579 unsigned &OpIdx = NumOpsAdded;
1583 unsigned RegClass = OpInfo[OpIdx].RegClass;
1584 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1585 "Reg operand expected");
1586 bool isSP = (RegClass == ARM::SPRRegClassID);
1588 MI.addOperand(MCOperand::CreateReg(
1589 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1592 // Skip tied_to operand constraint.
1593 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1594 assert(NumOps >= 4 && "Expect >=4 operands");
1595 MI.addOperand(MCOperand::CreateReg(0));
1599 MI.addOperand(MCOperand::CreateReg(
1600 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1603 MI.addOperand(MCOperand::CreateReg(
1604 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1610 // A8.6.295 vcvt (floating-point <-> integer)
1611 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1612 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1614 // A8.6.297 vcvt (floating-point and fixed-point)
1615 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1616 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1617 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1619 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1621 const TargetInstrDesc &TID = ARMInsts[Opcode];
1622 const TargetOperandInfo *OpInfo = TID.OpInfo;
1623 if (!OpInfo) return false;
1625 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1626 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1627 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1631 assert(NumOps >= 3 && "Expect >= 3 operands");
1632 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1633 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1634 MI.addOperand(MCOperand::CreateReg(
1635 getRegisterEnum(B, RegClassID,
1636 decodeVFPRd(insn, SP))));
1638 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1639 "Tied to operand expected");
1640 MI.addOperand(MI.getOperand(0));
1642 assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() &&
1643 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1644 MI.addOperand(MCOperand::CreateImm(fbits));
1649 // The Rd (destination) and Rm (source) bits have different interpretations
1650 // depending on their single-precisonness.
1652 if (slice(insn, 18, 18) == 1) { // to_integer operation
1653 d = decodeVFPRd(insn, true /* Is Single Precision */);
1654 MI.addOperand(MCOperand::CreateReg(
1655 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1656 m = decodeVFPRm(insn, SP);
1657 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1659 d = decodeVFPRd(insn, SP);
1660 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1661 m = decodeVFPRm(insn, true /* Is Single Precision */);
1662 MI.addOperand(MCOperand::CreateReg(
1663 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1671 // VMOVRS - A8.6.330
1672 // Rt => Rd; Sn => UInt(Vn:N)
1673 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1674 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1676 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1678 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1680 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1681 decodeVFPRn(insn, true))));
1686 // VMOVRRD - A8.6.332
1687 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1689 // VMOVRRS - A8.6.331
1690 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1691 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1692 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1694 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1696 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1697 unsigned &OpIdx = NumOpsAdded;
1699 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1701 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1705 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1706 unsigned Sm = decodeVFPRm(insn, true);
1707 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1709 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1713 MI.addOperand(MCOperand::CreateReg(
1714 getRegisterEnum(B, ARM::DPRRegClassID,
1715 decodeVFPRm(insn, false))));
1721 // VMOVSR - A8.6.330
1722 // Rt => Rd; Sn => UInt(Vn:N)
1723 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1724 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1726 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1728 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1729 decodeVFPRn(insn, true))));
1730 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1736 // VMOVDRR - A8.6.332
1737 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1739 // VMOVRRS - A8.6.331
1740 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1741 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1742 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1744 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1746 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1747 unsigned &OpIdx = NumOpsAdded;
1751 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1752 unsigned Sm = decodeVFPRm(insn, true);
1753 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1755 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1759 MI.addOperand(MCOperand::CreateReg(
1760 getRegisterEnum(B, ARM::DPRRegClassID,
1761 decodeVFPRm(insn, false))));
1765 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1767 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1773 // VFP Load/Store Instructions.
1774 // VLDRD, VLDRS, VSTRD, VSTRS
1775 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1776 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1778 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1780 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS);
1781 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1783 // Extract Dd/Sd for operand 0.
1784 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1786 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1788 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1789 MI.addOperand(MCOperand::CreateReg(Base));
1791 // Next comes the AM5 Opcode.
1792 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1793 unsigned char Imm8 = insn & 0xFF;
1794 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1801 // VFP Load/Store Multiple Instructions.
1802 // We have an optional write back reg, the base, and two predicate operands.
1803 // It is then followed by a reglist of either DPR(s) or SPR(s).
1805 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1806 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1807 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1809 assert(NumOps >= 4 && "VFPLdStMulFrm expects NumOps >= 4");
1811 unsigned &OpIdx = NumOpsAdded;
1815 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1817 // Writeback to base, if necessary.
1818 if (Opcode == ARM::VLDMDIA_UPD || Opcode == ARM::VLDMSIA_UPD ||
1819 Opcode == ARM::VLDMDDB_UPD || Opcode == ARM::VLDMSDB_UPD ||
1820 Opcode == ARM::VSTMDIA_UPD || Opcode == ARM::VSTMSIA_UPD ||
1821 Opcode == ARM::VSTMDDB_UPD || Opcode == ARM::VSTMSDB_UPD) {
1822 MI.addOperand(MCOperand::CreateReg(Base));
1826 MI.addOperand(MCOperand::CreateReg(Base));
1828 // Handling the two predicate operands before the reglist.
1829 int64_t CondVal = insn >> ARMII::CondShift;
1830 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1831 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1835 bool isSPVFP = (Opcode == ARM::VLDMSIA || Opcode == ARM::VLDMSDB ||
1836 Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMSDB_UPD ||
1837 Opcode == ARM::VSTMSIA || Opcode == ARM::VSTMSDB ||
1838 Opcode == ARM::VSTMSIA_UPD || Opcode == ARM::VSTMSDB_UPD);
1839 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1842 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1844 // Fill the variadic part of reglist.
1845 unsigned char Imm8 = insn & 0xFF;
1846 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1848 // Apply some sanity checks before proceeding.
1849 if (Regs == 0 || (RegD + Regs) > 32 || (!isSPVFP && Regs > 16))
1852 for (unsigned i = 0; i < Regs; ++i) {
1853 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1861 // Misc. VFP Instructions.
1862 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1863 // FCONSTD (DPR and a VFPf64Imm operand)
1864 // FCONSTS (SPR and a VFPf32Imm operand)
1865 // VMRS/VMSR (GPR operand)
1866 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1867 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1869 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1870 unsigned &OpIdx = NumOpsAdded;
1874 if (Opcode == ARM::FMSTAT)
1877 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1879 unsigned RegEnum = 0;
1880 switch (OpInfo[0].RegClass) {
1881 case ARM::DPRRegClassID:
1882 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1884 case ARM::SPRRegClassID:
1885 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1887 case ARM::GPRRegClassID:
1888 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1891 assert(0 && "Invalid reg class id");
1895 MI.addOperand(MCOperand::CreateReg(RegEnum));
1898 // Extract/decode the f64/f32 immediate.
1899 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1900 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1901 // The asm syntax specifies the floating point value, not the 8-bit literal.
1902 APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1903 Opcode == ARM::FCONSTD ? 64 : 32);
1904 APFloat immFP = APFloat(immRaw, true);
1905 double imm = Opcode == ARM::FCONSTD ? immFP.convertToDouble() :
1906 immFP.convertToFloat();
1907 MI.addOperand(MCOperand::CreateFPImm(imm));
1915 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
1916 #include "ThumbDisassemblerCore.h"
1918 /////////////////////////////////////////////////////
1920 // Utility Functions For ARM Advanced SIMD //
1922 /////////////////////////////////////////////////////
1924 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
1925 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
1927 // A7.3 Register encoding
1929 // Extract/Decode NEON D/Vd:
1931 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
1932 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
1933 // handling it in the getRegisterEnum() utility function.
1934 // D = Inst{22}, Vd = Inst{15-12}
1935 static unsigned decodeNEONRd(uint32_t insn) {
1936 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
1937 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
1940 // Extract/Decode NEON N/Vn:
1942 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
1943 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
1944 // handling it in the getRegisterEnum() utility function.
1945 // N = Inst{7}, Vn = Inst{19-16}
1946 static unsigned decodeNEONRn(uint32_t insn) {
1947 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
1948 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
1951 // Extract/Decode NEON M/Vm:
1953 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
1954 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
1955 // handling it in the getRegisterEnum() utility function.
1956 // M = Inst{5}, Vm = Inst{3-0}
1957 static unsigned decodeNEONRm(uint32_t insn) {
1958 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
1959 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
1970 } // End of unnamed namespace
1972 // size field -> Inst{11-10}
1973 // index_align field -> Inst{7-4}
1975 // The Lane Index interpretation depends on the Data Size:
1976 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
1977 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
1978 // 32 (encoded as size = 0b10) -> Index = index_align[3]
1980 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
1981 static unsigned decodeLaneIndex(uint32_t insn) {
1982 unsigned size = insn >> 10 & 3;
1983 assert((size == 0 || size == 1 || size == 2) &&
1984 "Encoding error: size should be either 0, 1, or 2");
1986 unsigned index_align = insn >> 4 & 0xF;
1987 return (index_align >> 1) >> size;
1990 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
1991 // op = Inst{5}, cmode = Inst{11-8}
1992 // i = Inst{24} (ARM architecture)
1993 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
1994 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
1995 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
1996 unsigned char op = (insn >> 5) & 1;
1997 unsigned char cmode = (insn >> 8) & 0xF;
1998 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
1999 ((insn >> 16) & 7) << 4 |
2001 return (op << 12) | (cmode << 8) | Imm8;
2004 // A8.6.339 VMUL, VMULL (by scalar)
2005 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2006 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2007 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2014 assert(0 && "Unreachable code!");
2019 // A8.6.339 VMUL, VMULL (by scalar)
2020 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2021 // ESize32 => index = Inst{5} (M) D0-D15
2022 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2025 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2027 return (insn >> 5) & 1;
2029 assert(0 && "Unreachable code!");
2034 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2035 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2036 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2037 return 64 - ((insn >> 16) & 0x3F);
2040 // A8.6.302 VDUP (scalar)
2041 // ESize8 => index = Inst{19-17}
2042 // ESize16 => index = Inst{19-18}
2043 // ESize32 => index = Inst{19}
2044 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2047 return (insn >> 17) & 7;
2049 return (insn >> 18) & 3;
2051 return (insn >> 19) & 1;
2053 assert(0 && "Unspecified element size!");
2058 // A8.6.328 VMOV (ARM core register to scalar)
2059 // A8.6.329 VMOV (scalar to ARM core register)
2060 // ESize8 => index = Inst{21:6-5}
2061 // ESize16 => index = Inst{21:6}
2062 // ESize32 => index = Inst{21}
2063 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2066 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2068 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2070 return ((insn >> 21) & 1);
2072 assert(0 && "Unspecified element size!");
2077 // Imm6 = Inst{21-16}, L = Inst{7}
2079 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2081 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2082 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2083 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2084 // '1xxxxxx' => esize = 64; shift_amount = imm6
2086 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2088 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2089 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2090 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2091 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2093 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2094 ElemSize esize = ESizeNA;
2095 unsigned L = (insn >> 7) & 1;
2096 unsigned imm6 = (insn >> 16) & 0x3F;
2100 else if (imm6 >> 4 == 1)
2102 else if (imm6 >> 5 == 1)
2105 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2110 return esize == ESize64 ? imm6 : (imm6 - esize);
2112 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2116 // Imm4 = Inst{11-8}
2117 static unsigned decodeN3VImm(uint32_t insn) {
2118 return (insn >> 8) & 0xF;
2122 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2124 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2126 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2128 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2130 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2131 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2132 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2135 const TargetInstrDesc &TID = ARMInsts[Opcode];
2136 const TargetOperandInfo *OpInfo = TID.OpInfo;
2138 // At least one DPR register plus addressing mode #6.
2139 assert(NumOps >= 3 && "Expect >= 3 operands");
2141 unsigned &OpIdx = NumOpsAdded;
2145 // We have homogeneous NEON registers for Load/Store.
2146 unsigned RegClass = 0;
2148 // Double-spaced registers have increments of 2.
2149 unsigned Inc = DblSpaced ? 2 : 1;
2151 unsigned Rn = decodeRn(insn);
2152 unsigned Rm = decodeRm(insn);
2153 unsigned Rd = decodeNEONRd(insn);
2155 // A7.7.1 Advanced SIMD addressing mode.
2158 // LLVM Addressing Mode #6.
2159 unsigned RmEnum = 0;
2161 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2164 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2165 // then possible lane index.
2166 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2167 "Reg operand expected");
2170 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2175 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2176 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2177 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2179 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2183 MI.addOperand(MCOperand::CreateReg(RmEnum));
2187 assert(OpIdx < NumOps &&
2188 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2189 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2190 "Reg operand expected");
2192 RegClass = OpInfo[OpIdx].RegClass;
2193 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2194 MI.addOperand(MCOperand::CreateReg(
2195 getRegisterEnum(B, RegClass, Rd)));
2200 // Handle possible lane index.
2201 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2202 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2203 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2208 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2209 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2210 RegClass = OpInfo[0].RegClass;
2212 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2213 MI.addOperand(MCOperand::CreateReg(
2214 getRegisterEnum(B, RegClass, Rd)));
2220 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2225 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2226 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2227 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2229 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2233 MI.addOperand(MCOperand::CreateReg(RmEnum));
2237 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2238 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2239 "Tied to operand expected");
2240 MI.addOperand(MCOperand::CreateReg(0));
2244 // Handle possible lane index.
2245 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2246 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2247 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2252 // Accessing registers past the end of the NEON register file is not
2261 // If L (Inst{21}) == 0, store instructions.
2262 // Find out about double-spaced-ness of the Opcode and pass it on to
2263 // DisassembleNLdSt0().
2264 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2265 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2267 const StringRef Name = ARMInsts[Opcode].Name;
2268 bool DblSpaced = false;
2270 if (Name.find("LN") != std::string::npos) {
2271 // To one lane instructions.
2272 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2274 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2275 if (Name.endswith("16") || Name.endswith("16_UPD"))
2276 DblSpaced = slice(insn, 5, 5) == 1;
2278 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2279 if (Name.endswith("32") || Name.endswith("32_UPD"))
2280 DblSpaced = slice(insn, 6, 6) == 1;
2283 // Multiple n-element structures with type encoded as Inst{11-8}.
2284 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2286 // n == 2 && type == 0b1001 -> DblSpaced = true
2287 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2288 DblSpaced = slice(insn, 11, 8) == 9;
2290 // n == 3 && type == 0b0101 -> DblSpaced = true
2291 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2292 DblSpaced = slice(insn, 11, 8) == 5;
2294 // n == 4 && type == 0b0001 -> DblSpaced = true
2295 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2296 DblSpaced = slice(insn, 11, 8) == 1;
2299 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2300 slice(insn, 21, 21) == 0, DblSpaced, B);
2307 // Qd/Dd imm src(=Qd/Dd)
2308 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2309 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2311 const TargetInstrDesc &TID = ARMInsts[Opcode];
2312 const TargetOperandInfo *OpInfo = TID.OpInfo;
2314 assert(NumOps >= 2 &&
2315 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2316 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2317 (OpInfo[1].RegClass < 0) &&
2318 "Expect 1 reg operand followed by 1 imm operand");
2320 // Qd/Dd = Inst{22:15-12} => NEON Rd
2321 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2322 decodeNEONRd(insn))));
2324 ElemSize esize = ESizeNA;
2327 case ARM::VMOVv16i8:
2330 case ARM::VMOVv4i16:
2331 case ARM::VMOVv8i16:
2332 case ARM::VMVNv4i16:
2333 case ARM::VMVNv8i16:
2334 case ARM::VBICiv4i16:
2335 case ARM::VBICiv8i16:
2336 case ARM::VORRiv4i16:
2337 case ARM::VORRiv8i16:
2340 case ARM::VMOVv2i32:
2341 case ARM::VMOVv4i32:
2342 case ARM::VMVNv2i32:
2343 case ARM::VMVNv4i32:
2344 case ARM::VBICiv2i32:
2345 case ARM::VBICiv4i32:
2346 case ARM::VORRiv2i32:
2347 case ARM::VORRiv4i32:
2350 case ARM::VMOVv1i64:
2351 case ARM::VMOVv2i64:
2355 assert(0 && "Unexpected opcode!");
2359 // One register and a modified immediate value.
2360 // Add the imm operand.
2361 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2365 // VBIC/VORRiv*i* variants have an extra $src = $Vd to be filled in.
2367 (OpInfo[2].RegClass == ARM::DPRRegClassID ||
2368 OpInfo[2].RegClass == ARM::QPRRegClassID)) {
2369 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2370 decodeNEONRd(insn))));
2381 N2V_VectorConvert_Between_Float_Fixed
2383 } // End of unnamed namespace
2385 // Vector Convert [between floating-point and fixed-point]
2386 // Qd/Dd Qm/Dm [fbits]
2388 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2389 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2392 // Vector Move Long:
2395 // Vector Move Narrow:
2399 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2400 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2402 const TargetInstrDesc &TID = ARMInsts[Opc];
2403 const TargetOperandInfo *OpInfo = TID.OpInfo;
2405 assert(NumOps >= 2 &&
2406 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2407 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2408 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2409 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2410 "Expect >= 2 operands and first 2 as reg operands");
2412 unsigned &OpIdx = NumOpsAdded;
2416 ElemSize esize = ESizeNA;
2417 if (Flag == N2V_VectorDupLane) {
2418 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2419 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2420 "Unexpected Opcode");
2421 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2422 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2426 // Qd/Dd = Inst{22:15-12} => NEON Rd
2427 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2428 decodeNEONRd(insn))));
2432 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2434 MI.addOperand(MCOperand::CreateReg(0));
2438 // Dm = Inst{5:3-0} => NEON Rm
2439 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2440 decodeNEONRm(insn))));
2443 // VZIP and others have two TIED_TO reg operands.
2445 while (OpIdx < NumOps &&
2446 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2447 // Add TIED_TO operand.
2448 MI.addOperand(MI.getOperand(Idx));
2452 // Add the imm operand, if required.
2453 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2454 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2456 unsigned imm = 0xFFFFFFFF;
2458 if (Flag == N2V_VectorDupLane)
2459 imm = decodeNVLaneDupIndex(insn, esize);
2460 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2461 imm = decodeVCVTFractionBits(insn);
2463 assert(imm != 0xFFFFFFFF && "Internal error");
2464 MI.addOperand(MCOperand::CreateImm(imm));
2471 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2472 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2474 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2477 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2478 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2480 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2481 N2V_VectorConvert_Between_Float_Fixed, B);
2483 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2484 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2486 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2487 N2V_VectorDupLane, B);
2490 // Vector Shift [Accumulate] Instructions.
2491 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2493 // Vector Shift Left Long (with maximum shift count) Instructions.
2494 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2496 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2497 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2499 const TargetInstrDesc &TID = ARMInsts[Opcode];
2500 const TargetOperandInfo *OpInfo = TID.OpInfo;
2502 assert(NumOps >= 3 &&
2503 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2504 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2505 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2506 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2507 "Expect >= 3 operands and first 2 as reg operands");
2509 unsigned &OpIdx = NumOpsAdded;
2513 // Qd/Dd = Inst{22:15-12} => NEON Rd
2514 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2515 decodeNEONRd(insn))));
2518 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2520 MI.addOperand(MCOperand::CreateReg(0));
2524 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2525 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2526 "Reg operand expected");
2528 // Qm/Dm = Inst{5:3-0} => NEON Rm
2529 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2530 decodeNEONRm(insn))));
2533 assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
2535 // Add the imm operand.
2537 // VSHLL has maximum shift count as the imm, inferred from its size.
2541 Imm = decodeNVSAmt(insn, LeftShift);
2553 MI.addOperand(MCOperand::CreateImm(Imm));
2559 // Left shift instructions.
2560 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2561 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2563 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2566 // Right shift instructions have different shift amount interpretation.
2567 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2568 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2570 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2579 N3V_Multiply_By_Scalar
2581 } // End of unnamed namespace
2583 // NEON Three Register Instructions with Optional Immediate Operand
2585 // Vector Extract Instructions.
2586 // Qd/Dd Qn/Dn Qm/Dm imm4
2588 // Vector Shift (Register) Instructions.
2589 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2591 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2592 // Qd/Dd Qn/Dn RestrictedDm index
2595 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2596 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2598 const TargetInstrDesc &TID = ARMInsts[Opcode];
2599 const TargetOperandInfo *OpInfo = TID.OpInfo;
2601 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2602 assert(NumOps >= 3 &&
2603 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2604 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2605 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2606 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2607 "Expect >= 3 operands and first 2 as reg operands");
2609 unsigned &OpIdx = NumOpsAdded;
2613 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2614 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2615 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2616 ElemSize esize = ESizeNA;
2617 if (Flag == N3V_Multiply_By_Scalar) {
2618 unsigned size = (insn >> 20) & 3;
2619 if (size == 1) esize = ESize16;
2620 if (size == 2) esize = ESize32;
2621 assert (esize == ESize16 || esize == ESize32);
2624 // Qd/Dd = Inst{22:15-12} => NEON Rd
2625 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2626 decodeNEONRd(insn))));
2629 // VABA, VABAL, VBSLd, VBSLq, ...
2630 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2632 MI.addOperand(MCOperand::CreateReg(0));
2636 // Dn = Inst{7:19-16} => NEON Rn
2638 // Dm = Inst{5:3-0} => NEON Rm
2639 MI.addOperand(MCOperand::CreateReg(
2640 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2641 VdVnVm ? decodeNEONRn(insn)
2642 : decodeNEONRm(insn))));
2645 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2647 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2650 // Dm = Inst{5:3-0} => NEON Rm
2652 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2654 // Dn = Inst{7:19-16} => NEON Rn
2655 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2656 : decodeNEONRm(insn))
2657 : decodeNEONRn(insn);
2659 MI.addOperand(MCOperand::CreateReg(
2660 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2663 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2664 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2665 // Add the imm operand.
2668 Imm = decodeN3VImm(insn);
2669 else if (IsDmRestricted)
2670 Imm = decodeRestrictedDmIndex(insn, esize);
2672 assert(0 && "Internal error: unreachable code!");
2676 MI.addOperand(MCOperand::CreateImm(Imm));
2683 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2684 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2686 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2689 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2690 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2692 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2693 N3V_VectorShift, B);
2695 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode,
2696 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2698 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2699 N3V_VectorExtract, B);
2701 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2702 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2704 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2705 N3V_Multiply_By_Scalar, B);
2708 // Vector Table Lookup
2710 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2711 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2712 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2713 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2714 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2715 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2717 const TargetInstrDesc &TID = ARMInsts[Opcode];
2718 const TargetOperandInfo *OpInfo = TID.OpInfo;
2719 if (!OpInfo) return false;
2721 assert(NumOps >= 3 &&
2722 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2723 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2724 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2725 "Expect >= 3 operands and first 3 as reg operands");
2727 unsigned &OpIdx = NumOpsAdded;
2731 unsigned Rn = decodeNEONRn(insn);
2733 // {Dn} encoded as len = 0b00
2734 // {Dn Dn+1} encoded as len = 0b01
2735 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2736 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2737 unsigned Len = slice(insn, 9, 8) + 1;
2739 // Dd (the destination vector)
2740 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2741 decodeNEONRd(insn))));
2744 // Process tied_to operand constraint.
2746 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2747 MI.addOperand(MI.getOperand(Idx));
2751 // Do the <list> now.
2752 for (unsigned i = 0; i < Len; ++i) {
2753 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2754 "Reg operand expected");
2755 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2760 // Dm (the index vector)
2761 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2762 "Reg operand (index vector) expected");
2763 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2764 decodeNEONRm(insn))));
2770 // Vector Get Lane (move scalar to ARM core register) Instructions.
2771 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2772 static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2773 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2775 const TargetInstrDesc &TID = ARMInsts[Opcode];
2776 const TargetOperandInfo *OpInfo = TID.OpInfo;
2777 if (!OpInfo) return false;
2779 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2780 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2781 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2782 OpInfo[2].RegClass < 0 &&
2783 "Expect >= 3 operands with one dst operand");
2786 Opcode == ARM::VGETLNi32 ? ESize32
2787 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2790 // Rt = Inst{15-12} => ARM Rd
2791 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2794 // Dn = Inst{7:19-16} => NEON Rn
2795 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2796 decodeNEONRn(insn))));
2798 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2804 // Vector Set Lane (move ARM core register to scalar) Instructions.
2805 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2806 static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2807 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2809 const TargetInstrDesc &TID = ARMInsts[Opcode];
2810 const TargetOperandInfo *OpInfo = TID.OpInfo;
2811 if (!OpInfo) return false;
2813 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2814 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2815 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2816 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2817 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2818 OpInfo[3].RegClass < 0 &&
2819 "Expect >= 3 operands with one dst operand");
2822 Opcode == ARM::VSETLNi8 ? ESize8
2823 : (Opcode == ARM::VSETLNi16 ? ESize16
2826 // Dd = Inst{7:19-16} => NEON Rn
2827 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2828 decodeNEONRn(insn))));
2831 MI.addOperand(MCOperand::CreateReg(0));
2833 // Rt = Inst{15-12} => ARM Rd
2834 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2837 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2843 // Vector Duplicate Instructions (from ARM core register to all elements).
2844 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2845 static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2846 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2848 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2850 assert(NumOps >= 2 &&
2851 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2852 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2853 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2854 "Expect >= 2 operands and first 2 as reg operand");
2856 unsigned RegClass = OpInfo[0].RegClass;
2858 // Qd/Dd = Inst{7:19-16} => NEON Rn
2859 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2860 decodeNEONRn(insn))));
2862 // Rt = Inst{15-12} => ARM Rd
2863 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2873 static inline bool MemBarrierInstr(uint32_t insn) {
2874 unsigned op7_4 = slice(insn, 7, 4);
2875 if (slice(insn, 31, 8) == 0xf57ff0 && (op7_4 >= 4 && op7_4 <= 6))
2881 static inline bool PreLoadOpcode(unsigned Opcode) {
2883 case ARM::PLDi12: case ARM::PLDrs:
2884 case ARM::PLDWi12: case ARM::PLDWrs:
2885 case ARM::PLIi12: case ARM::PLIrs:
2892 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2893 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2895 // Preload Data/Instruction requires either 2 or 3 operands.
2896 // PLDi, PLDWi, PLIi: addrmode_imm12
2897 // PLDr[a|m], PLDWr[a|m], PLIr[a|m]: ldst_so_reg
2899 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2902 if (Opcode == ARM::PLDi12 || Opcode == ARM::PLDWi12
2903 || Opcode == ARM::PLIi12) {
2904 unsigned Imm12 = slice(insn, 11, 0);
2905 bool Negative = getUBit(insn) == 0;
2906 // -0 is represented specially. All other values are as normal.
2907 if (Imm12 == 0 && Negative)
2909 MI.addOperand(MCOperand::CreateImm(Imm12));
2912 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2915 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
2917 // Inst{6-5} encodes the shift opcode.
2918 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
2919 // Inst{11-7} encodes the imm5 shift amount.
2920 unsigned ShImm = slice(insn, 11, 7);
2922 // A8.4.1. Possible rrx or shift amount of 32...
2923 getImmShiftSE(ShOp, ShImm);
2924 MI.addOperand(MCOperand::CreateImm(
2925 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
2932 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2933 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2935 if (MemBarrierInstr(insn)) {
2936 // DMBsy, DSBsy, and ISBsy instructions have zero operand and are taken care
2937 // of within the generic ARMBasicMCBuilder::BuildIt() method.
2939 // Inst{3-0} encodes the memory barrier option for the variants.
2940 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
2958 if (Opcode == ARM::SETEND) {
2960 MI.addOperand(MCOperand::CreateImm(slice(insn, 9, 9)));
2964 // FIXME: To enable correct asm parsing and disasm of CPS we need 3 different
2965 // opcodes which match the same real instruction. This is needed since there's
2966 // no current handling of optional arguments. Fix here when a better handling
2967 // of optional arguments is implemented.
2968 if (Opcode == ARM::CPS3p) { // M = 1
2969 // Let's reject these impossible imod values by returning false:
2972 // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an
2973 // invalid combination, so we just check for imod=0b00 here.
2974 if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
2976 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
2977 MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
2978 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
2982 if (Opcode == ARM::CPS2p) { // mode = 0, M = 0
2983 // Let's reject these impossible imod values by returning false:
2984 // 1. (imod=0b00,M=0)
2986 if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
2988 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
2989 MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
2993 if (Opcode == ARM::CPS1p) { // imod = 0, iflags = 0, M = 1
2994 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
2999 // DBG has its option specified in Inst{3-0}.
3000 if (Opcode == ARM::DBG) {
3001 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3006 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
3007 if (Opcode == ARM::BKPT) {
3008 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
3009 slice(insn, 3, 0)));
3014 if (PreLoadOpcode(Opcode))
3015 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
3017 assert(0 && "Unexpected misc instruction!");
3021 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
3022 /// We divide the disassembly task into different categories, with each one
3023 /// corresponding to a specific instruction encoding format. There could be
3024 /// exceptions when handling a specific format, and that is why the Opcode is
3025 /// also present in the function prototype.
3026 static const DisassembleFP FuncPtrs[] = {
3030 &DisassembleBrMiscFrm,
3032 &DisassembleDPSoRegFrm,
3035 &DisassembleLdMiscFrm,
3036 &DisassembleStMiscFrm,
3037 &DisassembleLdStMulFrm,
3038 &DisassembleLdStExFrm,
3039 &DisassembleArithMiscFrm,
3042 &DisassembleVFPUnaryFrm,
3043 &DisassembleVFPBinaryFrm,
3044 &DisassembleVFPConv1Frm,
3045 &DisassembleVFPConv2Frm,
3046 &DisassembleVFPConv3Frm,
3047 &DisassembleVFPConv4Frm,
3048 &DisassembleVFPConv5Frm,
3049 &DisassembleVFPLdStFrm,
3050 &DisassembleVFPLdStMulFrm,
3051 &DisassembleVFPMiscFrm,
3052 &DisassembleThumbFrm,
3053 &DisassembleMiscFrm,
3054 &DisassembleNGetLnFrm,
3055 &DisassembleNSetLnFrm,
3056 &DisassembleNDupFrm,
3058 // VLD and VST (including one lane) Instructions.
3061 // A7.4.6 One register and a modified immediate value
3062 // 1-Register Instructions with imm.
3063 // LLVM only defines VMOVv instructions.
3064 &DisassembleN1RegModImmFrm,
3066 // 2-Register Instructions with no imm.
3067 &DisassembleN2RegFrm,
3069 // 2-Register Instructions with imm (vector convert float/fixed point).
3070 &DisassembleNVCVTFrm,
3072 // 2-Register Instructions with imm (vector dup lane).
3073 &DisassembleNVecDupLnFrm,
3075 // Vector Shift Left Instructions.
3076 &DisassembleN2RegVecShLFrm,
3078 // Vector Shift Righ Instructions, which has different interpretation of the
3079 // shift amount from the imm6 field.
3080 &DisassembleN2RegVecShRFrm,
3082 // 3-Register Data-Processing Instructions.
3083 &DisassembleN3RegFrm,
3085 // Vector Shift (Register) Instructions.
3086 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3087 &DisassembleN3RegVecShFrm,
3089 // Vector Extract Instructions.
3090 &DisassembleNVecExtractFrm,
3092 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3093 // By Scalar Instructions.
3094 &DisassembleNVecMulScalarFrm,
3096 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3097 // values in a table and generate a new vector.
3098 &DisassembleNVTBLFrm,
3103 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3104 /// The general idea is to set the Opcode for the MCInst, followed by adding
3105 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3106 /// to the Format-specific disassemble function for disassembly, followed by
3107 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3108 /// which follow the Dst/Src Operands.
3109 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3110 // Stage 1 sets the Opcode.
3111 MI.setOpcode(Opcode);
3112 // If the number of operands is zero, we're done!
3116 // Stage 2 calls the format-specific disassemble function to build the operand
3120 unsigned NumOpsAdded = 0;
3121 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3123 if (!OK || this->Err != 0) return false;
3124 if (NumOpsAdded >= NumOps)
3127 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3128 // FIXME: Should this be done selectively?
3129 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3132 // A8.3 Conditional execution
3133 // A8.3.1 Pseudocode details of conditional execution
3134 // Condition bits '111x' indicate the instruction is always executed.
3135 static uint32_t CondCode(uint32_t CondField) {
3136 if (CondField == 0xF)
3141 /// DoPredicateOperands - DoPredicateOperands process the predicate operands
3142 /// of some Thumb instructions which come before the reglist operands. It
3143 /// returns true if the two predicate operands have been processed.
3144 bool ARMBasicMCBuilder::DoPredicateOperands(MCInst& MI, unsigned Opcode,
3145 uint32_t /* insn */, unsigned short NumOpsRemaining) {
3147 assert(NumOpsRemaining > 0 && "Invalid argument");
3149 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3150 unsigned Idx = MI.getNumOperands();
3152 // First, we check whether this instr specifies the PredicateOperand through
3153 // a pair of TargetOperandInfos with isPredicate() property.
3154 if (NumOpsRemaining >= 2 &&
3155 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3156 OpInfo[Idx].RegClass < 0 &&
3157 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3159 // If we are inside an IT block, get the IT condition bits maintained via
3160 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3163 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3165 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3166 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3173 /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
3174 /// the possible Predicate and SBitModifier, to build the remaining MCOperand
3176 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3177 uint32_t insn, unsigned short NumOpsRemaining) {
3179 assert(NumOpsRemaining > 0 && "Invalid argument");
3181 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3182 const std::string &Name = ARMInsts[Opcode].Name;
3183 unsigned Idx = MI.getNumOperands();
3185 // First, we check whether this instr specifies the PredicateOperand through
3186 // a pair of TargetOperandInfos with isPredicate() property.
3187 if (NumOpsRemaining >= 2 &&
3188 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3189 OpInfo[Idx].RegClass < 0 &&
3190 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3192 // If we are inside an IT block, get the IT condition bits maintained via
3193 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3196 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3198 if (Name.length() > 1 && Name[0] == 't') {
3199 // Thumb conditional branch instructions have their cond field embedded,
3203 if (Name == "t2Bcc")
3204 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22))));
3205 else if (Name == "tBcc")
3206 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8))));
3208 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3210 // ARM instructions get their condition field from Inst{31-28}.
3211 MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
3214 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3216 NumOpsRemaining -= 2;
3219 if (NumOpsRemaining == 0)
3222 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3223 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3224 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3228 if (NumOpsRemaining == 0)
3234 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3235 /// after BuildIt is finished.
3236 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3239 if (!SP) return Status;
3241 if (Opcode == ARM::t2IT)
3242 Status = SP->InitIT(slice(insn, 7, 0)) ? Status : false;
3243 else if (InITBlock())
3249 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3250 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3252 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3253 unsigned Idx = (unsigned)format;
3254 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3255 Disasm = FuncPtrs[Idx];
3258 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3259 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3260 /// Return NULL if it fails to create/return a proper builder. API clients
3261 /// are responsible for freeing up of the allocated memory. Cacheing can be
3262 /// performed by the API clients to improve performance.
3263 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3264 // For "Unknown format", fail by returning a NULL pointer.
3265 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1)) {
3266 DEBUG(errs() << "Unknown format\n");
3270 return new ARMBasicMCBuilder(Opcode, Format,
3271 ARMInsts[Opcode].getNumOperands());