1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #include "ARMDisassemblerCore.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/Support/raw_ostream.h"
20 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
21 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
22 /// describing the operand info for each ARMInsts[i].
24 /// Together with an instruction's encoding format, we can take advantage of the
25 /// NumOperands and the OpInfo fields of the target instruction description in
26 /// the quest to build out the MCOperand list for an MCInst.
28 /// The general guideline is that with a known format, the number of dst and src
29 /// operands are well-known. The dst is built first, followed by the src
30 /// operand(s). The operands not yet used at this point are for the Implicit
31 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
32 /// defined with two components:
34 /// def pred { // Operand PredicateOperand
35 /// ValueType Type = OtherVT;
36 /// string PrintMethod = "printPredicateOperand";
37 /// string AsmOperandLowerMethod = ?;
38 /// dag MIOperandInfo = (ops i32imm, CCR);
39 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
40 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
43 /// which is manifested by the TargetOperandInfo[] of:
45 /// { 0, 0|(1<<TOI::Predicate), 0 },
46 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
48 /// So the first predicate MCOperand corresponds to the immediate part of the
49 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
50 /// corresponds to a register kind of ARM::CPSR.
52 /// For the Defs part, in the simple case of only cc_out:$s, we have:
54 /// def cc_out { // Operand OptionalDefOperand
55 /// ValueType Type = OtherVT;
56 /// string PrintMethod = "printSBitModifierOperand";
57 /// string AsmOperandLowerMethod = ?;
58 /// dag MIOperandInfo = (ops CCR);
59 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
60 /// dag DefaultOps = (ops (i32 zero_reg));
63 /// which is manifested by the one TargetOperandInfo of:
65 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
67 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
68 #include "ARMGenInstrInfo.inc"
72 const char *ARMUtils::OpcodeName(unsigned Opcode) {
73 return ARMInsts[Opcode].Name;
76 // Return the register enum Based on RegClass and the raw register number.
77 // For DRegPair, see comments below.
79 static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister,
80 bool DRegPair = false) {
82 if (DRegPair && RegClassID == ARM::QPRRegClassID) {
83 // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified
84 // in the ARM Architecture Manual as far as I understand it (A8.6.307).
85 // Therefore, we morph the RegClassID to be the sub register class and don't
86 // subsequently transform the RawRegister encoding when calculating RegNum.
88 // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part
89 // where this workaround is meant for.
90 RegClassID = ARM::DPRRegClassID;
93 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
95 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
101 switch (RegClassID) {
102 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
103 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
104 case ARM::DPR_VFP2RegClassID:
106 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
107 case ARM::QPR_VFP2RegClassID:
109 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
113 switch (RegClassID) {
114 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
115 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
116 case ARM::DPR_VFP2RegClassID:
118 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
119 case ARM::QPR_VFP2RegClassID:
121 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
125 switch (RegClassID) {
126 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
127 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
128 case ARM::DPR_VFP2RegClassID:
130 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
131 case ARM::QPR_VFP2RegClassID:
133 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
137 switch (RegClassID) {
138 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
139 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
140 case ARM::DPR_VFP2RegClassID:
142 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
143 case ARM::QPR_VFP2RegClassID:
145 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
149 switch (RegClassID) {
150 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
151 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
152 case ARM::DPR_VFP2RegClassID:
154 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
155 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
159 switch (RegClassID) {
160 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
161 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
162 case ARM::DPR_VFP2RegClassID:
164 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
165 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
169 switch (RegClassID) {
170 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
171 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
172 case ARM::DPR_VFP2RegClassID:
174 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
175 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
179 switch (RegClassID) {
180 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
181 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
182 case ARM::DPR_VFP2RegClassID:
184 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
185 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
189 switch (RegClassID) {
190 case ARM::GPRRegClassID: return ARM::R8;
191 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
192 case ARM::QPRRegClassID: return ARM::Q8;
193 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
197 switch (RegClassID) {
198 case ARM::GPRRegClassID: return ARM::R9;
199 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
200 case ARM::QPRRegClassID: return ARM::Q9;
201 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
205 switch (RegClassID) {
206 case ARM::GPRRegClassID: return ARM::R10;
207 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
208 case ARM::QPRRegClassID: return ARM::Q10;
209 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
213 switch (RegClassID) {
214 case ARM::GPRRegClassID: return ARM::R11;
215 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
216 case ARM::QPRRegClassID: return ARM::Q11;
217 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
221 switch (RegClassID) {
222 case ARM::GPRRegClassID: return ARM::R12;
223 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
224 case ARM::QPRRegClassID: return ARM::Q12;
225 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
229 switch (RegClassID) {
230 case ARM::GPRRegClassID: return ARM::SP;
231 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
232 case ARM::QPRRegClassID: return ARM::Q13;
233 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
237 switch (RegClassID) {
238 case ARM::GPRRegClassID: return ARM::LR;
239 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
240 case ARM::QPRRegClassID: return ARM::Q14;
241 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
245 switch (RegClassID) {
246 case ARM::GPRRegClassID: return ARM::PC;
247 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
248 case ARM::QPRRegClassID: return ARM::Q15;
249 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
253 switch (RegClassID) {
254 case ARM::DPRRegClassID: return ARM::D16;
255 case ARM::SPRRegClassID: return ARM::S16;
259 switch (RegClassID) {
260 case ARM::DPRRegClassID: return ARM::D17;
261 case ARM::SPRRegClassID: return ARM::S17;
265 switch (RegClassID) {
266 case ARM::DPRRegClassID: return ARM::D18;
267 case ARM::SPRRegClassID: return ARM::S18;
271 switch (RegClassID) {
272 case ARM::DPRRegClassID: return ARM::D19;
273 case ARM::SPRRegClassID: return ARM::S19;
277 switch (RegClassID) {
278 case ARM::DPRRegClassID: return ARM::D20;
279 case ARM::SPRRegClassID: return ARM::S20;
283 switch (RegClassID) {
284 case ARM::DPRRegClassID: return ARM::D21;
285 case ARM::SPRRegClassID: return ARM::S21;
289 switch (RegClassID) {
290 case ARM::DPRRegClassID: return ARM::D22;
291 case ARM::SPRRegClassID: return ARM::S22;
295 switch (RegClassID) {
296 case ARM::DPRRegClassID: return ARM::D23;
297 case ARM::SPRRegClassID: return ARM::S23;
301 switch (RegClassID) {
302 case ARM::DPRRegClassID: return ARM::D24;
303 case ARM::SPRRegClassID: return ARM::S24;
307 switch (RegClassID) {
308 case ARM::DPRRegClassID: return ARM::D25;
309 case ARM::SPRRegClassID: return ARM::S25;
313 switch (RegClassID) {
314 case ARM::DPRRegClassID: return ARM::D26;
315 case ARM::SPRRegClassID: return ARM::S26;
319 switch (RegClassID) {
320 case ARM::DPRRegClassID: return ARM::D27;
321 case ARM::SPRRegClassID: return ARM::S27;
325 switch (RegClassID) {
326 case ARM::DPRRegClassID: return ARM::D28;
327 case ARM::SPRRegClassID: return ARM::S28;
331 switch (RegClassID) {
332 case ARM::DPRRegClassID: return ARM::D29;
333 case ARM::SPRRegClassID: return ARM::S29;
337 switch (RegClassID) {
338 case ARM::DPRRegClassID: return ARM::D30;
339 case ARM::SPRRegClassID: return ARM::S30;
343 switch (RegClassID) {
344 case ARM::DPRRegClassID: return ARM::D31;
345 case ARM::SPRRegClassID: return ARM::S31;
349 errs() << "Invalid (RegClassID, RawRegister) combination\n";
350 // Encoding error. Mark the builder with error code != 0.
355 ///////////////////////////////
357 // Utility Functions //
359 ///////////////////////////////
361 // Extract/Decode Rd: Inst{15-12}.
362 static inline unsigned decodeRd(uint32_t insn) {
363 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
366 // Extract/Decode Rn: Inst{19-16}.
367 static inline unsigned decodeRn(uint32_t insn) {
368 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
371 // Extract/Decode Rm: Inst{3-0}.
372 static inline unsigned decodeRm(uint32_t insn) {
373 return (insn & ARMII::GPRRegMask);
376 // Extract/Decode Rs: Inst{11-8}.
377 static inline unsigned decodeRs(uint32_t insn) {
378 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
381 static inline unsigned getCondField(uint32_t insn) {
382 return (insn >> ARMII::CondShift);
385 static inline unsigned getIBit(uint32_t insn) {
386 return (insn >> ARMII::I_BitShift) & 1;
389 static inline unsigned getAM3IBit(uint32_t insn) {
390 return (insn >> ARMII::AM3_I_BitShift) & 1;
393 static inline unsigned getPBit(uint32_t insn) {
394 return (insn >> ARMII::P_BitShift) & 1;
397 static inline unsigned getUBit(uint32_t insn) {
398 return (insn >> ARMII::U_BitShift) & 1;
401 static inline unsigned getPUBits(uint32_t insn) {
402 return (insn >> ARMII::U_BitShift) & 3;
405 static inline unsigned getSBit(uint32_t insn) {
406 return (insn >> ARMII::S_BitShift) & 1;
409 static inline unsigned getWBit(uint32_t insn) {
410 return (insn >> ARMII::W_BitShift) & 1;
413 static inline unsigned getDBit(uint32_t insn) {
414 return (insn >> ARMII::D_BitShift) & 1;
417 static inline unsigned getNBit(uint32_t insn) {
418 return (insn >> ARMII::N_BitShift) & 1;
421 static inline unsigned getMBit(uint32_t insn) {
422 return (insn >> ARMII::M_BitShift) & 1;
425 // See A8.4 Shifts applied to a register.
426 // A8.4.2 Register controlled shifts.
428 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
429 // into llvm enums for shift opcode. The API clients should pass in the value
430 // encoded with two bits, so the assert stays to signal a wrong API usage.
432 // A8-12: DecodeRegShift()
433 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
435 default: assert(0 && "No such value"); return ARM_AM::no_shift;
436 case 0: return ARM_AM::lsl;
437 case 1: return ARM_AM::lsr;
438 case 2: return ARM_AM::asr;
439 case 3: return ARM_AM::ror;
443 // See A8.4 Shifts applied to a register.
444 // A8.4.1 Constant shifts.
446 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
447 // encodings into the intended ShiftOpc and shift amount.
449 // A8-11: DecodeImmShift()
450 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
451 // If type == 0b11 and imm5 == 0, we have an rrx, instead.
452 if (ShOp == ARM_AM::ror && ShImm == 0)
454 // If (lsr or asr) and imm5 == 0, shift amount is 32.
455 if ((ShOp == ARM_AM::lsr || ShOp == ARM_AM::asr) && ShImm == 0)
459 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
460 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
461 // clients should pass in the value encoded with two bits, so the assert stays
462 // to signal a wrong API usage.
463 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
465 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
466 case 1: return ARM_AM::ia; // P=0 U=1
467 case 3: return ARM_AM::ib; // P=1 U=1
468 case 0: return ARM_AM::da; // P=0 U=0
469 case 2: return ARM_AM::db; // P=1 U=0
473 ////////////////////////////////////////////
475 // Disassemble function definitions //
477 ////////////////////////////////////////////
479 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
480 /// instr into a list of MCOperands in the appropriate order, with possible dst,
481 /// followed by possible src(s).
483 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
484 /// the CPSR, is factored into ARMBasicMCBuilder's method named
485 /// TryPredicateAndSBitModifier.
487 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
488 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
490 if (Opcode == ARM::Int_MemBarrierV7 || Opcode == ARM::Int_SyncBarrierV7)
493 assert(0 && "Unexpected pseudo instruction!");
497 // Multiply Instructions.
498 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
499 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
501 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
502 // Rd{19-16} Rn{3-0} Rm{11-8}
504 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
505 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
507 // The mapping of the multiply registers to the "regular" ARM registers, where
508 // there are convenience decoder functions, is:
514 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
515 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
517 const TargetInstrDesc &TID = ARMInsts[Opcode];
518 unsigned short NumDefs = TID.getNumDefs();
519 const TargetOperandInfo *OpInfo = TID.OpInfo;
520 unsigned &OpIdx = NumOpsAdded;
524 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
526 && OpInfo[0].RegClass == ARM::GPRRegClassID
527 && OpInfo[1].RegClass == ARM::GPRRegClassID
528 && OpInfo[2].RegClass == ARM::GPRRegClassID
529 && "Expect three register operands");
531 // Instructions with two destination registers have RdLo{15-12} first.
533 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
534 "Expect 4th register operand");
535 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
540 // The destination register: RdHi{19-16} or Rd{19-16}.
541 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
544 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
545 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
547 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
551 // Many multiply instructions (e.g., MLA) have three src registers.
552 // The third register operand is Ra{15-12}.
553 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
554 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
562 // Helper routines for disassembly of coprocessor instructions.
564 static bool LdStCopOpcode(unsigned Opcode) {
565 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
566 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
570 static bool CoprocessorOpcode(unsigned Opcode) {
571 if (LdStCopOpcode(Opcode))
577 case ARM::CDP: case ARM::CDP2:
578 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
579 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
583 static inline unsigned GetCoprocessor(uint32_t insn) {
584 return slice(insn, 11, 8);
586 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
587 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
589 static inline unsigned GetCopOpc2(uint32_t insn) {
590 return slice(insn, 7, 5);
592 static inline unsigned GetCopOpc(uint32_t insn) {
593 return slice(insn, 7, 4);
595 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
598 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
600 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
602 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
604 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
606 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
610 // LDC_OPTION: cop CRd Rn imm8
612 // STC_OPTION: cop CRd Rn imm8
615 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
616 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
618 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
620 unsigned &OpIdx = NumOpsAdded;
621 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
622 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
623 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
624 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
625 bool LdStCop = LdStCopOpcode(Opcode);
629 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
632 // Unindex if P:W = 0b00 --> _OPTION variant
633 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
635 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
637 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
641 MI.addOperand(MCOperand::CreateReg(0));
642 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
643 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
645 MI.addOperand(MCOperand::CreateImm(Offset));
648 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
652 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
653 : GetCopOpc1(insn, NoGPR)));
655 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
656 : MCOperand::CreateReg(
657 getRegisterEnum(B, ARM::GPRRegClassID,
660 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
661 getRegisterEnum(B, ARM::GPRRegClassID,
663 : MCOperand::CreateImm(decodeRn(insn)));
665 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
670 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
678 // Branch Instructions.
679 // BLr9: SignExtend(Imm24:'00', 32)
680 // Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
681 // SMC: ZeroExtend(imm4, 32)
682 // SVC: ZeroExtend(Imm24, 32)
684 // Various coprocessor instructions are assigned BrFrm arbitrarily.
685 // Delegates to DisassembleCoprocessor() helper function.
688 // MSR/MSRsys: Rm mask=Inst{19-16}
690 // MSRi/MSRsysi: so_imm
691 // SRSW/SRS: addrmode4:$addr mode_imm
692 // RFEW/RFE: addrmode4:$addr Rn
693 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
694 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
696 if (CoprocessorOpcode(Opcode))
697 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
699 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
700 if (!OpInfo) return false;
702 // MRS and MRSsys take one GPR reg Rd.
703 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
704 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
705 "Reg operand expected");
706 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
711 // BXJ takes one GPR reg Rm.
712 if (Opcode == ARM::BXJ) {
713 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
714 "Reg operand expected");
715 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
720 // MSR and MSRsys take one GPR reg Rm, followed by the mask.
721 if (Opcode == ARM::MSR || Opcode == ARM::MSRsys) {
722 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
723 "Reg operand expected");
724 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
726 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
730 // MSRi and MSRsysi take one so_imm operand, followed by the mask.
731 if (Opcode == ARM::MSRi || Opcode == ARM::MSRsysi) {
732 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
733 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
734 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
735 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
736 unsigned Imm = insn & 0xFF;
737 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
738 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
742 // SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the
743 // mode immediate (Inst{4-0}).
744 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
745 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
746 // ARMInstPrinter::printAddrMode4Operand() prints special mode string
747 // if the base register is SP; so don't set ARM::SP.
748 MI.addOperand(MCOperand::CreateReg(0));
749 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
750 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
752 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
753 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
755 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
761 assert((Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred
762 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
763 "Unexpected Opcode");
765 assert(NumOps >= 1 && OpInfo[0].RegClass == 0 && "Reg operand expected");
768 if (Opcode == ARM::SMC) {
769 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
770 Imm32 = slice(insn, 3, 0);
771 } else if (Opcode == ARM::SVC) {
772 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
773 Imm32 = slice(insn, 23, 0);
775 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
776 unsigned Imm26 = slice(insn, 23, 0) << 2;
777 //Imm32 = signextend<signed int, 26>(Imm26);
778 Imm32 = SignExtend32<26>(Imm26);
780 // When executing an ARM instruction, PC reads as the address of the current
781 // instruction plus 8. The assembler subtracts 8 from the difference
782 // between the branch instruction and the target address, disassembler has
783 // to add 8 to compensate.
787 MI.addOperand(MCOperand::CreateImm(Imm32));
793 // Misc. Branch Instructions.
794 // BR_JTadd, BR_JTr, BR_JTm
797 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
798 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
800 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
801 if (!OpInfo) return false;
803 unsigned &OpIdx = NumOpsAdded;
807 // BX_RET has only two predicate operands, do an early return.
808 if (Opcode == ARM::BX_RET)
811 // BLXr9 and BRIND take one GPR reg.
812 if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
813 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
814 "Reg operand expected");
815 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
821 // BR_JTadd is an ADD with Rd = PC, (Rn, Rm) as the target and index regs.
822 if (Opcode == ARM::BR_JTadd) {
823 // InOperandList with GPR:$target and GPR:$idx regs.
825 assert(NumOps == 4 && "Expect 4 operands");
826 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
828 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
831 // Fill in the two remaining imm operands to signify build completion.
832 MI.addOperand(MCOperand::CreateImm(0));
833 MI.addOperand(MCOperand::CreateImm(0));
839 // BR_JTr is a MOV with Rd = PC, and Rm as the source register.
840 if (Opcode == ARM::BR_JTr) {
841 // InOperandList with GPR::$target reg.
843 assert(NumOps == 3 && "Expect 3 operands");
844 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
847 // Fill in the two remaining imm operands to signify build completion.
848 MI.addOperand(MCOperand::CreateImm(0));
849 MI.addOperand(MCOperand::CreateImm(0));
855 // BR_JTm is an LDR with Rt = PC.
856 if (Opcode == ARM::BR_JTm) {
857 // This is the reg/reg form, with base reg followed by +/- reg shop imm.
858 // See also ARMAddressingModes.h (Addressing Mode #2).
860 assert(NumOps == 5 && getIBit(insn) == 1 && "Expect 5 operands && I-bit=1");
861 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
864 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
866 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
867 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
869 // Inst{6-5} encodes the shift opcode.
870 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
871 // Inst{11-7} encodes the imm5 shift amount.
872 unsigned ShImm = slice(insn, 11, 7);
874 // A8.4.1. Possible rrx or shift amount of 32...
875 getImmShiftSE(ShOp, ShImm);
876 MI.addOperand(MCOperand::CreateImm(
877 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
879 // Fill in the two remaining imm operands to signify build completion.
880 MI.addOperand(MCOperand::CreateImm(0));
881 MI.addOperand(MCOperand::CreateImm(0));
887 assert(0 && "Unexpected BrMiscFrm Opcode");
891 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
892 uint32_t lsb = slice(insn, 11, 7);
893 uint32_t msb = slice(insn, 20, 16);
896 errs() << "Encoding error: lsb > msb\n";
900 for (uint32_t i = lsb; i <= msb; ++i)
906 static inline bool SaturateOpcode(unsigned Opcode) {
908 case ARM::SSATlsl: case ARM::SSATasr: case ARM::SSAT16:
909 case ARM::USATlsl: case ARM::USATasr: case ARM::USAT16:
916 static inline unsigned decodeSaturatePos(unsigned Opcode, uint32_t insn) {
920 return slice(insn, 20, 16) + 1;
922 return slice(insn, 19, 16) + 1;
925 return slice(insn, 20, 16);
927 return slice(insn, 19, 16);
929 assert(0 && "Invalid opcode passed in");
934 // A major complication is the fact that some of the saturating add/subtract
935 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
936 // They are QADD, QDADD, QDSUB, and QSUB.
937 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
938 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
940 const TargetInstrDesc &TID = ARMInsts[Opcode];
941 unsigned short NumDefs = TID.getNumDefs();
942 bool isUnary = isUnaryDP(TID.TSFlags);
943 const TargetOperandInfo *OpInfo = TID.OpInfo;
944 unsigned &OpIdx = NumOpsAdded;
948 // Disassemble register def if there is one.
949 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
950 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
955 // Now disassemble the src operands.
959 // SSAT/SSAT16/USAT/USAT16 has imm operand after Rd.
960 if (SaturateOpcode(Opcode)) {
961 MI.addOperand(MCOperand::CreateImm(decodeSaturatePos(Opcode, insn)));
963 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
966 if (Opcode == ARM::SSAT16 || Opcode == ARM::USAT16) {
971 // For SSAT operand reg (Rm) has been disassembled above.
972 // Now disassemble the shift amount.
974 // Inst{11-7} encodes the imm5 shift amount.
975 unsigned ShAmt = slice(insn, 11, 7);
977 // A8.6.183. Possible ASR shift amount of 32...
978 if (Opcode == ARM::SSATasr && ShAmt == 0)
981 MI.addOperand(MCOperand::CreateImm(ShAmt));
987 // Special-case handling of BFC/BFI/SBFX/UBFX.
988 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
989 // TIED_TO operand skipped for BFC and Inst{3-0} (Reg) for BFI.
990 MI.addOperand(MCOperand::CreateReg(Opcode == ARM::BFC ? 0
991 : getRegisterEnum(B, ARM::GPRRegClassID,
994 if (!getBFCInvMask(insn, mask))
997 MI.addOperand(MCOperand::CreateImm(mask));
1001 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
1002 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1004 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
1005 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
1010 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
1011 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
1013 // BinaryDP has an Rn operand.
1015 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1016 "Reg operand expected");
1017 MI.addOperand(MCOperand::CreateReg(
1018 getRegisterEnum(B, ARM::GPRRegClassID,
1019 RmRn ? decodeRm(insn) : decodeRn(insn))));
1023 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
1024 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1025 MI.addOperand(MCOperand::CreateReg(0));
1029 // Now disassemble operand 2.
1030 if (OpIdx >= NumOps)
1033 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
1034 // We have a reg/reg form.
1035 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
1036 // routed here as well.
1037 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
1038 MI.addOperand(MCOperand::CreateReg(
1039 getRegisterEnum(B, ARM::GPRRegClassID,
1040 RmRn? decodeRn(insn) : decodeRm(insn))));
1042 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
1043 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
1044 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1045 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
1046 MI.addOperand(MCOperand::CreateImm(Imm16));
1049 // We have a reg/imm form.
1050 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
1051 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
1052 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
1053 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1054 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
1055 unsigned Imm = insn & 0xFF;
1056 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
1063 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1064 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1066 const TargetInstrDesc &TID = ARMInsts[Opcode];
1067 unsigned short NumDefs = TID.getNumDefs();
1068 bool isUnary = isUnaryDP(TID.TSFlags);
1069 const TargetOperandInfo *OpInfo = TID.OpInfo;
1070 unsigned &OpIdx = NumOpsAdded;
1074 // Disassemble register def if there is one.
1075 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
1076 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1081 // Disassemble the src operands.
1082 if (OpIdx >= NumOps)
1085 // BinaryDP has an Rn operand.
1087 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1088 "Reg operand expected");
1089 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1094 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
1095 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1096 MI.addOperand(MCOperand::CreateReg(0));
1100 // Disassemble operand 2, which consists of three components.
1101 if (OpIdx + 2 >= NumOps)
1104 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1105 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
1106 (OpInfo[OpIdx+2].RegClass == 0) &&
1107 "Expect 3 reg operands");
1109 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
1110 unsigned Rs = slice(insn, 4, 4);
1112 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1115 // Register-controlled shifts: [Rm, Rs, shift].
1116 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1118 // Inst{6-5} encodes the shift opcode.
1119 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1120 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
1122 // Constant shifts: [Rm, reg0, shift_imm].
1123 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
1124 // Inst{6-5} encodes the shift opcode.
1125 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1126 // Inst{11-7} encodes the imm5 shift amount.
1127 unsigned ShImm = slice(insn, 11, 7);
1129 // A8.4.1. Possible rrx or shift amount of 32...
1130 getImmShiftSE(ShOp, ShImm);
1131 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1138 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1139 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1141 const TargetInstrDesc &TID = ARMInsts[Opcode];
1142 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1143 const TargetOperandInfo *OpInfo = TID.OpInfo;
1144 if (!OpInfo) return false;
1146 unsigned &OpIdx = NumOpsAdded;
1150 assert(((!isStore && TID.getNumDefs() > 0) ||
1151 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1152 && "Invalid arguments");
1154 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1155 if (isPrePost && isStore) {
1156 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1157 "Reg operand expected");
1158 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1163 // Disassemble the dst/src operand.
1164 if (OpIdx >= NumOps)
1167 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1168 "Reg operand expected");
1169 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1173 // After dst of a pre- and post-indexed load is the address base writeback.
1174 if (isPrePost && !isStore) {
1175 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1176 "Reg operand expected");
1177 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1182 // Disassemble the base operand.
1183 if (OpIdx >= NumOps)
1186 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1187 "Reg operand expected");
1188 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1189 && "Index mode or tied_to operand expected");
1190 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1194 // For reg/reg form, base reg is followed by +/- reg shop imm.
1195 // For immediate form, it is followed by +/- imm12.
1196 // See also ARMAddressingModes.h (Addressing Mode #2).
1197 if (OpIdx + 1 >= NumOps)
1200 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1201 (OpInfo[OpIdx+1].RegClass == 0) &&
1202 "Expect 1 reg operand followed by 1 imm operand");
1204 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1205 if (getIBit(insn) == 0) {
1206 MI.addOperand(MCOperand::CreateReg(0));
1208 // Disassemble the 12-bit immediate offset.
1209 unsigned Imm12 = slice(insn, 11, 0);
1210 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
1211 MI.addOperand(MCOperand::CreateImm(Offset));
1213 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1214 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1216 // Inst{6-5} encodes the shift opcode.
1217 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1218 // Inst{11-7} encodes the imm5 shift amount.
1219 unsigned ShImm = slice(insn, 11, 7);
1221 // A8.4.1. Possible rrx or shift amount of 32...
1222 getImmShiftSE(ShOp, ShImm);
1223 MI.addOperand(MCOperand::CreateImm(
1224 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
1231 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1232 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1233 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1236 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1237 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1238 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1241 static bool HasDualReg(unsigned Opcode) {
1245 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1246 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1251 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1252 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1254 const TargetInstrDesc &TID = ARMInsts[Opcode];
1255 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1256 const TargetOperandInfo *OpInfo = TID.OpInfo;
1257 if (!OpInfo) return false;
1259 unsigned &OpIdx = NumOpsAdded;
1263 assert(((!isStore && TID.getNumDefs() > 0) ||
1264 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1265 && "Invalid arguments");
1267 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1268 if (isPrePost && isStore) {
1269 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1270 "Reg operand expected");
1271 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1276 bool DualReg = HasDualReg(Opcode);
1278 // Disassemble the dst/src operand.
1279 if (OpIdx >= NumOps)
1282 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1283 "Reg operand expected");
1284 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1288 // Fill in LDRD and STRD's second operand.
1290 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1291 decodeRd(insn) + 1)));
1295 // After dst of a pre- and post-indexed load is the address base writeback.
1296 if (isPrePost && !isStore) {
1297 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1298 "Reg operand expected");
1299 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1304 // Disassemble the base operand.
1305 if (OpIdx >= NumOps)
1308 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1309 "Reg operand expected");
1310 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1311 && "Index mode or tied_to operand expected");
1312 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1316 // For reg/reg form, base reg is followed by +/- reg.
1317 // For immediate form, it is followed by +/- imm8.
1318 // See also ARMAddressingModes.h (Addressing Mode #3).
1319 if (OpIdx + 1 >= NumOps)
1322 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1323 (OpInfo[OpIdx+1].RegClass == 0) &&
1324 "Expect 1 reg operand followed by 1 imm operand");
1326 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1327 if (getAM3IBit(insn) == 1) {
1328 MI.addOperand(MCOperand::CreateReg(0));
1330 // Disassemble the 8-bit immediate offset.
1331 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1332 unsigned Imm4L = insn & 0xF;
1333 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1334 MI.addOperand(MCOperand::CreateImm(Offset));
1336 // Disassemble the offset reg (Rm).
1337 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1339 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1340 MI.addOperand(MCOperand::CreateImm(Offset));
1347 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1348 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1349 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1353 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1354 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1355 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1358 // The algorithm for disassembly of LdStMulFrm is different from others because
1359 // it explicitly populates the two predicate operands after operand 0 (the base)
1360 // and operand 1 (the AM4 mode imm). After operand 3, we need to populate the
1361 // reglist with each affected register encoded as an MCOperand.
1362 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1363 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1365 assert(NumOps >= 5 && "LdStMulFrm expects NumOps >= 5");
1367 unsigned &OpIdx = NumOpsAdded;
1371 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1373 // Writeback to base, if necessary.
1374 if (Opcode == ARM::LDM_UPD || Opcode == ARM::STM_UPD) {
1375 MI.addOperand(MCOperand::CreateReg(Base));
1379 MI.addOperand(MCOperand::CreateReg(Base));
1381 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1382 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
1384 // Handling the two predicate operands before the reglist.
1385 int64_t CondVal = insn >> ARMII::CondShift;
1386 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1387 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1391 // Fill the variadic part of reglist.
1392 unsigned RegListBits = insn & ((1 << 16) - 1);
1393 for (unsigned i = 0; i < 16; ++i) {
1394 if ((RegListBits >> i) & 1) {
1395 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1404 // LDREX, LDREXB, LDREXH: Rd Rn
1405 // LDREXD: Rd Rd+1 Rn
1406 // STREX, STREXB, STREXH: Rd Rm Rn
1407 // STREXD: Rd Rm Rm+1 Rn
1409 // SWP, SWPB: Rd Rm Rn
1410 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1411 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1413 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1414 if (!OpInfo) return false;
1416 unsigned &OpIdx = NumOpsAdded;
1421 && OpInfo[0].RegClass == ARM::GPRRegClassID
1422 && OpInfo[1].RegClass == ARM::GPRRegClassID
1423 && "Expect 2 reg operands");
1425 bool isStore = slice(insn, 20, 20) == 0;
1426 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1428 // Add the destination operand.
1429 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1433 // Store register Exclusive needs a source operand.
1435 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1440 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1441 decodeRm(insn)+1)));
1445 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1446 decodeRd(insn)+1)));
1450 // Finally add the pointer operand.
1451 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1458 // Misc. Arithmetic Instructions.
1460 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1461 // RBIT, REV, REV16, REVSH: Rd Rm
1462 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1463 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1465 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1466 unsigned &OpIdx = NumOpsAdded;
1471 && OpInfo[0].RegClass == ARM::GPRRegClassID
1472 && OpInfo[1].RegClass == ARM::GPRRegClassID
1473 && "Expect 2 reg operands");
1475 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1477 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1482 assert(NumOps >= 4 && "Expect >= 4 operands");
1483 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1488 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1492 // If there is still an operand info left which is an immediate operand, add
1493 // an additional imm5 LSL/ASR operand.
1494 if (ThreeReg && OpInfo[OpIdx].RegClass == 0
1495 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1496 // Extract the 5-bit immediate field Inst{11-7}.
1497 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1498 MI.addOperand(MCOperand::CreateImm(ShiftAmt));
1505 // Extend instructions.
1506 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1507 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1508 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1509 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1510 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1512 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1513 unsigned &OpIdx = NumOpsAdded;
1518 && OpInfo[0].RegClass == ARM::GPRRegClassID
1519 && OpInfo[1].RegClass == ARM::GPRRegClassID
1520 && "Expect 2 reg operands");
1522 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1524 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1529 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1534 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1538 // If there is still an operand info left which is an immediate operand, add
1539 // an additional rotate immediate operand.
1540 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
1541 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1542 // Extract the 2-bit rotate field Inst{11-10}.
1543 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1544 // Rotation by 8, 16, or 24 bits.
1545 MI.addOperand(MCOperand::CreateImm(rot << 3));
1552 /////////////////////////////////////
1554 // Utility Functions For VFP //
1556 /////////////////////////////////////
1558 // Extract/Decode Dd/Sd:
1560 // SP => d = UInt(Vd:D)
1561 // DP => d = UInt(D:Vd)
1562 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1563 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1564 : (decodeRd(insn) | getDBit(insn) << 4);
1567 // Extract/Decode Dn/Sn:
1569 // SP => n = UInt(Vn:N)
1570 // DP => n = UInt(N:Vn)
1571 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1572 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1573 : (decodeRn(insn) | getNBit(insn) << 4);
1576 // Extract/Decode Dm/Sm:
1578 // SP => m = UInt(Vm:M)
1579 // DP => m = UInt(M:Vm)
1580 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1581 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1582 : (decodeRm(insn) | getMBit(insn) << 4);
1587 static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
1588 assert(N == 32 || N == 64);
1591 unsigned bit6 = slice(byte, 6, 6);
1593 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1595 Result |= 0x1f << 25;
1597 Result |= 0x1 << 30;
1599 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1600 (uint64_t)slice(byte, 5, 0) << 48;
1602 Result |= 0xffL << 54;
1604 Result |= 0x1L << 62;
1610 // VFP Unary Format Instructions:
1612 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1613 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1614 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1615 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1616 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1618 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1620 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1621 unsigned &OpIdx = NumOpsAdded;
1625 unsigned RegClass = OpInfo[OpIdx].RegClass;
1626 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1627 "Reg operand expected");
1628 bool isSP = (RegClass == ARM::SPRRegClassID);
1630 MI.addOperand(MCOperand::CreateReg(
1631 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1634 // Early return for compare with zero instructions.
1635 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1636 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1639 RegClass = OpInfo[OpIdx].RegClass;
1640 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1641 "Reg operand expected");
1642 isSP = (RegClass == ARM::SPRRegClassID);
1644 MI.addOperand(MCOperand::CreateReg(
1645 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1651 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1652 // Some of them have operand constraints which tie the first operand in the
1653 // InOperandList to that of the dst. As far as asm printing is concerned, this
1654 // tied_to operand is simply skipped.
1655 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1656 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1658 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1660 const TargetInstrDesc &TID = ARMInsts[Opcode];
1661 const TargetOperandInfo *OpInfo = TID.OpInfo;
1662 unsigned &OpIdx = NumOpsAdded;
1666 unsigned RegClass = OpInfo[OpIdx].RegClass;
1667 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1668 "Reg operand expected");
1669 bool isSP = (RegClass == ARM::SPRRegClassID);
1671 MI.addOperand(MCOperand::CreateReg(
1672 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1675 // Skip tied_to operand constraint.
1676 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1677 assert(NumOps >= 4 && "Expect >=4 operands");
1678 MI.addOperand(MCOperand::CreateReg(0));
1682 MI.addOperand(MCOperand::CreateReg(
1683 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1686 MI.addOperand(MCOperand::CreateReg(
1687 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1693 // A8.6.295 vcvt (floating-point <-> integer)
1694 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1695 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1697 // A8.6.297 vcvt (floating-point and fixed-point)
1698 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1699 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1700 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1702 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1704 const TargetInstrDesc &TID = ARMInsts[Opcode];
1705 const TargetOperandInfo *OpInfo = TID.OpInfo;
1706 if (!OpInfo) return false;
1708 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1709 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1710 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1714 assert(NumOps >= 3 && "Expect >= 3 operands");
1715 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1716 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1717 MI.addOperand(MCOperand::CreateReg(
1718 getRegisterEnum(B, RegClassID,
1719 decodeVFPRd(insn, SP))));
1721 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1722 "Tied to operand expected");
1723 MI.addOperand(MI.getOperand(0));
1725 assert(OpInfo[2].RegClass == 0 && !OpInfo[2].isPredicate() &&
1726 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1727 MI.addOperand(MCOperand::CreateImm(fbits));
1732 // The Rd (destination) and Rm (source) bits have different interpretations
1733 // depending on their single-precisonness.
1735 if (slice(insn, 18, 18) == 1) { // to_integer operation
1736 d = decodeVFPRd(insn, true /* Is Single Precision */);
1737 MI.addOperand(MCOperand::CreateReg(
1738 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1739 m = decodeVFPRm(insn, SP);
1740 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1742 d = decodeVFPRd(insn, SP);
1743 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1744 m = decodeVFPRm(insn, true /* Is Single Precision */);
1745 MI.addOperand(MCOperand::CreateReg(
1746 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1754 // VMOVRS - A8.6.330
1755 // Rt => Rd; Sn => UInt(Vn:N)
1756 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1757 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1759 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1761 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1763 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1764 decodeVFPRn(insn, true))));
1769 // VMOVRRD - A8.6.332
1770 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1772 // VMOVRRS - A8.6.331
1773 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1774 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1775 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1777 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1779 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1780 unsigned &OpIdx = NumOpsAdded;
1782 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1784 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1788 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1789 unsigned Sm = decodeVFPRm(insn, true);
1790 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1792 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1796 MI.addOperand(MCOperand::CreateReg(
1797 getRegisterEnum(B, ARM::DPRRegClassID,
1798 decodeVFPRm(insn, false))));
1804 // VMOVSR - A8.6.330
1805 // Rt => Rd; Sn => UInt(Vn:N)
1806 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1807 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1809 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1811 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1812 decodeVFPRn(insn, true))));
1813 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1819 // VMOVDRR - A8.6.332
1820 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1822 // VMOVRRS - A8.6.331
1823 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1824 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1825 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1827 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1829 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1830 unsigned &OpIdx = NumOpsAdded;
1834 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1835 unsigned Sm = decodeVFPRm(insn, true);
1836 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1838 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1842 MI.addOperand(MCOperand::CreateReg(
1843 getRegisterEnum(B, ARM::DPRRegClassID,
1844 decodeVFPRm(insn, false))));
1848 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1850 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1856 // VFP Load/Store Instructions.
1857 // VLDRD, VLDRS, VSTRD, VSTRS
1858 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1859 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1861 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1863 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS) ? true : false;
1864 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1866 // Extract Dd/Sd for operand 0.
1867 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1869 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1871 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1872 MI.addOperand(MCOperand::CreateReg(Base));
1874 // Next comes the AM5 Opcode.
1875 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1876 unsigned char Imm8 = insn & 0xFF;
1877 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1884 // VFP Load/Store Multiple Instructions.
1885 // This is similar to the algorithm for LDM/STM in that operand 0 (the base) and
1886 // operand 1 (the AM5 mode imm) is followed by two predicate operands. It is
1887 // followed by a reglist of either DPR(s) or SPR(s).
1889 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1890 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1891 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1893 assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
1895 unsigned &OpIdx = NumOpsAdded;
1899 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1901 // Writeback to base, if necessary.
1902 if (Opcode == ARM::VLDMD_UPD || Opcode == ARM::VLDMS_UPD ||
1903 Opcode == ARM::VSTMD_UPD || Opcode == ARM::VSTMS_UPD) {
1904 MI.addOperand(MCOperand::CreateReg(Base));
1908 MI.addOperand(MCOperand::CreateReg(Base));
1910 // Next comes the AM5 Opcode.
1911 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1912 unsigned char Imm8 = insn & 0xFF;
1913 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(SubMode, Imm8)));
1915 // Handling the two predicate operands before the reglist.
1916 int64_t CondVal = insn >> ARMII::CondShift;
1917 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1918 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1922 bool isSPVFP = (Opcode == ARM::VLDMS || Opcode == ARM::VLDMS_UPD ||
1923 Opcode == ARM::VSTMS || Opcode == ARM::VSTMS_UPD) ? true : false;
1924 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1927 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1929 // Fill the variadic part of reglist.
1930 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1931 for (unsigned i = 0; i < Regs; ++i) {
1932 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1940 // Misc. VFP Instructions.
1941 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1942 // FCONSTD (DPR and a VFPf64Imm operand)
1943 // FCONSTS (SPR and a VFPf32Imm operand)
1944 // VMRS/VMSR (GPR operand)
1945 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1946 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1948 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1949 unsigned &OpIdx = NumOpsAdded;
1953 if (Opcode == ARM::FMSTAT)
1956 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1958 unsigned RegEnum = 0;
1959 switch (OpInfo[0].RegClass) {
1960 case ARM::DPRRegClassID:
1961 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1963 case ARM::SPRRegClassID:
1964 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1966 case ARM::GPRRegClassID:
1967 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1970 assert(0 && "Invalid reg class id");
1974 MI.addOperand(MCOperand::CreateReg(RegEnum));
1977 // Extract/decode the f64/f32 immediate.
1978 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
1979 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1980 // The asm syntax specifies the before-expanded <imm>.
1981 // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1982 // Opcode == ARM::FCONSTD ? 64 : 32)
1983 MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0)));
1990 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
1991 #include "ThumbDisassemblerCore.h"
1993 /////////////////////////////////////////////////////
1995 // Utility Functions For ARM Advanced SIMD //
1997 /////////////////////////////////////////////////////
1999 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
2000 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
2002 // A7.3 Register encoding
2004 // Extract/Decode NEON D/Vd:
2006 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
2007 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
2008 // handling it in the getRegisterEnum() utility function.
2009 // D = Inst{22}, Vd = Inst{15-12}
2010 static unsigned decodeNEONRd(uint32_t insn) {
2011 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
2012 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
2015 // Extract/Decode NEON N/Vn:
2017 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
2018 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
2019 // handling it in the getRegisterEnum() utility function.
2020 // N = Inst{7}, Vn = Inst{19-16}
2021 static unsigned decodeNEONRn(uint32_t insn) {
2022 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
2023 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
2026 // Extract/Decode NEON M/Vm:
2028 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
2029 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
2030 // handling it in the getRegisterEnum() utility function.
2031 // M = Inst{5}, Vm = Inst{3-0}
2032 static unsigned decodeNEONRm(uint32_t insn) {
2033 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
2034 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
2045 } // End of unnamed namespace
2047 // size field -> Inst{11-10}
2048 // index_align field -> Inst{7-4}
2050 // The Lane Index interpretation depends on the Data Size:
2051 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
2052 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
2053 // 32 (encoded as size = 0b10) -> Index = index_align[3]
2055 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
2056 static unsigned decodeLaneIndex(uint32_t insn) {
2057 unsigned size = insn >> 10 & 3;
2058 assert((size == 0 || size == 1 || size == 2) &&
2059 "Encoding error: size should be either 0, 1, or 2");
2061 unsigned index_align = insn >> 4 & 0xF;
2062 return (index_align >> 1) >> size;
2065 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
2066 // op = Inst{5}, cmode = Inst{11-8}
2067 // i = Inst{24} (ARM architecture)
2068 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
2069 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
2070 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
2071 unsigned char cmode = (insn >> 8) & 0xF;
2072 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
2073 ((insn >> 16) & 7) << 4 |
2082 Imm64 = Imm8 << 8*(cmode >> 1 & 1);
2086 Imm64 = (Imm8 << 8) | 0xFF;
2087 else if (cmode == 13)
2088 Imm64 = (Imm8 << 16) | 0xFFFF;
2090 // Imm8 to be shifted left by how many bytes...
2091 Imm64 = Imm8 << 8*(cmode >> 1 & 3);
2096 for (unsigned i = 0; i < 8; ++i)
2097 if ((Imm8 >> i) & 1)
2098 Imm64 |= 0xFF << 8*i;
2102 assert(0 && "Unreachable code!");
2109 // A8.6.339 VMUL, VMULL (by scalar)
2110 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2111 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2112 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2119 assert(0 && "Unreachable code!");
2124 // A8.6.339 VMUL, VMULL (by scalar)
2125 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2126 // ESize32 => index = Inst{5} (M) D0-D15
2127 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2130 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2132 return (insn >> 5) & 1;
2134 assert(0 && "Unreachable code!");
2139 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2140 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2141 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2142 return 64 - ((insn >> 16) & 0x3F);
2145 // A8.6.302 VDUP (scalar)
2146 // ESize8 => index = Inst{19-17}
2147 // ESize16 => index = Inst{19-18}
2148 // ESize32 => index = Inst{19}
2149 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2152 return (insn >> 17) & 7;
2154 return (insn >> 18) & 3;
2156 return (insn >> 19) & 1;
2158 assert(0 && "Unspecified element size!");
2163 // A8.6.328 VMOV (ARM core register to scalar)
2164 // A8.6.329 VMOV (scalar to ARM core register)
2165 // ESize8 => index = Inst{21:6-5}
2166 // ESize16 => index = Inst{21:6}
2167 // ESize32 => index = Inst{21}
2168 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2171 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2173 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2175 return ((insn >> 21) & 1);
2177 assert(0 && "Unspecified element size!");
2182 // Imm6 = Inst{21-16}, L = Inst{7}
2184 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2186 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2187 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2188 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2189 // '1xxxxxx' => esize = 64; shift_amount = imm6
2191 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2193 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2194 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2195 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2196 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2198 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2199 ElemSize esize = ESizeNA;
2200 unsigned L = (insn >> 7) & 1;
2201 unsigned imm6 = (insn >> 16) & 0x3F;
2205 else if (imm6 >> 4 == 1)
2207 else if (imm6 >> 5 == 1)
2210 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2215 return esize == ESize64 ? imm6 : (imm6 - esize);
2217 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2221 // Imm4 = Inst{11-8}
2222 static unsigned decodeN3VImm(uint32_t insn) {
2223 return (insn >> 8) & 0xF;
2227 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2229 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2231 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2233 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2235 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2236 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2237 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2240 const TargetInstrDesc &TID = ARMInsts[Opcode];
2241 const TargetOperandInfo *OpInfo = TID.OpInfo;
2243 // At least one DPR register plus addressing mode #6.
2244 assert(NumOps >= 3 && "Expect >= 3 operands");
2246 unsigned &OpIdx = NumOpsAdded;
2250 // We have homogeneous NEON registers for Load/Store.
2251 unsigned RegClass = 0;
2253 // Double-spaced registers have increments of 2.
2254 unsigned Inc = DblSpaced ? 2 : 1;
2256 unsigned Rn = decodeRn(insn);
2257 unsigned Rm = decodeRm(insn);
2258 unsigned Rd = decodeNEONRd(insn);
2260 // A7.7.1 Advanced SIMD addressing mode.
2263 // LLVM Addressing Mode #6.
2264 unsigned RmEnum = 0;
2266 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2269 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2270 // then possible lane index.
2271 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2272 "Reg operand expected");
2275 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2280 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2281 OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected");
2282 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2284 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2288 MI.addOperand(MCOperand::CreateReg(RmEnum));
2292 assert(OpIdx < NumOps &&
2293 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2294 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2295 "Reg operand expected");
2297 RegClass = OpInfo[OpIdx].RegClass;
2298 while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
2299 if (Opcode >= ARM::VST1q16 && Opcode <= ARM::VST1q8)
2300 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
2303 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,Rd)));
2308 // Handle possible lane index.
2309 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2310 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2311 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2316 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2317 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2318 RegClass = OpInfo[0].RegClass;
2320 while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
2321 if (Opcode >= ARM::VLD1q16 && Opcode <= ARM::VLD1q8)
2322 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
2325 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd)));
2331 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2336 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2337 OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected");
2338 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2340 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2344 MI.addOperand(MCOperand::CreateReg(RmEnum));
2348 while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
2349 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2350 "Tied to operand expected");
2351 MI.addOperand(MCOperand::CreateReg(0));
2355 // Handle possible lane index.
2356 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2357 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2358 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2367 // If L (Inst{21}) == 0, store instructions.
2368 // Find out about double-spaced-ness of the Opcode and pass it on to
2369 // DisassembleNLdSt0().
2370 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2371 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2373 const StringRef Name = ARMInsts[Opcode].Name;
2374 bool DblSpaced = false;
2376 if (Name.find("LN") != std::string::npos) {
2377 // To one lane instructions.
2378 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2380 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2381 if (Name.endswith("16") || Name.endswith("16_UPD"))
2382 DblSpaced = slice(insn, 5, 5) == 1;
2384 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2385 if (Name.endswith("32") || Name.endswith("32_UPD"))
2386 DblSpaced = slice(insn, 6, 6) == 1;
2389 // Multiple n-element structures with type encoded as Inst{11-8}.
2390 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2392 // n == 2 && type == 0b1001 -> DblSpaced = true
2393 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2394 DblSpaced = slice(insn, 11, 8) == 9;
2396 // n == 3 && type == 0b0101 -> DblSpaced = true
2397 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2398 DblSpaced = slice(insn, 11, 8) == 5;
2400 // n == 4 && type == 0b0001 -> DblSpaced = true
2401 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2402 DblSpaced = slice(insn, 11, 8) == 1;
2405 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2406 slice(insn, 21, 21) == 0, DblSpaced, B);
2411 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2412 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2414 const TargetInstrDesc &TID = ARMInsts[Opcode];
2415 const TargetOperandInfo *OpInfo = TID.OpInfo;
2417 assert(NumOps >= 2 &&
2418 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2419 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2420 (OpInfo[1].RegClass == 0) &&
2421 "Expect 1 reg operand followed by 1 imm operand");
2423 // Qd/Dd = Inst{22:15-12} => NEON Rd
2424 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2425 decodeNEONRd(insn))));
2427 ElemSize esize = ESizeNA;
2430 case ARM::VMOVv16i8:
2433 case ARM::VMOVv4i16:
2434 case ARM::VMOVv8i16:
2437 case ARM::VMOVv2i32:
2438 case ARM::VMOVv4i32:
2441 case ARM::VMOVv1i64:
2442 case ARM::VMOVv2i64:
2445 assert(0 && "Unreachable code!");
2449 // One register and a modified immediate value.
2450 // Add the imm operand.
2451 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2461 N2V_VectorConvert_Between_Float_Fixed
2463 } // End of unnamed namespace
2465 // Vector Convert [between floating-point and fixed-point]
2466 // Qd/Dd Qm/Dm [fbits]
2468 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2469 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2472 // Vector Move Long:
2475 // Vector Move Narrow:
2479 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2480 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2482 const TargetInstrDesc &TID = ARMInsts[Opc];
2483 const TargetOperandInfo *OpInfo = TID.OpInfo;
2485 assert(NumOps >= 2 &&
2486 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2487 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2488 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2489 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2490 "Expect >= 2 operands and first 2 as reg operands");
2492 unsigned &OpIdx = NumOpsAdded;
2496 ElemSize esize = ESizeNA;
2497 if (Flag == N2V_VectorDupLane) {
2498 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2499 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2500 "Unexpected Opcode");
2501 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2502 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2506 // Qd/Dd = Inst{22:15-12} => NEON Rd
2507 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2508 decodeNEONRd(insn))));
2512 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2514 MI.addOperand(MCOperand::CreateReg(0));
2518 // Dm = Inst{5:3-0} => NEON Rm
2519 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2520 decodeNEONRm(insn))));
2523 // VZIP and others have two TIED_TO reg operands.
2525 while (OpIdx < NumOps &&
2526 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2527 // Add TIED_TO operand.
2528 MI.addOperand(MI.getOperand(Idx));
2532 // Add the imm operand, if required.
2533 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2534 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2536 unsigned imm = 0xFFFFFFFF;
2538 if (Flag == N2V_VectorDupLane)
2539 imm = decodeNVLaneDupIndex(insn, esize);
2540 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2541 imm = decodeVCVTFractionBits(insn);
2543 assert(imm != 0xFFFFFFFF && "Internal error");
2544 MI.addOperand(MCOperand::CreateImm(imm));
2551 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2552 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2554 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2557 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2558 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2560 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2561 N2V_VectorConvert_Between_Float_Fixed, B);
2563 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2564 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2566 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2567 N2V_VectorDupLane, B);
2570 // Vector Shift [Accumulate] Instructions.
2571 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2573 // Vector Shift Left Long (with maximum shift count) Instructions.
2574 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2576 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2577 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2579 const TargetInstrDesc &TID = ARMInsts[Opcode];
2580 const TargetOperandInfo *OpInfo = TID.OpInfo;
2582 assert(NumOps >= 3 &&
2583 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2584 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2585 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2586 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2587 "Expect >= 3 operands and first 2 as reg operands");
2589 unsigned &OpIdx = NumOpsAdded;
2593 // Qd/Dd = Inst{22:15-12} => NEON Rd
2594 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2595 decodeNEONRd(insn))));
2598 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2600 MI.addOperand(MCOperand::CreateReg(0));
2604 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2605 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2606 "Reg operand expected");
2608 // Qm/Dm = Inst{5:3-0} => NEON Rm
2609 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2610 decodeNEONRm(insn))));
2613 assert(OpInfo[OpIdx].RegClass == 0 && "Imm operand expected");
2615 // Add the imm operand.
2617 // VSHLL has maximum shift count as the imm, inferred from its size.
2621 Imm = decodeNVSAmt(insn, LeftShift);
2633 MI.addOperand(MCOperand::CreateImm(Imm));
2639 // Left shift instructions.
2640 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2641 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2643 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2646 // Right shift instructions have different shift amount interpretation.
2647 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2648 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2650 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2659 N3V_Multiply_By_Scalar
2661 } // End of unnamed namespace
2663 // NEON Three Register Instructions with Optional Immediate Operand
2665 // Vector Extract Instructions.
2666 // Qd/Dd Qn/Dn Qm/Dm imm4
2668 // Vector Shift (Register) Instructions.
2669 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2671 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2672 // Qd/Dd Qn/Dn RestrictedDm index
2675 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2676 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2678 const TargetInstrDesc &TID = ARMInsts[Opcode];
2679 const TargetOperandInfo *OpInfo = TID.OpInfo;
2681 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2682 assert(NumOps >= 3 &&
2683 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2684 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2685 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2686 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2687 "Expect >= 3 operands and first 2 as reg operands");
2689 unsigned &OpIdx = NumOpsAdded;
2693 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2694 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2695 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2696 ElemSize esize = ESizeNA;
2697 if (Flag == N3V_Multiply_By_Scalar) {
2698 unsigned size = (insn >> 20) & 3;
2699 if (size == 1) esize = ESize16;
2700 if (size == 2) esize = ESize32;
2701 assert (esize == ESize16 || esize == ESize32);
2704 // Qd/Dd = Inst{22:15-12} => NEON Rd
2705 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2706 decodeNEONRd(insn))));
2709 // VABA, VABAL, VBSLd, VBSLq, ...
2710 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2712 MI.addOperand(MCOperand::CreateReg(0));
2716 // Dn = Inst{7:19-16} => NEON Rn
2718 // Dm = Inst{5:3-0} => NEON Rm
2719 MI.addOperand(MCOperand::CreateReg(
2720 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2721 VdVnVm ? decodeNEONRn(insn)
2722 : decodeNEONRm(insn))));
2725 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2727 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2730 // Dm = Inst{5:3-0} => NEON Rm
2732 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2734 // Dn = Inst{7:19-16} => NEON Rn
2735 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2736 : decodeNEONRm(insn))
2737 : decodeNEONRn(insn);
2739 MI.addOperand(MCOperand::CreateReg(
2740 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2743 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
2744 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2745 // Add the imm operand.
2748 Imm = decodeN3VImm(insn);
2749 else if (IsDmRestricted)
2750 Imm = decodeRestrictedDmIndex(insn, esize);
2752 assert(0 && "Internal error: unreachable code!");
2756 MI.addOperand(MCOperand::CreateImm(Imm));
2763 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2764 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2766 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2769 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2770 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2772 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2773 N3V_VectorShift, B);
2775 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2776 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2778 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2779 N3V_VectorExtract, B);
2781 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2782 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2784 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2785 N3V_Multiply_By_Scalar, B);
2788 // Vector Table Lookup
2790 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2791 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2792 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2793 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2794 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2795 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2797 const TargetInstrDesc &TID = ARMInsts[Opcode];
2798 const TargetOperandInfo *OpInfo = TID.OpInfo;
2799 if (!OpInfo) return false;
2801 assert(NumOps >= 3 &&
2802 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2803 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2804 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2805 "Expect >= 3 operands and first 3 as reg operands");
2807 unsigned &OpIdx = NumOpsAdded;
2811 unsigned Rn = decodeNEONRn(insn);
2813 // {Dn} encoded as len = 0b00
2814 // {Dn Dn+1} encoded as len = 0b01
2815 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2816 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2817 unsigned Len = slice(insn, 9, 8) + 1;
2819 // Dd (the destination vector)
2820 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2821 decodeNEONRd(insn))));
2824 // Process tied_to operand constraint.
2826 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2827 MI.addOperand(MI.getOperand(Idx));
2831 // Do the <list> now.
2832 for (unsigned i = 0; i < Len; ++i) {
2833 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2834 "Reg operand expected");
2835 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2840 // Dm (the index vector)
2841 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2842 "Reg operand (index vector) expected");
2843 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2844 decodeNEONRm(insn))));
2850 static bool DisassembleNEONFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2851 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
2852 assert(0 && "Unreachable code!");
2856 // Vector Get Lane (move scalar to ARM core register) Instructions.
2857 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2858 static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2859 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2861 const TargetInstrDesc &TID = ARMInsts[Opcode];
2862 const TargetOperandInfo *OpInfo = TID.OpInfo;
2863 if (!OpInfo) return false;
2865 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2866 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2867 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2868 OpInfo[2].RegClass == 0 &&
2869 "Expect >= 3 operands with one dst operand");
2872 Opcode == ARM::VGETLNi32 ? ESize32
2873 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2876 // Rt = Inst{15-12} => ARM Rd
2877 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2880 // Dn = Inst{7:19-16} => NEON Rn
2881 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2882 decodeNEONRn(insn))));
2884 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2890 // Vector Set Lane (move ARM core register to scalar) Instructions.
2891 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2892 static bool DisassembleNEONSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2893 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2895 const TargetInstrDesc &TID = ARMInsts[Opcode];
2896 const TargetOperandInfo *OpInfo = TID.OpInfo;
2897 if (!OpInfo) return false;
2899 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2900 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2901 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2902 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2903 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2904 OpInfo[3].RegClass == 0 &&
2905 "Expect >= 3 operands with one dst operand");
2908 Opcode == ARM::VSETLNi8 ? ESize8
2909 : (Opcode == ARM::VSETLNi16 ? ESize16
2912 // Dd = Inst{7:19-16} => NEON Rn
2913 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2914 decodeNEONRn(insn))));
2917 MI.addOperand(MCOperand::CreateReg(0));
2919 // Rt = Inst{15-12} => ARM Rd
2920 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2923 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2929 // Vector Duplicate Instructions (from ARM core register to all elements).
2930 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2931 static bool DisassembleNEONDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2932 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2934 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2936 assert(NumOps >= 2 &&
2937 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2938 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2939 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2940 "Expect >= 2 operands and first 2 as reg operand");
2942 unsigned RegClass = OpInfo[0].RegClass;
2944 // Qd/Dd = Inst{7:19-16} => NEON Rn
2945 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2946 decodeNEONRn(insn))));
2948 // Rt = Inst{15-12} => ARM Rd
2949 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2959 static inline bool MemBarrierInstr(uint32_t insn) {
2960 unsigned op7_4 = slice(insn, 7, 4);
2961 if (slice(insn, 31, 20) == 0xf57 && (op7_4 >= 4 && op7_4 <= 6))
2967 static inline bool PreLoadOpcode(unsigned Opcode) {
2969 case ARM::PLDi: case ARM::PLDr:
2970 case ARM::PLDWi: case ARM::PLDWr:
2971 case ARM::PLIi: case ARM::PLIr:
2978 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2979 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2981 // Preload Data/Instruction requires either 2 or 4 operands.
2982 // PLDi, PLDWi, PLIi: Rn [+/-]imm12 add = (U == '1')
2983 // PLDr[a|m], PLDWr[a|m], PLIr[a|m]: Rn Rm addrmode2_opc
2985 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2988 if (Opcode == ARM::PLDi || Opcode == ARM::PLDWi || Opcode == ARM::PLIi) {
2989 unsigned Imm12 = slice(insn, 11, 0);
2990 bool Negative = getUBit(insn) == 0;
2991 int Offset = Negative ? -1 - Imm12 : 1 * Imm12;
2992 MI.addOperand(MCOperand::CreateImm(Offset));
2995 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2998 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
3000 // Inst{6-5} encodes the shift opcode.
3001 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
3002 // Inst{11-7} encodes the imm5 shift amount.
3003 unsigned ShImm = slice(insn, 11, 7);
3005 // A8.4.1. Possible rrx or shift amount of 32...
3006 getImmShiftSE(ShOp, ShImm);
3007 MI.addOperand(MCOperand::CreateImm(
3008 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
3015 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
3016 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
3018 if (MemBarrierInstr(insn))
3036 // CPS has a singleton $opt operand that contains the following information:
3037 // opt{4-0} = mode from Inst{4-0}
3038 // opt{5} = changemode from Inst{17}
3039 // opt{8-6} = AIF from Inst{8-6}
3040 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3041 if (Opcode == ARM::CPS) {
3042 unsigned Option = slice(insn, 4, 0) | slice(insn, 17, 17) << 5 |
3043 slice(insn, 8, 6) << 6 | slice(insn, 19, 18) << 9;
3044 MI.addOperand(MCOperand::CreateImm(Option));
3049 // DBG has its option specified in Inst{3-0}.
3050 if (Opcode == ARM::DBG) {
3051 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3056 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
3057 if (Opcode == ARM::BKPT) {
3058 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
3059 slice(insn, 3, 0)));
3064 if (PreLoadOpcode(Opcode))
3065 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
3067 assert(0 && "Unexpected misc instruction!");
3071 static bool DisassembleThumbMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
3072 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
3074 assert(0 && "Unexpected thumb misc. instruction!");
3078 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
3079 /// We divide the disassembly task into different categories, with each one
3080 /// corresponding to a specific instruction encoding format. There could be
3081 /// exceptions when handling a specific format, and that is why the Opcode is
3082 /// also present in the function prototype.
3083 static const DisassembleFP FuncPtrs[] = {
3087 &DisassembleBrMiscFrm,
3089 &DisassembleDPSoRegFrm,
3092 &DisassembleLdMiscFrm,
3093 &DisassembleStMiscFrm,
3094 &DisassembleLdStMulFrm,
3095 &DisassembleLdStExFrm,
3096 &DisassembleArithMiscFrm,
3098 &DisassembleVFPUnaryFrm,
3099 &DisassembleVFPBinaryFrm,
3100 &DisassembleVFPConv1Frm,
3101 &DisassembleVFPConv2Frm,
3102 &DisassembleVFPConv3Frm,
3103 &DisassembleVFPConv4Frm,
3104 &DisassembleVFPConv5Frm,
3105 &DisassembleVFPLdStFrm,
3106 &DisassembleVFPLdStMulFrm,
3107 &DisassembleVFPMiscFrm,
3108 &DisassembleThumbFrm,
3109 &DisassembleNEONFrm,
3110 &DisassembleNEONGetLnFrm,
3111 &DisassembleNEONSetLnFrm,
3112 &DisassembleNEONDupFrm,
3113 &DisassembleMiscFrm,
3114 &DisassembleThumbMiscFrm,
3116 // VLD and VST (including one lane) Instructions.
3119 // A7.4.6 One register and a modified immediate value
3120 // 1-Register Instructions with imm.
3121 // LLVM only defines VMOVv instructions.
3122 &DisassembleN1RegModImmFrm,
3124 // 2-Register Instructions with no imm.
3125 &DisassembleN2RegFrm,
3127 // 2-Register Instructions with imm (vector convert float/fixed point).
3128 &DisassembleNVCVTFrm,
3130 // 2-Register Instructions with imm (vector dup lane).
3131 &DisassembleNVecDupLnFrm,
3133 // Vector Shift Left Instructions.
3134 &DisassembleN2RegVecShLFrm,
3136 // Vector Shift Righ Instructions, which has different interpretation of the
3137 // shift amount from the imm6 field.
3138 &DisassembleN2RegVecShRFrm,
3140 // 3-Register Data-Processing Instructions.
3141 &DisassembleN3RegFrm,
3143 // Vector Shift (Register) Instructions.
3144 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3145 &DisassembleN3RegVecShFrm,
3147 // Vector Extract Instructions.
3148 &DisassembleNVecExtractFrm,
3150 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3151 // By Scalar Instructions.
3152 &DisassembleNVecMulScalarFrm,
3154 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3155 // values in a table and generate a new vector.
3156 &DisassembleNVTBLFrm,
3161 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3162 /// The general idea is to set the Opcode for the MCInst, followed by adding
3163 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3164 /// to the Format-specific disassemble function for disassembly, followed by
3165 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3166 /// which follow the Dst/Src Operands.
3167 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3168 // Stage 1 sets the Opcode.
3169 MI.setOpcode(Opcode);
3170 // If the number of operands is zero, we're done!
3174 // Stage 2 calls the format-specific disassemble function to build the operand
3178 unsigned NumOpsAdded = 0;
3179 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3181 if (!OK || this->Err != 0) return false;
3182 if (NumOpsAdded >= NumOps)
3185 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3186 // FIXME: Should this be done selectively?
3187 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3190 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3191 uint32_t insn, unsigned short NumOpsRemaining) {
3193 assert(NumOpsRemaining > 0 && "Invalid argument");
3195 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3196 const std::string &Name = ARMInsts[Opcode].Name;
3197 unsigned Idx = MI.getNumOperands();
3199 // First, we check whether this instr specifies the PredicateOperand through
3200 // a pair of TargetOperandInfos with isPredicate() property.
3201 if (NumOpsRemaining >= 2 &&
3202 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3203 OpInfo[Idx].RegClass == 0 && OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3205 // If we are inside an IT block, get the IT condition bits maintained via
3206 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3209 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3211 if (Name.length() > 1 && Name[0] == 't') {
3212 // Thumb conditional branch instructions have their cond field embedded,
3216 if (Name == "t2Bcc")
3217 MI.addOperand(MCOperand::CreateImm(slice(insn, 25, 22)));
3218 else if (Name == "tBcc")
3219 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 8)));
3221 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3223 // ARM Instructions. Check condition field.
3224 int64_t CondVal = getCondField(insn);
3226 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3228 MI.addOperand(MCOperand::CreateImm(CondVal));
3231 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3233 NumOpsRemaining -= 2;
3234 if (NumOpsRemaining == 0)
3238 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3239 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3240 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3244 if (NumOpsRemaining == 0)
3250 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3251 /// after BuildIt is finished.
3252 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3255 if (!SP) return Status;
3257 if (Opcode == ARM::t2IT)
3258 SP->InitIT(slice(insn, 7, 0));
3259 else if (InITBlock())
3265 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3266 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3268 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3269 unsigned Idx = (unsigned)format;
3270 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3271 Disasm = FuncPtrs[Idx];
3274 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3275 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3276 /// Return NULL if it fails to create/return a proper builder. API clients
3277 /// are responsible for freeing up of the allocated memory. Cacheing can be
3278 /// performed by the API clients to improve performance.
3279 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3280 // For "Unknown format", fail by returning a NULL pointer.
3281 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1))
3284 return new ARMBasicMCBuilder(Opcode, Format,
3285 ARMInsts[Opcode].getNumOperands());