1 //===- ARMDisassemblerCore.h - ARM disassembler helpers ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
12 // The first part defines the enumeration type of ARM instruction format, which
13 // specifies the encoding used by the instruction, as well as a helper function
14 // to convert the enums to printable char strings.
16 // It also contains code to represent the concepts of Builder and DisassembleFP
17 // to solve the problem of disassembling an ARM instr.
19 //===----------------------------------------------------------------------===//
21 #ifndef ARMDISASSEMBLERCORE_H
22 #define ARMDISASSEMBLERCORE_H
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "ARMBaseInstrInfo.h"
27 #include "ARMRegisterInfo.h"
28 #include "ARMDisassembler.h"
34 static const char *OpcodeName(unsigned Opcode);
37 /////////////////////////////////////////////////////
39 // Enums and Utilities for ARM Instruction Format //
41 /////////////////////////////////////////////////////
44 ENTRY(ARM_FORMAT_PSEUDO, 0) \
45 ENTRY(ARM_FORMAT_MULFRM, 1) \
46 ENTRY(ARM_FORMAT_BRFRM, 2) \
47 ENTRY(ARM_FORMAT_BRMISCFRM, 3) \
48 ENTRY(ARM_FORMAT_DPFRM, 4) \
49 ENTRY(ARM_FORMAT_DPSOREGFRM, 5) \
50 ENTRY(ARM_FORMAT_LDFRM, 6) \
51 ENTRY(ARM_FORMAT_STFRM, 7) \
52 ENTRY(ARM_FORMAT_LDMISCFRM, 8) \
53 ENTRY(ARM_FORMAT_STMISCFRM, 9) \
54 ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
55 ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
56 ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
57 ENTRY(ARM_FORMAT_EXTFRM, 13) \
58 ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
59 ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
60 ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
61 ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
62 ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
63 ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
64 ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
65 ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
66 ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
67 ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
68 ENTRY(ARM_FORMAT_THUMBFRM, 24) \
69 ENTRY(ARM_FORMAT_NEONFRM, 25) \
70 ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
71 ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
72 ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
73 ENTRY(ARM_FORMAT_MISCFRM, 29) \
74 ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
75 ENTRY(ARM_FORMAT_NLdSt, 31) \
76 ENTRY(ARM_FORMAT_N1RegModImm, 32) \
77 ENTRY(ARM_FORMAT_N2Reg, 33) \
78 ENTRY(ARM_FORMAT_NVCVT, 34) \
79 ENTRY(ARM_FORMAT_NVecDupLn, 35) \
80 ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
81 ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
82 ENTRY(ARM_FORMAT_N3Reg, 38) \
83 ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
84 ENTRY(ARM_FORMAT_NVecExtract, 40) \
85 ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
86 ENTRY(ARM_FORMAT_NVTBL, 42)
88 // ARM instruction format specifies the encoding used by the instruction.
89 #define ENTRY(n, v) n = v,
96 // Converts enum to const char*.
97 static const inline char *stringForARMFormat(ARMFormat form) {
98 #define ENTRY(n, v) case n: return #n;
108 /// Expands on the enum definitions from ARMBaseInstrInfo.h.
109 /// They are being used by the disassembler implementation.
114 NEON_RegRdShift = 12,
115 NEON_D_BitShift = 22,
116 NEON_RegRnShift = 16,
123 /// Utility function for extracting [From, To] bits from a uint32_t.
124 static inline unsigned slice(uint32_t Bits, unsigned From, unsigned To) {
125 assert(From < 32 && To < 32 && From >= To);
126 return (Bits >> To) & ((1 << (From - To + 1)) - 1);
129 /// Utility function for setting [From, To] bits to Val for a uint32_t.
130 static inline void setSlice(uint32_t &Bits, unsigned From, unsigned To,
132 assert(From < 32 && To < 32 && From >= To);
133 uint32_t Mask = ((1 << (From - To + 1)) - 1);
134 Bits &= ~(Mask << To);
135 Bits |= (Val & Mask) << To;
138 /// Various utilities for checking the target specific flags.
140 /// A unary data processing instruction doesn't have an Rn operand.
141 static inline bool isUnaryDP(uint64_t TSFlags) {
142 return (TSFlags & ARMII::UnaryDP);
145 /// This four-bit field describes the addressing mode used.
146 /// See also ARMBaseInstrInfo.h.
147 static inline unsigned getAddrMode(uint64_t TSFlags) {
148 return (TSFlags & ARMII::AddrModeMask);
151 /// {IndexModePre, IndexModePost}
152 /// Only valid for load and store ops.
153 /// See also ARMBaseInstrInfo.h.
154 static inline unsigned getIndexMode(uint64_t TSFlags) {
155 return (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
158 /// Pre-/post-indexed operations define an extra $base_wb in the OutOperandList.
159 static inline bool isPrePostLdSt(uint64_t TSFlags) {
160 return (TSFlags & ARMII::IndexModeMask) != 0;
163 // Forward declaration.
164 class ARMBasicMCBuilder;
166 // Builder Object is mostly ignored except in some Thumb disassemble functions.
167 typedef ARMBasicMCBuilder *BO;
169 /// DisassembleFP - DisassembleFP points to a function that disassembles an insn
170 /// and builds the MCOperand list upon disassembly. It returns false on failure
171 /// or true on success. The number of operands added is updated upon success.
172 typedef bool (*DisassembleFP)(MCInst &MI, unsigned Opcode, uint32_t insn,
173 unsigned short NumOps, unsigned &NumOpsAdded, BO Builder);
175 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
176 /// infrastructure of an MCInst given the Opcode and Format of the instr.
177 /// Return NULL if it fails to create/return a proper builder. API clients
178 /// are responsible for freeing up of the allocated memory. Cacheing can be
179 /// performed by the API clients to improve performance.
180 extern ARMBasicMCBuilder *CreateMCBuilder(unsigned Opcode, ARMFormat Format);
182 /// ARMBasicMCBuilder - ARMBasicMCBuilder represents an ARM MCInst builder that
183 /// knows how to build up the MCOperand list.
184 class ARMBasicMCBuilder {
185 friend ARMBasicMCBuilder *CreateMCBuilder(unsigned Opcode, ARMFormat Format);
188 unsigned short NumOps;
189 DisassembleFP Disasm;
191 int Err; // !=0 if the builder encounters some error condition during build.
194 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
195 ARMBasicMCBuilder(unsigned opc, ARMFormat format, unsigned short num);
198 ARMBasicMCBuilder(ARMBasicMCBuilder &B)
199 : Opcode(B.Opcode), Format(B.Format), NumOps(B.NumOps), Disasm(B.Disasm),
204 virtual ~ARMBasicMCBuilder() {}
206 void SetSession(Session *sp) {
210 void SetErr(int ErrCode) {
214 /// DoPredicateOperands - DoPredicateOperands process the predicate operands
215 /// of some Thumb instructions which come before the reglist operands. It
216 /// returns true if the two predicate operands have been processed.
217 bool DoPredicateOperands(MCInst& MI, unsigned Opcode,
218 uint32_t insn, unsigned short NumOpsRemaning);
220 /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
221 /// the possible Predicate and SBitModifier, to build the remaining MCOperand
223 bool TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
224 uint32_t insn, unsigned short NumOpsRemaning);
226 /// InITBlock - InITBlock returns true if we are inside an IT block.
229 return SP->ITCounter > 0;
234 /// Build - Build delegates to BuildIt to perform the heavy liftling. After
235 /// that, it invokes RunBuildAfterHook where some housekeepings can be done.
236 virtual bool Build(MCInst &MI, uint32_t insn) {
237 bool Status = BuildIt(MI, insn);
238 return RunBuildAfterHook(Status, MI, insn);
241 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
242 /// The general idea is to set the Opcode for the MCInst, followed by adding
243 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
244 /// to the Format-specific disassemble function for disassembly, followed by
245 /// TryPredicateAndSBitModifier() for PredicateOperand and OptionalDefOperand
246 /// which follow the Dst/Src Operands.
247 virtual bool BuildIt(MCInst &MI, uint32_t insn);
249 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
250 /// after BuildIt is finished.
251 virtual bool RunBuildAfterHook(bool Status, MCInst &MI, uint32_t insn);
254 /// Get condition of the current IT instruction.
255 unsigned GetITCond() {
257 return slice(SP->ITState, 7, 4);