1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #include "ARMGenAsmWriter.inc"
30 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
32 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
33 static unsigned translateShiftImm(unsigned imm) {
34 // lsr #32 and asr #32 exist, but should be encoded as a 0.
35 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
42 /// Prints the shift value with an immediate value.
43 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
44 unsigned ShImm, bool UseMarkup) {
45 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
49 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
50 O << getShiftOpcStr(ShOpc);
52 if (ShOpc != ARM_AM::rrx) {
56 O << "#" << translateShiftImm(ShImm);
62 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
63 const MCRegisterInfo &MRI)
64 : MCInstPrinter(MAI, MII, MRI) {}
66 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
67 OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
70 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
71 StringRef Annot, const MCSubtargetInfo &STI) {
72 unsigned Opcode = MI->getOpcode();
76 // Check for HINT instructions w/ canonical names.
80 switch (MI->getOperand(0).getImm()) {
97 if (STI.getFeatureBits()[ARM::HasV8Ops]) {
100 } // Fallthrough for non-v8
102 // Anything else should just print normally.
103 printInstruction(MI, STI, O);
104 printAnnotation(O, Annot);
107 printPredicateOperand(MI, 1, STI, O);
108 if (Opcode == ARM::t2HINT)
110 printAnnotation(O, Annot);
113 // Check for MOVs and print canonical forms, instead.
115 // FIXME: Thumb variants?
116 const MCOperand &Dst = MI->getOperand(0);
117 const MCOperand &MO1 = MI->getOperand(1);
118 const MCOperand &MO2 = MI->getOperand(2);
119 const MCOperand &MO3 = MI->getOperand(3);
121 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
122 printSBitModifierOperand(MI, 6, STI, O);
123 printPredicateOperand(MI, 4, STI, O);
126 printRegName(O, Dst.getReg());
128 printRegName(O, MO1.getReg());
131 printRegName(O, MO2.getReg());
132 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
133 printAnnotation(O, Annot);
138 // FIXME: Thumb variants?
139 const MCOperand &Dst = MI->getOperand(0);
140 const MCOperand &MO1 = MI->getOperand(1);
141 const MCOperand &MO2 = MI->getOperand(2);
143 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
144 printSBitModifierOperand(MI, 5, STI, O);
145 printPredicateOperand(MI, 3, STI, O);
148 printRegName(O, Dst.getReg());
150 printRegName(O, MO1.getReg());
152 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
153 printAnnotation(O, Annot);
157 O << ", " << markup("<imm:") << "#"
158 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
159 printAnnotation(O, Annot);
165 case ARM::t2STMDB_UPD:
166 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
167 // Should only print PUSH if there are at least two registers in the list.
169 printPredicateOperand(MI, 2, STI, O);
170 if (Opcode == ARM::t2STMDB_UPD)
173 printRegisterList(MI, 4, STI, O);
174 printAnnotation(O, Annot);
179 case ARM::STR_PRE_IMM:
180 if (MI->getOperand(2).getReg() == ARM::SP &&
181 MI->getOperand(3).getImm() == -4) {
183 printPredicateOperand(MI, 4, STI, O);
185 printRegName(O, MI->getOperand(1).getReg());
187 printAnnotation(O, Annot);
194 case ARM::t2LDMIA_UPD:
195 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
196 // Should only print POP if there are at least two registers in the list.
198 printPredicateOperand(MI, 2, STI, O);
199 if (Opcode == ARM::t2LDMIA_UPD)
202 printRegisterList(MI, 4, STI, O);
203 printAnnotation(O, Annot);
208 case ARM::LDR_POST_IMM:
209 if (MI->getOperand(2).getReg() == ARM::SP &&
210 MI->getOperand(4).getImm() == 4) {
212 printPredicateOperand(MI, 5, STI, O);
214 printRegName(O, MI->getOperand(0).getReg());
216 printAnnotation(O, Annot);
222 case ARM::VSTMSDB_UPD:
223 case ARM::VSTMDDB_UPD:
224 if (MI->getOperand(0).getReg() == ARM::SP) {
225 O << '\t' << "vpush";
226 printPredicateOperand(MI, 2, STI, O);
228 printRegisterList(MI, 4, STI, O);
229 printAnnotation(O, Annot);
235 case ARM::VLDMSIA_UPD:
236 case ARM::VLDMDIA_UPD:
237 if (MI->getOperand(0).getReg() == ARM::SP) {
239 printPredicateOperand(MI, 2, STI, O);
241 printRegisterList(MI, 4, STI, O);
242 printAnnotation(O, Annot);
248 bool Writeback = true;
249 unsigned BaseReg = MI->getOperand(0).getReg();
250 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
251 if (MI->getOperand(i).getReg() == BaseReg)
257 printPredicateOperand(MI, 1, STI, O);
259 printRegName(O, BaseReg);
263 printRegisterList(MI, 3, STI, O);
264 printAnnotation(O, Annot);
268 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
269 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
270 // a single GPRPair reg operand is used in the .td file to replace the two
271 // GPRs. However, when decoding them, the two GRPs cannot be automatically
272 // expressed as a GPRPair, so we have to manually merge them.
273 // FIXME: We would really like to be able to tablegen'erate this.
278 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
279 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
280 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
281 if (MRC.contains(Reg)) {
284 NewMI.setOpcode(Opcode);
287 NewMI.addOperand(MI->getOperand(0));
288 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
289 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
290 NewMI.addOperand(NewReg);
292 // Copy the rest operands into NewMI.
293 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
294 NewMI.addOperand(MI->getOperand(i));
295 printInstruction(&NewMI, STI, O);
300 // B9.3.3 ERET (Thumb)
301 // For a target that has Virtualization Extensions, ERET is the preferred
302 // disassembly of SUBS PC, LR, #0
303 case ARM::t2SUBS_PC_LR: {
304 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
305 MI->getOperand(0).getImm() == 0 &&
306 STI.getFeatureBits()[ARM::FeatureVirtualization]) {
308 printPredicateOperand(MI, 1, STI, O);
309 printAnnotation(O, Annot);
316 printInstruction(MI, STI, O);
317 printAnnotation(O, Annot);
320 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
321 const MCSubtargetInfo &STI, raw_ostream &O) {
322 const MCOperand &Op = MI->getOperand(OpNo);
324 unsigned Reg = Op.getReg();
325 printRegName(O, Reg);
326 } else if (Op.isImm()) {
327 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
329 assert(Op.isExpr() && "unknown operand kind in printOperand");
330 const MCExpr *Expr = Op.getExpr();
331 switch (Expr->getKind()) {
334 Expr->print(O, &MAI);
336 case MCExpr::Constant: {
337 // If a symbolic branch target was added as a constant expression then
338 // print that address in hex. And only print 32 unsigned bits for the
340 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
341 int64_t TargetAddress;
342 if (!Constant->evaluateAsAbsolute(TargetAddress)) {
344 Expr->print(O, &MAI);
347 O.write_hex(static_cast<uint32_t>(TargetAddress));
352 // FIXME: Should we always treat this as if it is a constant literal and
353 // prefix it with '#'?
354 Expr->print(O, &MAI);
360 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
361 const MCSubtargetInfo &STI,
363 const MCOperand &MO1 = MI->getOperand(OpNum);
365 MO1.getExpr()->print(O, &MAI);
369 O << markup("<mem:") << "[pc, ";
371 int32_t OffImm = (int32_t)MO1.getImm();
372 bool isSub = OffImm < 0;
374 // Special value for #-0. All others are normal.
375 if (OffImm == INT32_MIN)
378 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
380 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
382 O << "]" << markup(">");
385 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
386 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
388 // REG REG 0,SH_OPC - e.g. R5, ROR R3
389 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
390 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
391 const MCSubtargetInfo &STI,
393 const MCOperand &MO1 = MI->getOperand(OpNum);
394 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
395 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
397 printRegName(O, MO1.getReg());
399 // Print the shift opc.
400 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
401 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
402 if (ShOpc == ARM_AM::rrx)
406 printRegName(O, MO2.getReg());
407 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
410 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
411 const MCSubtargetInfo &STI,
413 const MCOperand &MO1 = MI->getOperand(OpNum);
414 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
416 printRegName(O, MO1.getReg());
418 // Print the shift opc.
419 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
420 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
423 //===--------------------------------------------------------------------===//
424 // Addressing Mode #2
425 //===--------------------------------------------------------------------===//
427 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
428 const MCSubtargetInfo &STI,
430 const MCOperand &MO1 = MI->getOperand(Op);
431 const MCOperand &MO2 = MI->getOperand(Op + 1);
432 const MCOperand &MO3 = MI->getOperand(Op + 2);
434 O << markup("<mem:") << "[";
435 printRegName(O, MO1.getReg());
438 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
439 O << ", " << markup("<imm:") << "#"
440 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
441 << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
443 O << "]" << markup(">");
448 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
449 printRegName(O, MO2.getReg());
451 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
452 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
453 O << "]" << markup(">");
456 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
457 const MCSubtargetInfo &STI,
459 const MCOperand &MO1 = MI->getOperand(Op);
460 const MCOperand &MO2 = MI->getOperand(Op + 1);
461 O << markup("<mem:") << "[";
462 printRegName(O, MO1.getReg());
464 printRegName(O, MO2.getReg());
465 O << "]" << markup(">");
468 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
469 const MCSubtargetInfo &STI,
471 const MCOperand &MO1 = MI->getOperand(Op);
472 const MCOperand &MO2 = MI->getOperand(Op + 1);
473 O << markup("<mem:") << "[";
474 printRegName(O, MO1.getReg());
476 printRegName(O, MO2.getReg());
477 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
480 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
481 const MCSubtargetInfo &STI,
483 const MCOperand &MO1 = MI->getOperand(Op);
485 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
486 printOperand(MI, Op, STI, O);
491 const MCOperand &MO3 = MI->getOperand(Op + 2);
492 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
493 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
496 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
499 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
501 const MCSubtargetInfo &STI,
503 const MCOperand &MO1 = MI->getOperand(OpNum);
504 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
507 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
508 O << markup("<imm:") << '#'
509 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
514 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
515 printRegName(O, MO1.getReg());
517 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
518 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
521 //===--------------------------------------------------------------------===//
522 // Addressing Mode #3
523 //===--------------------------------------------------------------------===//
525 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
527 bool AlwaysPrintImm0) {
528 const MCOperand &MO1 = MI->getOperand(Op);
529 const MCOperand &MO2 = MI->getOperand(Op + 1);
530 const MCOperand &MO3 = MI->getOperand(Op + 2);
532 O << markup("<mem:") << '[';
533 printRegName(O, MO1.getReg());
536 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
537 printRegName(O, MO2.getReg());
538 O << ']' << markup(">");
542 // If the op is sub we have to print the immediate even if it is 0
543 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
544 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
546 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
547 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
550 O << ']' << markup(">");
553 template <bool AlwaysPrintImm0>
554 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
555 const MCSubtargetInfo &STI,
557 const MCOperand &MO1 = MI->getOperand(Op);
558 if (!MO1.isReg()) { // For label symbolic references.
559 printOperand(MI, Op, STI, O);
563 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
564 ARMII::IndexModePost &&
565 "unexpected idxmode");
566 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
569 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
571 const MCSubtargetInfo &STI,
573 const MCOperand &MO1 = MI->getOperand(OpNum);
574 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
577 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
578 printRegName(O, MO1.getReg());
582 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
583 O << markup("<imm:") << '#'
584 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
588 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
589 const MCSubtargetInfo &STI,
591 const MCOperand &MO = MI->getOperand(OpNum);
592 unsigned Imm = MO.getImm();
593 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
597 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
598 const MCSubtargetInfo &STI,
600 const MCOperand &MO1 = MI->getOperand(OpNum);
601 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
603 O << (MO2.getImm() ? "" : "-");
604 printRegName(O, MO1.getReg());
607 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
608 const MCSubtargetInfo &STI,
610 const MCOperand &MO = MI->getOperand(OpNum);
611 unsigned Imm = MO.getImm();
612 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
616 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
617 const MCSubtargetInfo &STI,
619 ARM_AM::AMSubMode Mode =
620 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
621 O << ARM_AM::getAMSubModeStr(Mode);
624 template <bool AlwaysPrintImm0>
625 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
626 const MCSubtargetInfo &STI,
628 const MCOperand &MO1 = MI->getOperand(OpNum);
629 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
631 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
632 printOperand(MI, OpNum, STI, O);
636 O << markup("<mem:") << "[";
637 printRegName(O, MO1.getReg());
639 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
640 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
641 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
642 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
643 << ImmOffs * 4 << markup(">");
645 O << "]" << markup(">");
648 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
649 const MCSubtargetInfo &STI,
651 const MCOperand &MO1 = MI->getOperand(OpNum);
652 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
654 O << markup("<mem:") << "[";
655 printRegName(O, MO1.getReg());
657 O << ":" << (MO2.getImm() << 3);
659 O << "]" << markup(">");
662 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
663 const MCSubtargetInfo &STI,
665 const MCOperand &MO1 = MI->getOperand(OpNum);
666 O << markup("<mem:") << "[";
667 printRegName(O, MO1.getReg());
668 O << "]" << markup(">");
671 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
673 const MCSubtargetInfo &STI,
675 const MCOperand &MO = MI->getOperand(OpNum);
676 if (MO.getReg() == 0)
680 printRegName(O, MO.getReg());
684 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
686 const MCSubtargetInfo &STI,
688 const MCOperand &MO = MI->getOperand(OpNum);
689 uint32_t v = ~MO.getImm();
690 int32_t lsb = countTrailingZeros(v);
691 int32_t width = (32 - countLeadingZeros(v)) - lsb;
692 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
693 O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
694 << '#' << width << markup(">");
697 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
698 const MCSubtargetInfo &STI,
700 unsigned val = MI->getOperand(OpNum).getImm();
701 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
704 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
705 const MCSubtargetInfo &STI,
707 unsigned val = MI->getOperand(OpNum).getImm();
708 O << ARM_ISB::InstSyncBOptToString(val);
711 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
712 const MCSubtargetInfo &STI,
714 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
715 bool isASR = (ShiftOp & (1 << 5)) != 0;
716 unsigned Amt = ShiftOp & 0x1f;
718 O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
721 O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
725 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
726 const MCSubtargetInfo &STI,
728 unsigned Imm = MI->getOperand(OpNum).getImm();
731 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
732 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
735 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
736 const MCSubtargetInfo &STI,
738 unsigned Imm = MI->getOperand(OpNum).getImm();
739 // A shift amount of 32 is encoded as 0.
742 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
743 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
746 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
747 const MCSubtargetInfo &STI,
750 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
753 printRegName(O, MI->getOperand(i).getReg());
758 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
759 const MCSubtargetInfo &STI,
761 unsigned Reg = MI->getOperand(OpNum).getReg();
762 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
764 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
767 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
768 const MCSubtargetInfo &STI,
770 const MCOperand &Op = MI->getOperand(OpNum);
777 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
778 const MCSubtargetInfo &STI, raw_ostream &O) {
779 const MCOperand &Op = MI->getOperand(OpNum);
780 O << ARM_PROC::IModToString(Op.getImm());
783 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
784 const MCSubtargetInfo &STI, raw_ostream &O) {
785 const MCOperand &Op = MI->getOperand(OpNum);
786 unsigned IFlags = Op.getImm();
787 for (int i = 2; i >= 0; --i)
788 if (IFlags & (1 << i))
789 O << ARM_PROC::IFlagsToString(1 << i);
795 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
796 const MCSubtargetInfo &STI,
798 const MCOperand &Op = MI->getOperand(OpNum);
799 unsigned SpecRegRBit = Op.getImm() >> 4;
800 unsigned Mask = Op.getImm() & 0xf;
801 const FeatureBitset &FeatureBits = STI.getFeatureBits();
803 if (FeatureBits[ARM::FeatureMClass]) {
804 unsigned SYSm = Op.getImm();
805 unsigned Opcode = MI->getOpcode();
807 // For writes, handle extended mask bits if the DSP extension is present.
808 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
837 // Handle the basic 8-bit mask.
840 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
841 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
842 // alias for MSR APSR_nzcvq.
861 llvm_unreachable("Unexpected mask value!");
907 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
908 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
909 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
913 llvm_unreachable("Unexpected mask value!");
944 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
945 const MCSubtargetInfo &STI,
947 uint32_t Banked = MI->getOperand(OpNum).getImm();
948 uint32_t R = (Banked & 0x20) >> 5;
949 uint32_t SysM = Banked & 0x1f;
951 // Nothing much we can do about this, the encodings are specified in B9.2.3 of
952 // the ARM ARM v7C, and are all over the shop.
979 llvm_unreachable("Invalid banked SPSR register");
983 assert(!R && "should have dealt with SPSR regs");
984 const char *RegNames[] = {
985 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
986 "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
987 "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
988 "sp_abt", "lr_und", "sp_und", "", "", "", "",
989 "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
990 const char *Name = RegNames[SysM];
991 assert(Name[0] && "invalid banked register operand");
996 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
997 const MCSubtargetInfo &STI,
999 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1000 // Handle the undefined 15 CC value here for printing so we don't abort().
1001 if ((unsigned)CC == 15)
1003 else if (CC != ARMCC::AL)
1004 O << ARMCondCodeToString(CC);
1007 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1009 const MCSubtargetInfo &STI,
1011 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1012 O << ARMCondCodeToString(CC);
1015 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1016 const MCSubtargetInfo &STI,
1018 if (MI->getOperand(OpNum).getReg()) {
1019 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1020 "Expect ARM CPSR register!");
1025 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1026 const MCSubtargetInfo &STI,
1028 O << MI->getOperand(OpNum).getImm();
1031 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1032 const MCSubtargetInfo &STI,
1034 O << "p" << MI->getOperand(OpNum).getImm();
1037 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1038 const MCSubtargetInfo &STI,
1040 O << "c" << MI->getOperand(OpNum).getImm();
1043 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1044 const MCSubtargetInfo &STI,
1046 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1049 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1050 const MCSubtargetInfo &STI, raw_ostream &O) {
1051 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1054 template <unsigned scale>
1055 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1056 const MCSubtargetInfo &STI,
1058 const MCOperand &MO = MI->getOperand(OpNum);
1061 MO.getExpr()->print(O, &MAI);
1065 int32_t OffImm = (int32_t)MO.getImm() << scale;
1067 O << markup("<imm:");
1068 if (OffImm == INT32_MIN)
1070 else if (OffImm < 0)
1071 O << "#-" << -OffImm;
1077 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1078 const MCSubtargetInfo &STI,
1080 O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1084 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1085 const MCSubtargetInfo &STI,
1087 unsigned Imm = MI->getOperand(OpNum).getImm();
1088 O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1092 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1093 const MCSubtargetInfo &STI,
1095 // (3 - the number of trailing zeros) is the number of then / else.
1096 unsigned Mask = MI->getOperand(OpNum).getImm();
1097 unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1098 unsigned CondBit0 = Firstcond & 1;
1099 unsigned NumTZ = countTrailingZeros(Mask);
1100 assert(NumTZ <= 3 && "Invalid IT mask!");
1101 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1102 bool T = ((Mask >> Pos) & 1) == CondBit0;
1110 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1111 const MCSubtargetInfo &STI,
1113 const MCOperand &MO1 = MI->getOperand(Op);
1114 const MCOperand &MO2 = MI->getOperand(Op + 1);
1116 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1117 printOperand(MI, Op, STI, O);
1121 O << markup("<mem:") << "[";
1122 printRegName(O, MO1.getReg());
1123 if (unsigned RegNum = MO2.getReg()) {
1125 printRegName(O, RegNum);
1127 O << "]" << markup(">");
1130 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1132 const MCSubtargetInfo &STI,
1135 const MCOperand &MO1 = MI->getOperand(Op);
1136 const MCOperand &MO2 = MI->getOperand(Op + 1);
1138 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1139 printOperand(MI, Op, STI, O);
1143 O << markup("<mem:") << "[";
1144 printRegName(O, MO1.getReg());
1145 if (unsigned ImmOffs = MO2.getImm()) {
1146 O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1149 O << "]" << markup(">");
1152 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1154 const MCSubtargetInfo &STI,
1156 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1159 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1161 const MCSubtargetInfo &STI,
1163 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1166 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1168 const MCSubtargetInfo &STI,
1170 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1173 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1174 const MCSubtargetInfo &STI,
1176 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1179 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1180 // register with shift forms.
1181 // REG 0 0 - e.g. R5
1182 // REG IMM, SH_OPC - e.g. R5, LSL #3
1183 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1184 const MCSubtargetInfo &STI,
1186 const MCOperand &MO1 = MI->getOperand(OpNum);
1187 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1189 unsigned Reg = MO1.getReg();
1190 printRegName(O, Reg);
1192 // Print the shift opc.
1193 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1194 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1195 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1198 template <bool AlwaysPrintImm0>
1199 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1200 const MCSubtargetInfo &STI,
1202 const MCOperand &MO1 = MI->getOperand(OpNum);
1203 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1205 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1206 printOperand(MI, OpNum, STI, O);
1210 O << markup("<mem:") << "[";
1211 printRegName(O, MO1.getReg());
1213 int32_t OffImm = (int32_t)MO2.getImm();
1214 bool isSub = OffImm < 0;
1215 // Special value for #-0. All others are normal.
1216 if (OffImm == INT32_MIN)
1219 O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1220 } else if (AlwaysPrintImm0 || OffImm > 0) {
1221 O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1223 O << "]" << markup(">");
1226 template <bool AlwaysPrintImm0>
1227 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1229 const MCSubtargetInfo &STI,
1231 const MCOperand &MO1 = MI->getOperand(OpNum);
1232 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1234 O << markup("<mem:") << "[";
1235 printRegName(O, MO1.getReg());
1237 int32_t OffImm = (int32_t)MO2.getImm();
1238 bool isSub = OffImm < 0;
1240 if (OffImm == INT32_MIN)
1243 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1244 } else if (AlwaysPrintImm0 || OffImm > 0) {
1245 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1247 O << "]" << markup(">");
1250 template <bool AlwaysPrintImm0>
1251 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1253 const MCSubtargetInfo &STI,
1255 const MCOperand &MO1 = MI->getOperand(OpNum);
1256 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1258 if (!MO1.isReg()) { // For label symbolic references.
1259 printOperand(MI, OpNum, STI, O);
1263 O << markup("<mem:") << "[";
1264 printRegName(O, MO1.getReg());
1266 int32_t OffImm = (int32_t)MO2.getImm();
1267 bool isSub = OffImm < 0;
1269 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1272 if (OffImm == INT32_MIN)
1275 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1276 } else if (AlwaysPrintImm0 || OffImm > 0) {
1277 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1279 O << "]" << markup(">");
1282 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1283 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1285 const MCOperand &MO1 = MI->getOperand(OpNum);
1286 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1288 O << markup("<mem:") << "[";
1289 printRegName(O, MO1.getReg());
1291 O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1294 O << "]" << markup(">");
1297 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1298 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1300 const MCOperand &MO1 = MI->getOperand(OpNum);
1301 int32_t OffImm = (int32_t)MO1.getImm();
1302 O << ", " << markup("<imm:");
1303 if (OffImm == INT32_MIN)
1305 else if (OffImm < 0)
1306 O << "#-" << -OffImm;
1312 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1313 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1315 const MCOperand &MO1 = MI->getOperand(OpNum);
1316 int32_t OffImm = (int32_t)MO1.getImm();
1318 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1320 O << ", " << markup("<imm:");
1321 if (OffImm == INT32_MIN)
1323 else if (OffImm < 0)
1324 O << "#-" << -OffImm;
1330 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1332 const MCSubtargetInfo &STI,
1334 const MCOperand &MO1 = MI->getOperand(OpNum);
1335 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1336 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1338 O << markup("<mem:") << "[";
1339 printRegName(O, MO1.getReg());
1341 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1343 printRegName(O, MO2.getReg());
1345 unsigned ShAmt = MO3.getImm();
1347 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1348 O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1350 O << "]" << markup(">");
1353 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1354 const MCSubtargetInfo &STI,
1356 const MCOperand &MO = MI->getOperand(OpNum);
1357 O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1361 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1362 const MCSubtargetInfo &STI,
1364 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1366 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1367 O << markup("<imm:") << "#0x";
1372 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1373 const MCSubtargetInfo &STI,
1375 unsigned Imm = MI->getOperand(OpNum).getImm();
1376 O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1379 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1380 const MCSubtargetInfo &STI,
1382 unsigned Imm = MI->getOperand(OpNum).getImm();
1385 assert(Imm <= 3 && "illegal ror immediate!");
1386 O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1389 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1390 const MCSubtargetInfo &STI,
1392 MCOperand Op = MI->getOperand(OpNum);
1394 // Support for fixups (MCFixup)
1396 return printOperand(MI, OpNum, STI, O);
1398 unsigned Bits = Op.getImm() & 0xFF;
1399 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1401 bool PrintUnsigned = false;
1402 switch (MI->getOpcode()) {
1404 // Movs to PC should be treated unsigned
1405 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1408 // Movs to special registers should be treated unsigned
1409 PrintUnsigned = true;
1413 int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1414 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1415 // #rot has the least possible value
1416 O << "#" << markup("<imm:");
1418 O << static_cast<uint32_t>(Rotated);
1425 // Explicit #bits, #rot implied
1426 O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1427 << Rot << markup(">");
1430 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1431 const MCSubtargetInfo &STI, raw_ostream &O) {
1432 O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1436 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1437 const MCSubtargetInfo &STI, raw_ostream &O) {
1438 O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1442 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1443 const MCSubtargetInfo &STI,
1445 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1448 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1449 const MCSubtargetInfo &STI,
1452 printRegName(O, MI->getOperand(OpNum).getReg());
1456 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1457 const MCSubtargetInfo &STI,
1459 unsigned Reg = MI->getOperand(OpNum).getReg();
1460 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1461 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1463 printRegName(O, Reg0);
1465 printRegName(O, Reg1);
1469 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1470 const MCSubtargetInfo &STI,
1472 unsigned Reg = MI->getOperand(OpNum).getReg();
1473 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1474 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1476 printRegName(O, Reg0);
1478 printRegName(O, Reg1);
1482 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1483 const MCSubtargetInfo &STI,
1485 // Normally, it's not safe to use register enum values directly with
1486 // addition to get the next register, but for VFP registers, the
1487 // sort order is guaranteed because they're all of the form D<n>.
1489 printRegName(O, MI->getOperand(OpNum).getReg());
1491 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1493 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1497 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1498 const MCSubtargetInfo &STI,
1500 // Normally, it's not safe to use register enum values directly with
1501 // addition to get the next register, but for VFP registers, the
1502 // sort order is guaranteed because they're all of the form D<n>.
1504 printRegName(O, MI->getOperand(OpNum).getReg());
1506 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1508 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1510 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1514 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1516 const MCSubtargetInfo &STI,
1519 printRegName(O, MI->getOperand(OpNum).getReg());
1523 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1525 const MCSubtargetInfo &STI,
1527 unsigned Reg = MI->getOperand(OpNum).getReg();
1528 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1529 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1531 printRegName(O, Reg0);
1533 printRegName(O, Reg1);
1537 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1539 const MCSubtargetInfo &STI,
1541 // Normally, it's not safe to use register enum values directly with
1542 // addition to get the next register, but for VFP registers, the
1543 // sort order is guaranteed because they're all of the form D<n>.
1545 printRegName(O, MI->getOperand(OpNum).getReg());
1547 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1549 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1553 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1555 const MCSubtargetInfo &STI,
1557 // Normally, it's not safe to use register enum values directly with
1558 // addition to get the next register, but for VFP registers, the
1559 // sort order is guaranteed because they're all of the form D<n>.
1561 printRegName(O, MI->getOperand(OpNum).getReg());
1563 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1565 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1567 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1571 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1572 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1574 unsigned Reg = MI->getOperand(OpNum).getReg();
1575 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1576 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1578 printRegName(O, Reg0);
1580 printRegName(O, Reg1);
1584 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1585 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1587 // Normally, it's not safe to use register enum values directly with
1588 // addition to get the next register, but for VFP registers, the
1589 // sort order is guaranteed because they're all of the form D<n>.
1591 printRegName(O, MI->getOperand(OpNum).getReg());
1593 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1595 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1599 void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1600 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1602 // Normally, it's not safe to use register enum values directly with
1603 // addition to get the next register, but for VFP registers, the
1604 // sort order is guaranteed because they're all of the form D<n>.
1606 printRegName(O, MI->getOperand(OpNum).getReg());
1608 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1610 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1612 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1616 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1618 const MCSubtargetInfo &STI,
1620 // Normally, it's not safe to use register enum values directly with
1621 // addition to get the next register, but for VFP registers, the
1622 // sort order is guaranteed because they're all of the form D<n>.
1624 printRegName(O, MI->getOperand(OpNum).getReg());
1626 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1628 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1632 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1633 const MCSubtargetInfo &STI,
1635 // Normally, it's not safe to use register enum values directly with
1636 // addition to get the next register, but for VFP registers, the
1637 // sort order is guaranteed because they're all of the form D<n>.
1639 printRegName(O, MI->getOperand(OpNum).getReg());
1641 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1643 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1645 printRegName(O, MI->getOperand(OpNum).getReg() + 6);