1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #include "ARMGenAsmWriter.inc"
27 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
28 // Check for MOVs and print canonical forms, instead.
29 if (MI->getOpcode() == ARM::MOVs) {
30 // FIXME: Thumb variants?
31 const MCOperand &Dst = MI->getOperand(0);
32 const MCOperand &MO1 = MI->getOperand(1);
33 const MCOperand &MO2 = MI->getOperand(2);
34 const MCOperand &MO3 = MI->getOperand(3);
36 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
37 printSBitModifierOperand(MI, 6, O);
38 printPredicateOperand(MI, 4, O);
40 O << '\t' << getRegisterName(Dst.getReg())
41 << ", " << getRegisterName(MO1.getReg());
43 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
49 O << getRegisterName(MO2.getReg());
50 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
52 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
58 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
59 MI->getOperand(0).getReg() == ARM::SP) {
60 const MCOperand &MO1 = MI->getOperand(2);
61 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
63 printPredicateOperand(MI, 3, O);
65 printRegisterList(MI, 5, O);
71 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
72 MI->getOperand(0).getReg() == ARM::SP) {
73 const MCOperand &MO1 = MI->getOperand(2);
74 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
76 printPredicateOperand(MI, 3, O);
78 printRegisterList(MI, 5, O);
84 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
85 MI->getOperand(0).getReg() == ARM::SP) {
86 const MCOperand &MO1 = MI->getOperand(2);
87 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
89 printPredicateOperand(MI, 3, O);
91 printRegisterList(MI, 5, O);
97 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
98 MI->getOperand(0).getReg() == ARM::SP) {
99 const MCOperand &MO1 = MI->getOperand(2);
100 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
102 printPredicateOperand(MI, 3, O);
104 printRegisterList(MI, 5, O);
109 printInstruction(MI, O);
112 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
113 raw_ostream &O, const char *Modifier) {
114 const MCOperand &Op = MI->getOperand(OpNo);
116 unsigned Reg = Op.getReg();
117 O << getRegisterName(Reg);
118 } else if (Op.isImm()) {
119 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
120 O << '#' << Op.getImm();
122 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
123 assert(Op.isExpr() && "unknown operand kind in printOperand");
128 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
129 const MCAsmInfo *MAI) {
130 // Break it up into two parts that make up a shifter immediate.
131 V = ARM_AM::getSOImmVal(V);
132 assert(V != -1 && "Not a valid so_imm value!");
134 unsigned Imm = ARM_AM::getSOImmValImm(V);
135 unsigned Rot = ARM_AM::getSOImmValRot(V);
137 // Print low-level immediate formation info, per
138 // A5.1.3: "Data-processing operands - Immediate".
140 O << "#" << Imm << ", " << Rot;
141 // Pretty printed version.
143 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
150 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
151 /// immediate in bits 0-7.
152 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
154 const MCOperand &MO = MI->getOperand(OpNum);
155 assert(MO.isImm() && "Not a valid so_imm value!");
156 printSOImm(O, MO.getImm(), CommentStream, &MAI);
159 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
160 /// followed by an 'orr' to materialize.
161 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
163 // FIXME: REMOVE this method.
167 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
168 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
170 // REG REG 0,SH_OPC - e.g. R5, ROR R3
171 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
172 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
174 const MCOperand &MO1 = MI->getOperand(OpNum);
175 const MCOperand &MO2 = MI->getOperand(OpNum+1);
176 const MCOperand &MO3 = MI->getOperand(OpNum+2);
178 O << getRegisterName(MO1.getReg());
180 // Print the shift opc.
181 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
182 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
184 O << ' ' << getRegisterName(MO2.getReg());
185 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
186 } else if (ShOpc != ARM_AM::rrx) {
187 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
192 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
194 const MCOperand &MO1 = MI->getOperand(Op);
195 const MCOperand &MO2 = MI->getOperand(Op+1);
196 const MCOperand &MO3 = MI->getOperand(Op+2);
198 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
199 printOperand(MI, Op, O);
203 O << "[" << getRegisterName(MO1.getReg());
206 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
208 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
209 << ARM_AM::getAM2Offset(MO3.getImm());
215 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
216 << getRegisterName(MO2.getReg());
218 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
220 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
225 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
228 const MCOperand &MO1 = MI->getOperand(OpNum);
229 const MCOperand &MO2 = MI->getOperand(OpNum+1);
232 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
234 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
239 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
240 << getRegisterName(MO1.getReg());
242 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
244 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
248 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
250 const MCOperand &MO1 = MI->getOperand(OpNum);
251 const MCOperand &MO2 = MI->getOperand(OpNum+1);
252 const MCOperand &MO3 = MI->getOperand(OpNum+2);
254 O << '[' << getRegisterName(MO1.getReg());
257 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
258 << getRegisterName(MO2.getReg()) << ']';
262 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
264 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
269 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
272 const MCOperand &MO1 = MI->getOperand(OpNum);
273 const MCOperand &MO2 = MI->getOperand(OpNum+1);
276 O << (char)ARM_AM::getAM3Op(MO2.getImm())
277 << getRegisterName(MO1.getReg());
281 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
283 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
288 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
290 const char *Modifier) {
291 const MCOperand &MO2 = MI->getOperand(OpNum+1);
292 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
293 if (Modifier && strcmp(Modifier, "submode") == 0) {
294 O << ARM_AM::getAMSubModeStr(Mode);
295 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
296 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
297 if (Mode == ARM_AM::ia)
300 printOperand(MI, OpNum, O);
304 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
306 const char *Modifier) {
307 const MCOperand &MO1 = MI->getOperand(OpNum);
308 const MCOperand &MO2 = MI->getOperand(OpNum+1);
310 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
311 printOperand(MI, OpNum, O);
315 O << "[" << getRegisterName(MO1.getReg());
317 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
319 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
325 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
327 const MCOperand &MO1 = MI->getOperand(OpNum);
328 const MCOperand &MO2 = MI->getOperand(OpNum+1);
330 O << "[" << getRegisterName(MO1.getReg());
332 // FIXME: Both darwin as and GNU as violate ARM docs here.
333 O << ", :" << (MO2.getImm() << 3);
338 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
341 const MCOperand &MO = MI->getOperand(OpNum);
342 if (MO.getReg() == 0)
345 O << ", " << getRegisterName(MO.getReg());
348 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
350 const char *Modifier) {
351 // All instructions using addrmodepc are pseudos and should have been
352 // handled explicitly in printInstructionThroughMCStreamer(). If one got
353 // here, it wasn't, so something's wrong.
354 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
357 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
360 const MCOperand &MO = MI->getOperand(OpNum);
361 uint32_t v = ~MO.getImm();
362 int32_t lsb = CountTrailingZeros_32(v);
363 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
364 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
365 O << '#' << lsb << ", #" << width;
368 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
370 unsigned val = MI->getOperand(OpNum).getImm();
371 O << ARM_MB::MemBOptToString(val);
374 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
376 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
377 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
379 case ARM_AM::no_shift:
388 assert(0 && "unexpected shift opcode for shift immediate operand");
390 O << ARM_AM::getSORegOffset(ShiftOp);
393 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
396 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
397 if (i != OpNum) O << ", ";
398 O << getRegisterName(MI->getOperand(i).getReg());
403 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
405 const MCOperand &Op = MI->getOperand(OpNum);
412 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
414 const MCOperand &Op = MI->getOperand(OpNum);
415 unsigned option = Op.getImm();
416 unsigned mode = option & 31;
417 bool changemode = option >> 5 & 1;
418 unsigned AIF = option >> 6 & 7;
419 unsigned imod = option >> 9 & 3;
426 if (AIF & 4) O << 'a';
427 if (AIF & 2) O << 'i';
428 if (AIF & 1) O << 'f';
429 if (AIF > 0 && changemode) O << ", ";
435 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
437 const MCOperand &Op = MI->getOperand(OpNum);
438 unsigned Mask = Op.getImm();
441 if (Mask & 8) O << 'f';
442 if (Mask & 4) O << 's';
443 if (Mask & 2) O << 'x';
444 if (Mask & 1) O << 'c';
448 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
450 const MCOperand &Op = MI->getOperand(OpNum);
453 O << '-' << (-Op.getImm() - 1);
458 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
460 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
462 O << ARMCondCodeToString(CC);
465 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
468 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
469 O << ARMCondCodeToString(CC);
472 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
474 if (MI->getOperand(OpNum).getReg()) {
475 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
476 "Expect ARM CPSR register!");
483 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
485 const char *Modifier) {
486 // FIXME: remove this.
490 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
492 O << MI->getOperand(OpNum).getImm();
496 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
498 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
501 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
503 O << "#" << MI->getOperand(OpNum).getImm() * 4;
506 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
508 // (3 - the number of trailing zeros) is the number of then / else.
509 unsigned Mask = MI->getOperand(OpNum).getImm();
510 unsigned CondBit0 = Mask >> 4 & 1;
511 unsigned NumTZ = CountTrailingZeros_32(Mask);
512 assert(NumTZ <= 3 && "Invalid IT mask!");
513 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
514 bool T = ((Mask >> Pos) & 1) == CondBit0;
522 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
524 const MCOperand &MO1 = MI->getOperand(Op);
525 const MCOperand &MO2 = MI->getOperand(Op+1);
526 O << "[" << getRegisterName(MO1.getReg());
527 O << ", " << getRegisterName(MO2.getReg()) << "]";
530 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
533 const MCOperand &MO1 = MI->getOperand(Op);
534 const MCOperand &MO2 = MI->getOperand(Op+1);
535 const MCOperand &MO3 = MI->getOperand(Op+2);
537 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
538 printOperand(MI, Op, O);
542 O << "[" << getRegisterName(MO1.getReg());
544 O << ", " << getRegisterName(MO3.getReg());
545 else if (unsigned ImmOffs = MO2.getImm())
546 O << ", #" << ImmOffs * Scale;
550 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
552 printThumbAddrModeRI5Operand(MI, Op, O, 1);
555 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
557 printThumbAddrModeRI5Operand(MI, Op, O, 2);
560 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
562 printThumbAddrModeRI5Operand(MI, Op, O, 4);
565 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
567 const MCOperand &MO1 = MI->getOperand(Op);
568 const MCOperand &MO2 = MI->getOperand(Op+1);
569 O << "[" << getRegisterName(MO1.getReg());
570 if (unsigned ImmOffs = MO2.getImm())
571 O << ", #" << ImmOffs*4;
575 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
577 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
578 if (MI->getOpcode() == ARM::t2TBH)
583 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
584 // register with shift forms.
586 // REG IMM, SH_OPC - e.g. R5, LSL #3
587 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
589 const MCOperand &MO1 = MI->getOperand(OpNum);
590 const MCOperand &MO2 = MI->getOperand(OpNum+1);
592 unsigned Reg = MO1.getReg();
593 O << getRegisterName(Reg);
595 // Print the shift opc.
596 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
597 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
598 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
599 if (ShOpc != ARM_AM::rrx)
600 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
603 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
606 const MCOperand &MO1 = MI->getOperand(OpNum);
607 const MCOperand &MO2 = MI->getOperand(OpNum+1);
609 O << "[" << getRegisterName(MO1.getReg());
611 unsigned OffImm = MO2.getImm();
612 if (OffImm) // Don't print +0.
613 O << ", #" << OffImm;
617 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
620 const MCOperand &MO1 = MI->getOperand(OpNum);
621 const MCOperand &MO2 = MI->getOperand(OpNum+1);
623 O << "[" << getRegisterName(MO1.getReg());
625 int32_t OffImm = (int32_t)MO2.getImm();
628 O << ", #-" << -OffImm;
630 O << ", #" << OffImm;
634 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
637 const MCOperand &MO1 = MI->getOperand(OpNum);
638 const MCOperand &MO2 = MI->getOperand(OpNum+1);
640 O << "[" << getRegisterName(MO1.getReg());
642 int32_t OffImm = (int32_t)MO2.getImm() / 4;
645 O << ", #-" << -OffImm * 4;
647 O << ", #" << OffImm * 4;
651 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
654 const MCOperand &MO1 = MI->getOperand(OpNum);
655 int32_t OffImm = (int32_t)MO1.getImm();
658 O << "#-" << -OffImm;
663 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
666 const MCOperand &MO1 = MI->getOperand(OpNum);
667 int32_t OffImm = (int32_t)MO1.getImm() / 4;
670 O << "#-" << -OffImm * 4;
672 O << "#" << OffImm * 4;
675 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
678 const MCOperand &MO1 = MI->getOperand(OpNum);
679 const MCOperand &MO2 = MI->getOperand(OpNum+1);
680 const MCOperand &MO3 = MI->getOperand(OpNum+2);
682 O << "[" << getRegisterName(MO1.getReg());
684 assert(MO2.getReg() && "Invalid so_reg load / store address!");
685 O << ", " << getRegisterName(MO2.getReg());
687 unsigned ShAmt = MO3.getImm();
689 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
690 O << ", lsl #" << ShAmt;
695 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
697 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
700 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
702 O << '#' << MI->getOperand(OpNum).getFPImm();
705 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
707 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
709 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
710 O << "#0x" << utohexstr(Val);