1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
31 /// 32 as the immediate shouldbe within the range 1-32.
32 static unsigned translateShiftImm(unsigned imm) {
38 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
39 return getInstructionName(Opcode);
42 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
43 OS << getRegisterName(RegNo);
46 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
47 unsigned Opcode = MI->getOpcode();
49 // Check for MOVs and print canonical forms, instead.
50 if (Opcode == ARM::MOVsr) {
51 // FIXME: Thumb variants?
52 const MCOperand &Dst = MI->getOperand(0);
53 const MCOperand &MO1 = MI->getOperand(1);
54 const MCOperand &MO2 = MI->getOperand(2);
55 const MCOperand &MO3 = MI->getOperand(3);
57 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
58 printSBitModifierOperand(MI, 6, O);
59 printPredicateOperand(MI, 4, O);
61 O << '\t' << getRegisterName(Dst.getReg())
62 << ", " << getRegisterName(MO1.getReg());
64 O << ", " << getRegisterName(MO2.getReg());
65 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
69 if (Opcode == ARM::MOVsi) {
70 // FIXME: Thumb variants?
71 const MCOperand &Dst = MI->getOperand(0);
72 const MCOperand &MO1 = MI->getOperand(1);
73 const MCOperand &MO2 = MI->getOperand(2);
75 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
76 printSBitModifierOperand(MI, 5, O);
77 printPredicateOperand(MI, 3, O);
79 O << '\t' << getRegisterName(Dst.getReg())
80 << ", " << getRegisterName(MO1.getReg());
82 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
85 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
91 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
92 MI->getOperand(0).getReg() == ARM::SP) {
94 printPredicateOperand(MI, 2, O);
95 if (Opcode == ARM::t2STMDB_UPD)
98 printRegisterList(MI, 4, O);
101 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
102 MI->getOperand(3).getImm() == -4) {
104 printPredicateOperand(MI, 4, O);
105 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
110 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
111 MI->getOperand(0).getReg() == ARM::SP) {
113 printPredicateOperand(MI, 2, O);
114 if (Opcode == ARM::t2LDMIA_UPD)
117 printRegisterList(MI, 4, O);
120 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
121 MI->getOperand(4).getImm() == 4) {
123 printPredicateOperand(MI, 5, O);
124 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
130 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
131 MI->getOperand(0).getReg() == ARM::SP) {
132 O << '\t' << "vpush";
133 printPredicateOperand(MI, 2, O);
135 printRegisterList(MI, 4, O);
140 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
141 MI->getOperand(0).getReg() == ARM::SP) {
143 printPredicateOperand(MI, 2, O);
145 printRegisterList(MI, 4, O);
149 if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
150 bool Writeback = true;
151 unsigned BaseReg = MI->getOperand(0).getReg();
152 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
153 if (MI->getOperand(i).getReg() == BaseReg)
157 if (Opcode == ARM::tLDMIA)
159 else if (Opcode == ARM::tSTMIA)
162 llvm_unreachable("Unknown opcode!");
164 printPredicateOperand(MI, 1, O);
165 O << '\t' << getRegisterName(BaseReg);
166 if (Writeback) O << "!";
168 printRegisterList(MI, 3, O);
172 printInstruction(MI, O);
175 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
177 const MCOperand &Op = MI->getOperand(OpNo);
179 unsigned Reg = Op.getReg();
180 O << getRegisterName(Reg);
181 } else if (Op.isImm()) {
182 O << '#' << Op.getImm();
184 assert(Op.isExpr() && "unknown operand kind in printOperand");
189 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
190 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
192 // REG REG 0,SH_OPC - e.g. R5, ROR R3
193 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
194 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
196 const MCOperand &MO1 = MI->getOperand(OpNum);
197 const MCOperand &MO2 = MI->getOperand(OpNum+1);
198 const MCOperand &MO3 = MI->getOperand(OpNum+2);
200 O << getRegisterName(MO1.getReg());
202 // Print the shift opc.
203 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
204 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
205 if (ShOpc == ARM_AM::rrx)
208 O << ' ' << getRegisterName(MO2.getReg());
209 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
212 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
214 const MCOperand &MO1 = MI->getOperand(OpNum);
215 const MCOperand &MO2 = MI->getOperand(OpNum+1);
217 O << getRegisterName(MO1.getReg());
219 // Print the shift opc.
220 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
221 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
222 if (ShOpc == ARM_AM::rrx)
224 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
228 //===--------------------------------------------------------------------===//
229 // Addressing Mode #2
230 //===--------------------------------------------------------------------===//
232 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
234 const MCOperand &MO1 = MI->getOperand(Op);
235 const MCOperand &MO2 = MI->getOperand(Op+1);
236 const MCOperand &MO3 = MI->getOperand(Op+2);
238 O << "[" << getRegisterName(MO1.getReg());
241 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
243 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
244 << ARM_AM::getAM2Offset(MO3.getImm());
250 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
251 << getRegisterName(MO2.getReg());
253 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
255 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
260 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
262 const MCOperand &MO1 = MI->getOperand(Op);
263 const MCOperand &MO2 = MI->getOperand(Op+1);
264 const MCOperand &MO3 = MI->getOperand(Op+2);
266 O << "[" << getRegisterName(MO1.getReg()) << "], ";
269 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
271 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
276 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
277 << getRegisterName(MO2.getReg());
279 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
281 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
285 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
287 const MCOperand &MO1 = MI->getOperand(Op);
289 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
290 printOperand(MI, Op, O);
294 const MCOperand &MO3 = MI->getOperand(Op+2);
295 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
297 if (IdxMode == ARMII::IndexModePost) {
298 printAM2PostIndexOp(MI, Op, O);
301 printAM2PreOrOffsetIndexOp(MI, Op, O);
304 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
307 const MCOperand &MO1 = MI->getOperand(OpNum);
308 const MCOperand &MO2 = MI->getOperand(OpNum+1);
311 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
313 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
318 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
319 << getRegisterName(MO1.getReg());
321 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
323 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
327 //===--------------------------------------------------------------------===//
328 // Addressing Mode #3
329 //===--------------------------------------------------------------------===//
331 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
333 const MCOperand &MO1 = MI->getOperand(Op);
334 const MCOperand &MO2 = MI->getOperand(Op+1);
335 const MCOperand &MO3 = MI->getOperand(Op+2);
337 O << "[" << getRegisterName(MO1.getReg()) << "], ";
340 O << (char)ARM_AM::getAM3Op(MO3.getImm())
341 << getRegisterName(MO2.getReg());
345 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
347 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
351 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
353 const MCOperand &MO1 = MI->getOperand(Op);
354 const MCOperand &MO2 = MI->getOperand(Op+1);
355 const MCOperand &MO3 = MI->getOperand(Op+2);
357 O << '[' << getRegisterName(MO1.getReg());
360 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
361 << getRegisterName(MO2.getReg()) << ']';
365 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
367 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
372 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
374 const MCOperand &MO3 = MI->getOperand(Op+2);
375 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
377 if (IdxMode == ARMII::IndexModePost) {
378 printAM3PostIndexOp(MI, Op, O);
381 printAM3PreOrOffsetIndexOp(MI, Op, O);
384 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
387 const MCOperand &MO1 = MI->getOperand(OpNum);
388 const MCOperand &MO2 = MI->getOperand(OpNum+1);
391 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
392 << getRegisterName(MO1.getReg());
396 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
398 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
402 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
405 const MCOperand &MO = MI->getOperand(OpNum);
406 unsigned Imm = MO.getImm();
407 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
410 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
412 const MCOperand &MO1 = MI->getOperand(OpNum);
413 const MCOperand &MO2 = MI->getOperand(OpNum+1);
415 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
418 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
421 const MCOperand &MO = MI->getOperand(OpNum);
422 unsigned Imm = MO.getImm();
423 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
427 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
429 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
431 O << ARM_AM::getAMSubModeStr(Mode);
434 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
436 const MCOperand &MO1 = MI->getOperand(OpNum);
437 const MCOperand &MO2 = MI->getOperand(OpNum+1);
439 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
440 printOperand(MI, OpNum, O);
444 O << "[" << getRegisterName(MO1.getReg());
446 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
448 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
454 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
456 const MCOperand &MO1 = MI->getOperand(OpNum);
457 const MCOperand &MO2 = MI->getOperand(OpNum+1);
459 O << "[" << getRegisterName(MO1.getReg());
461 // FIXME: Both darwin as and GNU as violate ARM docs here.
462 O << ", :" << (MO2.getImm() << 3);
467 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
469 const MCOperand &MO1 = MI->getOperand(OpNum);
470 O << "[" << getRegisterName(MO1.getReg()) << "]";
473 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
476 const MCOperand &MO = MI->getOperand(OpNum);
477 if (MO.getReg() == 0)
480 O << ", " << getRegisterName(MO.getReg());
483 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
486 const MCOperand &MO = MI->getOperand(OpNum);
487 uint32_t v = ~MO.getImm();
488 int32_t lsb = CountTrailingZeros_32(v);
489 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
490 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
491 O << '#' << lsb << ", #" << width;
494 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
496 unsigned val = MI->getOperand(OpNum).getImm();
497 O << ARM_MB::MemBOptToString(val);
500 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
502 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
503 bool isASR = (ShiftOp & (1 << 5)) != 0;
504 unsigned Amt = ShiftOp & 0x1f;
506 O << ", asr #" << (Amt == 0 ? 32 : Amt);
508 O << ", lsl #" << Amt;
511 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
513 unsigned Imm = MI->getOperand(OpNum).getImm();
516 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
517 O << ", lsl #" << Imm;
520 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
522 unsigned Imm = MI->getOperand(OpNum).getImm();
523 // A shift amount of 32 is encoded as 0.
526 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
527 O << ", asr #" << Imm;
530 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
533 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
534 if (i != OpNum) O << ", ";
535 O << getRegisterName(MI->getOperand(i).getReg());
540 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
542 const MCOperand &Op = MI->getOperand(OpNum);
549 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
551 const MCOperand &Op = MI->getOperand(OpNum);
552 O << ARM_PROC::IModToString(Op.getImm());
555 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
557 const MCOperand &Op = MI->getOperand(OpNum);
558 unsigned IFlags = Op.getImm();
559 for (int i=2; i >= 0; --i)
560 if (IFlags & (1 << i))
561 O << ARM_PROC::IFlagsToString(1 << i);
564 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
566 const MCOperand &Op = MI->getOperand(OpNum);
567 unsigned SpecRegRBit = Op.getImm() >> 4;
568 unsigned Mask = Op.getImm() & 0xf;
570 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
571 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
572 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
576 case 4: O << "g"; return;
577 case 8: O << "nzcvq"; return;
578 case 12: O << "nzcvqg"; return;
580 llvm_unreachable("Unexpected mask value!");
590 if (Mask & 8) O << 'f';
591 if (Mask & 4) O << 's';
592 if (Mask & 2) O << 'x';
593 if (Mask & 1) O << 'c';
597 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
599 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
601 O << ARMCondCodeToString(CC);
604 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
607 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
608 O << ARMCondCodeToString(CC);
611 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
613 if (MI->getOperand(OpNum).getReg()) {
614 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
615 "Expect ARM CPSR register!");
620 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
622 O << MI->getOperand(OpNum).getImm();
625 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
627 O << "p" << MI->getOperand(OpNum).getImm();
630 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
632 O << "c" << MI->getOperand(OpNum).getImm();
635 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
637 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
640 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
642 O << "#" << MI->getOperand(OpNum).getImm() * 4;
645 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
647 unsigned Imm = MI->getOperand(OpNum).getImm();
648 O << "#" << (Imm == 0 ? 32 : Imm);
651 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
653 // (3 - the number of trailing zeros) is the number of then / else.
654 unsigned Mask = MI->getOperand(OpNum).getImm();
655 unsigned CondBit0 = Mask >> 4 & 1;
656 unsigned NumTZ = CountTrailingZeros_32(Mask);
657 assert(NumTZ <= 3 && "Invalid IT mask!");
658 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
659 bool T = ((Mask >> Pos) & 1) == CondBit0;
667 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
669 const MCOperand &MO1 = MI->getOperand(Op);
670 const MCOperand &MO2 = MI->getOperand(Op + 1);
672 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
673 printOperand(MI, Op, O);
677 O << "[" << getRegisterName(MO1.getReg());
678 if (unsigned RegNum = MO2.getReg())
679 O << ", " << getRegisterName(RegNum);
683 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
687 const MCOperand &MO1 = MI->getOperand(Op);
688 const MCOperand &MO2 = MI->getOperand(Op + 1);
690 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
691 printOperand(MI, Op, O);
695 O << "[" << getRegisterName(MO1.getReg());
696 if (unsigned ImmOffs = MO2.getImm())
697 O << ", #" << ImmOffs * Scale;
701 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
704 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
707 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
710 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
713 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
716 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
719 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
721 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
724 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
725 // register with shift forms.
727 // REG IMM, SH_OPC - e.g. R5, LSL #3
728 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
730 const MCOperand &MO1 = MI->getOperand(OpNum);
731 const MCOperand &MO2 = MI->getOperand(OpNum+1);
733 unsigned Reg = MO1.getReg();
734 O << getRegisterName(Reg);
736 // Print the shift opc.
737 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
738 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
739 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
740 if (ShOpc != ARM_AM::rrx)
741 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
744 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
746 const MCOperand &MO1 = MI->getOperand(OpNum);
747 const MCOperand &MO2 = MI->getOperand(OpNum+1);
749 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
750 printOperand(MI, OpNum, O);
754 O << "[" << getRegisterName(MO1.getReg());
756 int32_t OffImm = (int32_t)MO2.getImm();
757 bool isSub = OffImm < 0;
758 // Special value for #-0. All others are normal.
759 if (OffImm == INT32_MIN)
762 O << ", #-" << -OffImm;
764 O << ", #" << OffImm;
768 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
771 const MCOperand &MO1 = MI->getOperand(OpNum);
772 const MCOperand &MO2 = MI->getOperand(OpNum+1);
774 O << "[" << getRegisterName(MO1.getReg());
776 int32_t OffImm = (int32_t)MO2.getImm();
779 O << ", #-" << -OffImm;
781 O << ", #" << OffImm;
785 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
788 const MCOperand &MO1 = MI->getOperand(OpNum);
789 const MCOperand &MO2 = MI->getOperand(OpNum+1);
791 O << "[" << getRegisterName(MO1.getReg());
793 int32_t OffImm = (int32_t)MO2.getImm() / 4;
796 O << ", #-" << -OffImm * 4;
798 O << ", #" << OffImm * 4;
802 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
805 const MCOperand &MO1 = MI->getOperand(OpNum);
806 int32_t OffImm = (int32_t)MO1.getImm();
809 O << "#-" << -OffImm;
814 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
817 const MCOperand &MO1 = MI->getOperand(OpNum);
818 int32_t OffImm = (int32_t)MO1.getImm() / 4;
821 O << "#-" << -OffImm * 4;
823 O << "#" << OffImm * 4;
826 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
829 const MCOperand &MO1 = MI->getOperand(OpNum);
830 const MCOperand &MO2 = MI->getOperand(OpNum+1);
831 const MCOperand &MO3 = MI->getOperand(OpNum+2);
833 O << "[" << getRegisterName(MO1.getReg());
835 assert(MO2.getReg() && "Invalid so_reg load / store address!");
836 O << ", " << getRegisterName(MO2.getReg());
838 unsigned ShAmt = MO3.getImm();
840 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
841 O << ", lsl #" << ShAmt;
846 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
848 const MCOperand &MO = MI->getOperand(OpNum);
851 O << (float)MO.getFPImm();
858 FPUnion.I = MO.getImm();
863 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
865 const MCOperand &MO = MI->getOperand(OpNum);
870 // We expect the binary encoding of a floating point number here.
876 FPUnion.I = MO.getImm();
881 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
883 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
885 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
886 O << "#0x" << utohexstr(Val);
889 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
891 unsigned Imm = MI->getOperand(OpNum).getImm();
895 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
897 unsigned Imm = MI->getOperand(OpNum).getImm();
902 default: assert (0 && "illegal ror immediate!");
903 case 1: O << "8"; break;
904 case 2: O << "16"; break;
905 case 3: O << "24"; break;