1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
32 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
33 OS << getRegisterName(RegNo);
36 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
37 unsigned Opcode = MI->getOpcode();
39 // Check for MOVs and print canonical forms, instead.
40 if (Opcode == ARM::MOVs) {
41 // FIXME: Thumb variants?
42 const MCOperand &Dst = MI->getOperand(0);
43 const MCOperand &MO1 = MI->getOperand(1);
44 const MCOperand &MO2 = MI->getOperand(2);
45 const MCOperand &MO3 = MI->getOperand(3);
47 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
48 printSBitModifierOperand(MI, 6, O);
49 printPredicateOperand(MI, 4, O);
51 O << '\t' << getRegisterName(Dst.getReg())
52 << ", " << getRegisterName(MO1.getReg());
54 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
60 O << getRegisterName(MO2.getReg());
61 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
63 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
69 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
70 MI->getOperand(0).getReg() == ARM::SP) {
72 printPredicateOperand(MI, 2, O);
73 if (Opcode == ARM::t2STMDB_UPD)
76 printRegisterList(MI, 4, O);
81 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
82 MI->getOperand(0).getReg() == ARM::SP) {
84 printPredicateOperand(MI, 2, O);
85 if (Opcode == ARM::t2LDMIA_UPD)
88 printRegisterList(MI, 4, O);
93 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
94 MI->getOperand(0).getReg() == ARM::SP) {
96 printPredicateOperand(MI, 2, O);
98 printRegisterList(MI, 4, O);
103 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
104 MI->getOperand(0).getReg() == ARM::SP) {
106 printPredicateOperand(MI, 2, O);
108 printRegisterList(MI, 4, O);
112 if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
113 bool Writeback = true;
114 unsigned BaseReg = MI->getOperand(0).getReg();
115 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
116 if (MI->getOperand(i).getReg() == BaseReg)
120 if (Opcode == ARM::tLDMIA)
122 else if (Opcode == ARM::tSTMIA)
125 llvm_unreachable("Unknown opcode!");
127 printPredicateOperand(MI, 1, O);
128 O << '\t' << getRegisterName(BaseReg);
129 if (Writeback) O << "!";
131 printRegisterList(MI, 3, O);
135 printInstruction(MI, O);
138 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
140 const MCOperand &Op = MI->getOperand(OpNo);
142 unsigned Reg = Op.getReg();
143 O << getRegisterName(Reg);
144 } else if (Op.isImm()) {
145 O << '#' << Op.getImm();
147 assert(Op.isExpr() && "unknown operand kind in printOperand");
152 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
153 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
155 // REG REG 0,SH_OPC - e.g. R5, ROR R3
156 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
157 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
159 const MCOperand &MO1 = MI->getOperand(OpNum);
160 const MCOperand &MO2 = MI->getOperand(OpNum+1);
161 const MCOperand &MO3 = MI->getOperand(OpNum+2);
163 O << getRegisterName(MO1.getReg());
165 // Print the shift opc.
166 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
167 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
168 if (ShOpc == ARM_AM::rrx)
171 O << ' ' << getRegisterName(MO2.getReg());
172 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
173 } else if (ShOpc != ARM_AM::rrx) {
174 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
178 //===--------------------------------------------------------------------===//
179 // Addressing Mode #2
180 //===--------------------------------------------------------------------===//
182 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
184 const MCOperand &MO1 = MI->getOperand(Op);
185 const MCOperand &MO2 = MI->getOperand(Op+1);
186 const MCOperand &MO3 = MI->getOperand(Op+2);
188 O << "[" << getRegisterName(MO1.getReg());
191 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
193 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
194 << ARM_AM::getAM2Offset(MO3.getImm());
200 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
201 << getRegisterName(MO2.getReg());
203 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
205 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
210 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
212 const MCOperand &MO1 = MI->getOperand(Op);
213 const MCOperand &MO2 = MI->getOperand(Op+1);
214 const MCOperand &MO3 = MI->getOperand(Op+2);
216 O << "[" << getRegisterName(MO1.getReg()) << "], ";
219 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
221 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
226 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
227 << getRegisterName(MO2.getReg());
229 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
231 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
235 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
237 const MCOperand &MO1 = MI->getOperand(Op);
239 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
240 printOperand(MI, Op, O);
244 const MCOperand &MO3 = MI->getOperand(Op+2);
245 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
247 if (IdxMode == ARMII::IndexModePost) {
248 printAM2PostIndexOp(MI, Op, O);
251 printAM2PreOrOffsetIndexOp(MI, Op, O);
254 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
257 const MCOperand &MO1 = MI->getOperand(OpNum);
258 const MCOperand &MO2 = MI->getOperand(OpNum+1);
261 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
263 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
268 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
269 << getRegisterName(MO1.getReg());
271 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
273 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
277 //===--------------------------------------------------------------------===//
278 // Addressing Mode #3
279 //===--------------------------------------------------------------------===//
281 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
283 const MCOperand &MO1 = MI->getOperand(Op);
284 const MCOperand &MO2 = MI->getOperand(Op+1);
285 const MCOperand &MO3 = MI->getOperand(Op+2);
287 O << "[" << getRegisterName(MO1.getReg()) << "], ";
290 O << (char)ARM_AM::getAM3Op(MO3.getImm())
291 << getRegisterName(MO2.getReg());
295 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
297 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
301 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
303 const MCOperand &MO1 = MI->getOperand(Op);
304 const MCOperand &MO2 = MI->getOperand(Op+1);
305 const MCOperand &MO3 = MI->getOperand(Op+2);
307 O << '[' << getRegisterName(MO1.getReg());
310 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
311 << getRegisterName(MO2.getReg()) << ']';
315 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
317 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
322 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
324 const MCOperand &MO3 = MI->getOperand(Op+2);
325 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
327 if (IdxMode == ARMII::IndexModePost) {
328 printAM3PostIndexOp(MI, Op, O);
331 printAM3PreOrOffsetIndexOp(MI, Op, O);
334 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
337 const MCOperand &MO1 = MI->getOperand(OpNum);
338 const MCOperand &MO2 = MI->getOperand(OpNum+1);
341 O << (char)ARM_AM::getAM3Op(MO2.getImm())
342 << getRegisterName(MO1.getReg());
346 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
348 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
352 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
354 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
356 O << ARM_AM::getAMSubModeStr(Mode);
359 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
361 const MCOperand &MO1 = MI->getOperand(OpNum);
362 const MCOperand &MO2 = MI->getOperand(OpNum+1);
364 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
365 printOperand(MI, OpNum, O);
369 O << "[" << getRegisterName(MO1.getReg());
371 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
373 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
379 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
381 const MCOperand &MO1 = MI->getOperand(OpNum);
382 const MCOperand &MO2 = MI->getOperand(OpNum+1);
384 O << "[" << getRegisterName(MO1.getReg());
386 // FIXME: Both darwin as and GNU as violate ARM docs here.
387 O << ", :" << (MO2.getImm() << 3);
392 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
394 const MCOperand &MO1 = MI->getOperand(OpNum);
395 O << "[" << getRegisterName(MO1.getReg()) << "]";
398 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
401 const MCOperand &MO = MI->getOperand(OpNum);
402 if (MO.getReg() == 0)
405 O << ", " << getRegisterName(MO.getReg());
408 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
411 const MCOperand &MO = MI->getOperand(OpNum);
412 uint32_t v = ~MO.getImm();
413 int32_t lsb = CountTrailingZeros_32(v);
414 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
415 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
416 O << '#' << lsb << ", #" << width;
419 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
421 unsigned val = MI->getOperand(OpNum).getImm();
422 O << ARM_MB::MemBOptToString(val);
425 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
427 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
428 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
430 case ARM_AM::no_shift:
439 assert(0 && "unexpected shift opcode for shift immediate operand");
441 O << ARM_AM::getSORegOffset(ShiftOp);
444 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
446 unsigned Imm = MI->getOperand(OpNum).getImm();
449 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
450 O << ", lsl #" << Imm;
453 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
455 unsigned Imm = MI->getOperand(OpNum).getImm();
456 // A shift amount of 32 is encoded as 0.
459 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
460 O << ", asr #" << Imm;
463 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
466 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
467 if (i != OpNum) O << ", ";
468 O << getRegisterName(MI->getOperand(i).getReg());
473 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
475 const MCOperand &Op = MI->getOperand(OpNum);
482 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
484 const MCOperand &Op = MI->getOperand(OpNum);
485 O << ARM_PROC::IModToString(Op.getImm());
488 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
490 const MCOperand &Op = MI->getOperand(OpNum);
491 unsigned IFlags = Op.getImm();
492 for (int i=2; i >= 0; --i)
493 if (IFlags & (1 << i))
494 O << ARM_PROC::IFlagsToString(1 << i);
497 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
499 const MCOperand &Op = MI->getOperand(OpNum);
500 unsigned SpecRegRBit = Op.getImm() >> 4;
501 unsigned Mask = Op.getImm() & 0xf;
503 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
504 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
505 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
509 case 4: O << "g"; return;
510 case 8: O << "nzcvq"; return;
511 case 12: O << "nzcvqg"; return;
513 llvm_unreachable("Unexpected mask value!");
523 if (Mask & 8) O << 'f';
524 if (Mask & 4) O << 's';
525 if (Mask & 2) O << 'x';
526 if (Mask & 1) O << 'c';
530 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
532 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
534 O << ARMCondCodeToString(CC);
537 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
540 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
541 O << ARMCondCodeToString(CC);
544 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
546 if (MI->getOperand(OpNum).getReg()) {
547 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
548 "Expect ARM CPSR register!");
553 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
555 O << MI->getOperand(OpNum).getImm();
558 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
560 O << "p" << MI->getOperand(OpNum).getImm();
563 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
565 O << "c" << MI->getOperand(OpNum).getImm();
568 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
570 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
573 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
575 O << "#" << MI->getOperand(OpNum).getImm() * 4;
578 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
580 // (3 - the number of trailing zeros) is the number of then / else.
581 unsigned Mask = MI->getOperand(OpNum).getImm();
582 unsigned CondBit0 = Mask >> 4 & 1;
583 unsigned NumTZ = CountTrailingZeros_32(Mask);
584 assert(NumTZ <= 3 && "Invalid IT mask!");
585 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
586 bool T = ((Mask >> Pos) & 1) == CondBit0;
594 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
596 const MCOperand &MO1 = MI->getOperand(Op);
597 const MCOperand &MO2 = MI->getOperand(Op + 1);
599 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
600 printOperand(MI, Op, O);
604 O << "[" << getRegisterName(MO1.getReg());
605 if (unsigned RegNum = MO2.getReg())
606 O << ", " << getRegisterName(RegNum);
610 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
614 const MCOperand &MO1 = MI->getOperand(Op);
615 const MCOperand &MO2 = MI->getOperand(Op + 1);
617 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
618 printOperand(MI, Op, O);
622 O << "[" << getRegisterName(MO1.getReg());
623 if (unsigned ImmOffs = MO2.getImm())
624 O << ", #" << ImmOffs * Scale;
628 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
631 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
634 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
637 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
640 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
643 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
646 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
648 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
651 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
652 // register with shift forms.
654 // REG IMM, SH_OPC - e.g. R5, LSL #3
655 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
657 const MCOperand &MO1 = MI->getOperand(OpNum);
658 const MCOperand &MO2 = MI->getOperand(OpNum+1);
660 unsigned Reg = MO1.getReg();
661 O << getRegisterName(Reg);
663 // Print the shift opc.
664 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
665 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
666 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
667 if (ShOpc != ARM_AM::rrx)
668 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
671 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
673 const MCOperand &MO1 = MI->getOperand(OpNum);
674 const MCOperand &MO2 = MI->getOperand(OpNum+1);
676 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
677 printOperand(MI, OpNum, O);
681 O << "[" << getRegisterName(MO1.getReg());
683 int32_t OffImm = (int32_t)MO2.getImm();
684 bool isSub = OffImm < 0;
685 // Special value for #-0. All others are normal.
686 if (OffImm == INT32_MIN)
689 O << ", #-" << -OffImm;
691 O << ", #" << OffImm;
695 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
698 const MCOperand &MO1 = MI->getOperand(OpNum);
699 const MCOperand &MO2 = MI->getOperand(OpNum+1);
701 O << "[" << getRegisterName(MO1.getReg());
703 int32_t OffImm = (int32_t)MO2.getImm();
706 O << ", #-" << -OffImm;
708 O << ", #" << OffImm;
712 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
715 const MCOperand &MO1 = MI->getOperand(OpNum);
716 const MCOperand &MO2 = MI->getOperand(OpNum+1);
718 O << "[" << getRegisterName(MO1.getReg());
720 int32_t OffImm = (int32_t)MO2.getImm() / 4;
723 O << ", #-" << -OffImm * 4;
725 O << ", #" << OffImm * 4;
729 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
732 const MCOperand &MO1 = MI->getOperand(OpNum);
733 int32_t OffImm = (int32_t)MO1.getImm();
736 O << "#-" << -OffImm;
741 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
744 const MCOperand &MO1 = MI->getOperand(OpNum);
745 int32_t OffImm = (int32_t)MO1.getImm() / 4;
748 O << "#-" << -OffImm * 4;
750 O << "#" << OffImm * 4;
753 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
756 const MCOperand &MO1 = MI->getOperand(OpNum);
757 const MCOperand &MO2 = MI->getOperand(OpNum+1);
758 const MCOperand &MO3 = MI->getOperand(OpNum+2);
760 O << "[" << getRegisterName(MO1.getReg());
762 assert(MO2.getReg() && "Invalid so_reg load / store address!");
763 O << ", " << getRegisterName(MO2.getReg());
765 unsigned ShAmt = MO3.getImm();
767 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
768 O << ", lsl #" << ShAmt;
773 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
775 const MCOperand &MO = MI->getOperand(OpNum);
778 O << (float)MO.getFPImm();
785 FPUnion.I = MO.getImm();
790 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
792 const MCOperand &MO = MI->getOperand(OpNum);
797 // We expect the binary encoding of a floating point number here.
803 FPUnion.I = MO.getImm();
808 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
810 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
812 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
813 O << "#0x" << utohexstr(Val);