1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
31 /// 32 as the immediate shouldbe within the range 1-32.
32 static unsigned translateShiftImm(unsigned imm) {
39 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
40 const MCSubtargetInfo &STI) :
42 // Initialize the set of available features.
43 setAvailableFeatures(STI.getFeatureBits());
46 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
47 return getInstructionName(Opcode);
50 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 OS << getRegisterName(RegNo);
54 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
56 unsigned Opcode = MI->getOpcode();
58 // Check for MOVs and print canonical forms, instead.
59 if (Opcode == ARM::MOVsr) {
60 // FIXME: Thumb variants?
61 const MCOperand &Dst = MI->getOperand(0);
62 const MCOperand &MO1 = MI->getOperand(1);
63 const MCOperand &MO2 = MI->getOperand(2);
64 const MCOperand &MO3 = MI->getOperand(3);
66 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
67 printSBitModifierOperand(MI, 6, O);
68 printPredicateOperand(MI, 4, O);
70 O << '\t' << getRegisterName(Dst.getReg())
71 << ", " << getRegisterName(MO1.getReg());
73 O << ", " << getRegisterName(MO2.getReg());
74 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
75 printAnnotation(O, Annot);
79 if (Opcode == ARM::MOVsi) {
80 // FIXME: Thumb variants?
81 const MCOperand &Dst = MI->getOperand(0);
82 const MCOperand &MO1 = MI->getOperand(1);
83 const MCOperand &MO2 = MI->getOperand(2);
85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
86 printSBitModifierOperand(MI, 5, O);
87 printPredicateOperand(MI, 3, O);
89 O << '\t' << getRegisterName(Dst.getReg())
90 << ", " << getRegisterName(MO1.getReg());
92 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
93 printAnnotation(O, Annot);
97 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
98 printAnnotation(O, Annot);
104 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
105 MI->getOperand(0).getReg() == ARM::SP) {
107 printPredicateOperand(MI, 2, O);
108 if (Opcode == ARM::t2STMDB_UPD)
111 printRegisterList(MI, 4, O);
112 printAnnotation(O, Annot);
115 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
116 MI->getOperand(3).getImm() == -4) {
118 printPredicateOperand(MI, 4, O);
119 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
120 printAnnotation(O, Annot);
125 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
126 MI->getOperand(0).getReg() == ARM::SP) {
128 printPredicateOperand(MI, 2, O);
129 if (Opcode == ARM::t2LDMIA_UPD)
132 printRegisterList(MI, 4, O);
133 printAnnotation(O, Annot);
136 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
137 MI->getOperand(4).getImm() == 4) {
139 printPredicateOperand(MI, 5, O);
140 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
141 printAnnotation(O, Annot);
147 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
148 MI->getOperand(0).getReg() == ARM::SP) {
149 O << '\t' << "vpush";
150 printPredicateOperand(MI, 2, O);
152 printRegisterList(MI, 4, O);
153 printAnnotation(O, Annot);
158 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
159 MI->getOperand(0).getReg() == ARM::SP) {
161 printPredicateOperand(MI, 2, O);
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
168 if (Opcode == ARM::tLDMIA) {
169 bool Writeback = true;
170 unsigned BaseReg = MI->getOperand(0).getReg();
171 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
172 if (MI->getOperand(i).getReg() == BaseReg)
178 printPredicateOperand(MI, 1, O);
179 O << '\t' << getRegisterName(BaseReg);
180 if (Writeback) O << "!";
182 printRegisterList(MI, 3, O);
183 printAnnotation(O, Annot);
188 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
189 MI->getOperand(1).getReg() == ARM::R8) {
191 printPredicateOperand(MI, 2, O);
192 printAnnotation(O, Annot);
196 printInstruction(MI, O);
197 printAnnotation(O, Annot);
200 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
202 const MCOperand &Op = MI->getOperand(OpNo);
204 unsigned Reg = Op.getReg();
205 O << getRegisterName(Reg);
206 } else if (Op.isImm()) {
207 O << '#' << Op.getImm();
209 assert(Op.isExpr() && "unknown operand kind in printOperand");
214 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
216 const MCOperand &MO1 = MI->getOperand(OpNum);
219 else if (MO1.isImm())
220 O << "[pc, #" << MO1.getImm() << "]";
222 llvm_unreachable("Unknown LDR label operand?");
225 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
226 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
228 // REG REG 0,SH_OPC - e.g. R5, ROR R3
229 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
230 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
232 const MCOperand &MO1 = MI->getOperand(OpNum);
233 const MCOperand &MO2 = MI->getOperand(OpNum+1);
234 const MCOperand &MO3 = MI->getOperand(OpNum+2);
236 O << getRegisterName(MO1.getReg());
238 // Print the shift opc.
239 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
240 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
241 if (ShOpc == ARM_AM::rrx)
244 O << ' ' << getRegisterName(MO2.getReg());
245 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
248 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
250 const MCOperand &MO1 = MI->getOperand(OpNum);
251 const MCOperand &MO2 = MI->getOperand(OpNum+1);
253 O << getRegisterName(MO1.getReg());
255 // Print the shift opc.
256 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
257 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
258 if (ShOpc == ARM_AM::rrx)
260 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
264 //===--------------------------------------------------------------------===//
265 // Addressing Mode #2
266 //===--------------------------------------------------------------------===//
268 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
270 const MCOperand &MO1 = MI->getOperand(Op);
271 const MCOperand &MO2 = MI->getOperand(Op+1);
272 const MCOperand &MO3 = MI->getOperand(Op+2);
274 O << "[" << getRegisterName(MO1.getReg());
277 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
279 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
280 << ARM_AM::getAM2Offset(MO3.getImm());
286 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
287 << getRegisterName(MO2.getReg());
289 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
291 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
296 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
298 const MCOperand &MO1 = MI->getOperand(Op);
299 const MCOperand &MO2 = MI->getOperand(Op+1);
300 const MCOperand &MO3 = MI->getOperand(Op+2);
302 O << "[" << getRegisterName(MO1.getReg()) << "], ";
305 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
307 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
312 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
313 << getRegisterName(MO2.getReg());
315 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
317 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
321 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
323 const MCOperand &MO1 = MI->getOperand(Op);
324 const MCOperand &MO2 = MI->getOperand(Op+1);
325 O << "[" << getRegisterName(MO1.getReg()) << ", "
326 << getRegisterName(MO2.getReg()) << "]";
329 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
331 const MCOperand &MO1 = MI->getOperand(Op);
332 const MCOperand &MO2 = MI->getOperand(Op+1);
333 O << "[" << getRegisterName(MO1.getReg()) << ", "
334 << getRegisterName(MO2.getReg()) << ", lsl #1]";
337 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
339 const MCOperand &MO1 = MI->getOperand(Op);
341 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
342 printOperand(MI, Op, O);
346 const MCOperand &MO3 = MI->getOperand(Op+2);
347 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
349 if (IdxMode == ARMII::IndexModePost) {
350 printAM2PostIndexOp(MI, Op, O);
353 printAM2PreOrOffsetIndexOp(MI, Op, O);
356 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
359 const MCOperand &MO1 = MI->getOperand(OpNum);
360 const MCOperand &MO2 = MI->getOperand(OpNum+1);
363 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
365 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
370 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
371 << getRegisterName(MO1.getReg());
373 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
375 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
379 //===--------------------------------------------------------------------===//
380 // Addressing Mode #3
381 //===--------------------------------------------------------------------===//
383 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
385 const MCOperand &MO1 = MI->getOperand(Op);
386 const MCOperand &MO2 = MI->getOperand(Op+1);
387 const MCOperand &MO3 = MI->getOperand(Op+2);
389 O << "[" << getRegisterName(MO1.getReg()) << "], ";
392 O << (char)ARM_AM::getAM3Op(MO3.getImm())
393 << getRegisterName(MO2.getReg());
397 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
399 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
403 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
405 const MCOperand &MO1 = MI->getOperand(Op);
406 const MCOperand &MO2 = MI->getOperand(Op+1);
407 const MCOperand &MO3 = MI->getOperand(Op+2);
409 O << '[' << getRegisterName(MO1.getReg());
412 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
413 << getRegisterName(MO2.getReg()) << ']';
417 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
419 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
424 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
426 const MCOperand &MO3 = MI->getOperand(Op+2);
427 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
429 if (IdxMode == ARMII::IndexModePost) {
430 printAM3PostIndexOp(MI, Op, O);
433 printAM3PreOrOffsetIndexOp(MI, Op, O);
436 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
439 const MCOperand &MO1 = MI->getOperand(OpNum);
440 const MCOperand &MO2 = MI->getOperand(OpNum+1);
443 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
444 << getRegisterName(MO1.getReg());
448 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
450 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
454 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
457 const MCOperand &MO = MI->getOperand(OpNum);
458 unsigned Imm = MO.getImm();
459 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
462 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
464 const MCOperand &MO1 = MI->getOperand(OpNum);
465 const MCOperand &MO2 = MI->getOperand(OpNum+1);
467 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
470 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
473 const MCOperand &MO = MI->getOperand(OpNum);
474 unsigned Imm = MO.getImm();
475 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
479 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
481 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
483 O << ARM_AM::getAMSubModeStr(Mode);
486 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
488 const MCOperand &MO1 = MI->getOperand(OpNum);
489 const MCOperand &MO2 = MI->getOperand(OpNum+1);
491 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
492 printOperand(MI, OpNum, O);
496 O << "[" << getRegisterName(MO1.getReg());
498 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
499 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
500 if (ImmOffs || Op == ARM_AM::sub) {
502 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
508 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
510 const MCOperand &MO1 = MI->getOperand(OpNum);
511 const MCOperand &MO2 = MI->getOperand(OpNum+1);
513 O << "[" << getRegisterName(MO1.getReg());
515 // FIXME: Both darwin as and GNU as violate ARM docs here.
516 O << ", :" << (MO2.getImm() << 3);
521 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
523 const MCOperand &MO1 = MI->getOperand(OpNum);
524 O << "[" << getRegisterName(MO1.getReg()) << "]";
527 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
530 const MCOperand &MO = MI->getOperand(OpNum);
531 if (MO.getReg() == 0)
534 O << ", " << getRegisterName(MO.getReg());
537 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
540 const MCOperand &MO = MI->getOperand(OpNum);
541 uint32_t v = ~MO.getImm();
542 int32_t lsb = CountTrailingZeros_32(v);
543 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
544 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
545 O << '#' << lsb << ", #" << width;
548 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
550 unsigned val = MI->getOperand(OpNum).getImm();
551 O << ARM_MB::MemBOptToString(val);
554 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
556 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
557 bool isASR = (ShiftOp & (1 << 5)) != 0;
558 unsigned Amt = ShiftOp & 0x1f;
560 O << ", asr #" << (Amt == 0 ? 32 : Amt);
562 O << ", lsl #" << Amt;
565 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
567 unsigned Imm = MI->getOperand(OpNum).getImm();
570 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
571 O << ", lsl #" << Imm;
574 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
576 unsigned Imm = MI->getOperand(OpNum).getImm();
577 // A shift amount of 32 is encoded as 0.
580 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
581 O << ", asr #" << Imm;
584 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
587 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
588 if (i != OpNum) O << ", ";
589 O << getRegisterName(MI->getOperand(i).getReg());
594 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
596 const MCOperand &Op = MI->getOperand(OpNum);
603 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
605 const MCOperand &Op = MI->getOperand(OpNum);
606 O << ARM_PROC::IModToString(Op.getImm());
609 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
611 const MCOperand &Op = MI->getOperand(OpNum);
612 unsigned IFlags = Op.getImm();
613 for (int i=2; i >= 0; --i)
614 if (IFlags & (1 << i))
615 O << ARM_PROC::IFlagsToString(1 << i);
618 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
620 const MCOperand &Op = MI->getOperand(OpNum);
621 unsigned SpecRegRBit = Op.getImm() >> 4;
622 unsigned Mask = Op.getImm() & 0xf;
624 if (getAvailableFeatures() & ARM::FeatureMClass) {
625 switch (Op.getImm()) {
626 default: assert(0 && "Unexpected mask value!");
627 case 0: O << "apsr"; return;
628 case 1: O << "iapsr"; return;
629 case 2: O << "eapsr"; return;
630 case 3: O << "xpsr"; return;
631 case 5: O << "ipsr"; return;
632 case 6: O << "epsr"; return;
633 case 7: O << "iepsr"; return;
634 case 8: O << "msp"; return;
635 case 9: O << "psp"; return;
636 case 16: O << "primask"; return;
637 case 17: O << "basepri"; return;
638 case 18: O << "basepri_max"; return;
639 case 19: O << "faultmask"; return;
640 case 20: O << "control"; return;
644 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
645 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
646 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
650 case 4: O << "g"; return;
651 case 8: O << "nzcvq"; return;
652 case 12: O << "nzcvqg"; return;
654 llvm_unreachable("Unexpected mask value!");
664 if (Mask & 8) O << 'f';
665 if (Mask & 4) O << 's';
666 if (Mask & 2) O << 'x';
667 if (Mask & 1) O << 'c';
671 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
673 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
675 O << ARMCondCodeToString(CC);
678 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
681 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
682 O << ARMCondCodeToString(CC);
685 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
687 if (MI->getOperand(OpNum).getReg()) {
688 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
689 "Expect ARM CPSR register!");
694 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
696 O << MI->getOperand(OpNum).getImm();
699 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
701 O << "p" << MI->getOperand(OpNum).getImm();
704 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
706 O << "c" << MI->getOperand(OpNum).getImm();
709 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
711 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
714 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
716 O << "#" << MI->getOperand(OpNum).getImm() * 4;
719 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
721 unsigned Imm = MI->getOperand(OpNum).getImm();
722 O << "#" << (Imm == 0 ? 32 : Imm);
725 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
727 // (3 - the number of trailing zeros) is the number of then / else.
728 unsigned Mask = MI->getOperand(OpNum).getImm();
729 unsigned CondBit0 = Mask >> 4 & 1;
730 unsigned NumTZ = CountTrailingZeros_32(Mask);
731 assert(NumTZ <= 3 && "Invalid IT mask!");
732 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
733 bool T = ((Mask >> Pos) & 1) == CondBit0;
741 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
743 const MCOperand &MO1 = MI->getOperand(Op);
744 const MCOperand &MO2 = MI->getOperand(Op + 1);
746 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
747 printOperand(MI, Op, O);
751 O << "[" << getRegisterName(MO1.getReg());
752 if (unsigned RegNum = MO2.getReg())
753 O << ", " << getRegisterName(RegNum);
757 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
761 const MCOperand &MO1 = MI->getOperand(Op);
762 const MCOperand &MO2 = MI->getOperand(Op + 1);
764 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
765 printOperand(MI, Op, O);
769 O << "[" << getRegisterName(MO1.getReg());
770 if (unsigned ImmOffs = MO2.getImm())
771 O << ", #" << ImmOffs * Scale;
775 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
778 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
781 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
784 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
787 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
790 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
793 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
795 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
798 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
799 // register with shift forms.
801 // REG IMM, SH_OPC - e.g. R5, LSL #3
802 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
804 const MCOperand &MO1 = MI->getOperand(OpNum);
805 const MCOperand &MO2 = MI->getOperand(OpNum+1);
807 unsigned Reg = MO1.getReg();
808 O << getRegisterName(Reg);
810 // Print the shift opc.
811 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
812 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
813 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
814 if (ShOpc != ARM_AM::rrx)
815 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
818 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
820 const MCOperand &MO1 = MI->getOperand(OpNum);
821 const MCOperand &MO2 = MI->getOperand(OpNum+1);
823 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
824 printOperand(MI, OpNum, O);
828 O << "[" << getRegisterName(MO1.getReg());
830 int32_t OffImm = (int32_t)MO2.getImm();
831 bool isSub = OffImm < 0;
832 // Special value for #-0. All others are normal.
833 if (OffImm == INT32_MIN)
836 O << ", #-" << -OffImm;
838 O << ", #" << OffImm;
842 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
845 const MCOperand &MO1 = MI->getOperand(OpNum);
846 const MCOperand &MO2 = MI->getOperand(OpNum+1);
848 O << "[" << getRegisterName(MO1.getReg());
850 int32_t OffImm = (int32_t)MO2.getImm();
852 if (OffImm == INT32_MIN)
855 O << ", #-" << -OffImm;
857 O << ", #" << OffImm;
861 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
864 const MCOperand &MO1 = MI->getOperand(OpNum);
865 const MCOperand &MO2 = MI->getOperand(OpNum+1);
867 O << "[" << getRegisterName(MO1.getReg());
869 int32_t OffImm = (int32_t)MO2.getImm() / 4;
872 O << ", #-" << -OffImm * 4;
874 O << ", #" << OffImm * 4;
878 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
881 const MCOperand &MO1 = MI->getOperand(OpNum);
882 const MCOperand &MO2 = MI->getOperand(OpNum+1);
884 O << "[" << getRegisterName(MO1.getReg());
886 O << ", #" << MO2.getImm() * 4;
890 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
893 const MCOperand &MO1 = MI->getOperand(OpNum);
894 int32_t OffImm = (int32_t)MO1.getImm();
897 O << ", #-" << -OffImm;
899 O << ", #" << OffImm;
902 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
905 const MCOperand &MO1 = MI->getOperand(OpNum);
906 int32_t OffImm = (int32_t)MO1.getImm() / 4;
911 O << "#-" << -OffImm * 4;
913 O << "#" << OffImm * 4;
917 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
920 const MCOperand &MO1 = MI->getOperand(OpNum);
921 const MCOperand &MO2 = MI->getOperand(OpNum+1);
922 const MCOperand &MO3 = MI->getOperand(OpNum+2);
924 O << "[" << getRegisterName(MO1.getReg());
926 assert(MO2.getReg() && "Invalid so_reg load / store address!");
927 O << ", " << getRegisterName(MO2.getReg());
929 unsigned ShAmt = MO3.getImm();
931 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
932 O << ", lsl #" << ShAmt;
937 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
939 const MCOperand &MO = MI->getOperand(OpNum);
940 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
943 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
945 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
947 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
948 O << "#0x" << utohexstr(Val);
951 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
953 unsigned Imm = MI->getOperand(OpNum).getImm();
957 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
959 unsigned Imm = MI->getOperand(OpNum).getImm();
964 default: assert (0 && "illegal ror immediate!");
965 case 1: O << "8"; break;
966 case 2: O << "16"; break;
967 case 3: O << "24"; break;