1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
33 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
34 unsigned Opcode = MI->getOpcode();
36 // Check for MOVs and print canonical forms, instead.
37 if (Opcode == ARM::MOVs) {
38 // FIXME: Thumb variants?
39 const MCOperand &Dst = MI->getOperand(0);
40 const MCOperand &MO1 = MI->getOperand(1);
41 const MCOperand &MO2 = MI->getOperand(2);
42 const MCOperand &MO3 = MI->getOperand(3);
44 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
45 printSBitModifierOperand(MI, 6, O);
46 printPredicateOperand(MI, 4, O);
48 O << '\t' << getRegisterName(Dst.getReg())
49 << ", " << getRegisterName(MO1.getReg());
51 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
57 O << getRegisterName(MO2.getReg());
58 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
60 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
66 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
67 MI->getOperand(0).getReg() == ARM::SP) {
69 printPredicateOperand(MI, 2, O);
71 printRegisterList(MI, 4, O);
76 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
77 MI->getOperand(0).getReg() == ARM::SP) {
79 printPredicateOperand(MI, 2, O);
81 printRegisterList(MI, 4, O);
86 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
87 MI->getOperand(0).getReg() == ARM::SP) {
89 printPredicateOperand(MI, 2, O);
91 printRegisterList(MI, 4, O);
96 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
97 MI->getOperand(0).getReg() == ARM::SP) {
99 printPredicateOperand(MI, 2, O);
101 printRegisterList(MI, 4, O);
105 printInstruction(MI, O);
108 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
110 const MCOperand &Op = MI->getOperand(OpNo);
112 unsigned Reg = Op.getReg();
113 O << getRegisterName(Reg);
114 } else if (Op.isImm()) {
115 O << '#' << Op.getImm();
117 assert(Op.isExpr() && "unknown operand kind in printOperand");
122 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
123 const MCAsmInfo *MAI) {
124 // Break it up into two parts that make up a shifter immediate.
125 V = ARM_AM::getSOImmVal(V);
126 assert(V != -1 && "Not a valid so_imm value!");
128 unsigned Imm = ARM_AM::getSOImmValImm(V);
129 unsigned Rot = ARM_AM::getSOImmValRot(V);
131 // Print low-level immediate formation info, per
132 // A5.1.3: "Data-processing operands - Immediate".
134 O << "#" << Imm << ", " << Rot;
135 // Pretty printed version.
137 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
144 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
145 /// immediate in bits 0-7.
146 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
148 const MCOperand &MO = MI->getOperand(OpNum);
149 assert(MO.isImm() && "Not a valid so_imm value!");
150 printSOImm(O, MO.getImm(), CommentStream, &MAI);
153 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
154 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
156 // REG REG 0,SH_OPC - e.g. R5, ROR R3
157 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
158 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
160 const MCOperand &MO1 = MI->getOperand(OpNum);
161 const MCOperand &MO2 = MI->getOperand(OpNum+1);
162 const MCOperand &MO3 = MI->getOperand(OpNum+2);
164 O << getRegisterName(MO1.getReg());
166 // Print the shift opc.
167 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
168 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
170 O << ' ' << getRegisterName(MO2.getReg());
171 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
172 } else if (ShOpc != ARM_AM::rrx) {
173 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
178 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
180 const MCOperand &MO1 = MI->getOperand(Op);
181 const MCOperand &MO2 = MI->getOperand(Op+1);
182 const MCOperand &MO3 = MI->getOperand(Op+2);
184 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
185 printOperand(MI, Op, O);
189 O << "[" << getRegisterName(MO1.getReg());
192 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
194 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
195 << ARM_AM::getAM2Offset(MO3.getImm());
201 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
202 << getRegisterName(MO2.getReg());
204 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
206 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
211 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
214 const MCOperand &MO1 = MI->getOperand(OpNum);
215 const MCOperand &MO2 = MI->getOperand(OpNum+1);
218 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
220 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
225 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
226 << getRegisterName(MO1.getReg());
228 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
230 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
234 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
236 const MCOperand &MO1 = MI->getOperand(OpNum);
237 const MCOperand &MO2 = MI->getOperand(OpNum+1);
238 const MCOperand &MO3 = MI->getOperand(OpNum+2);
240 O << '[' << getRegisterName(MO1.getReg());
243 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
244 << getRegisterName(MO2.getReg()) << ']';
248 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
250 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
255 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
258 const MCOperand &MO1 = MI->getOperand(OpNum);
259 const MCOperand &MO2 = MI->getOperand(OpNum+1);
262 O << (char)ARM_AM::getAM3Op(MO2.getImm())
263 << getRegisterName(MO1.getReg());
267 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
269 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
273 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
275 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
277 O << ARM_AM::getAMSubModeStr(Mode);
280 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
282 const MCOperand &MO1 = MI->getOperand(OpNum);
283 const MCOperand &MO2 = MI->getOperand(OpNum+1);
285 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
286 printOperand(MI, OpNum, O);
290 O << "[" << getRegisterName(MO1.getReg());
292 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
294 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
300 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
302 const MCOperand &MO1 = MI->getOperand(OpNum);
303 const MCOperand &MO2 = MI->getOperand(OpNum+1);
305 O << "[" << getRegisterName(MO1.getReg());
307 // FIXME: Both darwin as and GNU as violate ARM docs here.
308 O << ", :" << (MO2.getImm() << 3);
313 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
316 const MCOperand &MO = MI->getOperand(OpNum);
317 if (MO.getReg() == 0)
320 O << ", " << getRegisterName(MO.getReg());
323 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
326 const MCOperand &MO = MI->getOperand(OpNum);
327 uint32_t v = ~MO.getImm();
328 int32_t lsb = CountTrailingZeros_32(v);
329 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
330 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
331 O << '#' << lsb << ", #" << width;
334 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
336 unsigned val = MI->getOperand(OpNum).getImm();
337 O << ARM_MB::MemBOptToString(val);
340 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
342 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
343 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
345 case ARM_AM::no_shift:
354 assert(0 && "unexpected shift opcode for shift immediate operand");
356 O << ARM_AM::getSORegOffset(ShiftOp);
359 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
362 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
363 if (i != OpNum) O << ", ";
364 O << getRegisterName(MI->getOperand(i).getReg());
369 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
371 const MCOperand &Op = MI->getOperand(OpNum);
378 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
380 const MCOperand &Op = MI->getOperand(OpNum);
381 unsigned option = Op.getImm();
382 unsigned mode = option & 31;
383 bool changemode = option >> 5 & 1;
384 unsigned AIF = option >> 6 & 7;
385 unsigned imod = option >> 9 & 3;
392 if (AIF & 4) O << 'a';
393 if (AIF & 2) O << 'i';
394 if (AIF & 1) O << 'f';
395 if (AIF > 0 && changemode) O << ", ";
401 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
403 const MCOperand &Op = MI->getOperand(OpNum);
404 unsigned Mask = Op.getImm();
407 if (Mask & 8) O << 'f';
408 if (Mask & 4) O << 's';
409 if (Mask & 2) O << 'x';
410 if (Mask & 1) O << 'c';
414 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
416 const MCOperand &Op = MI->getOperand(OpNum);
419 O << '-' << (-Op.getImm() - 1);
424 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
426 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
428 O << ARMCondCodeToString(CC);
431 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
434 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
435 O << ARMCondCodeToString(CC);
438 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
440 if (MI->getOperand(OpNum).getReg()) {
441 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
442 "Expect ARM CPSR register!");
447 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
449 O << MI->getOperand(OpNum).getImm();
452 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
454 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
457 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
459 O << "#" << MI->getOperand(OpNum).getImm() * 4;
462 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
464 // (3 - the number of trailing zeros) is the number of then / else.
465 unsigned Mask = MI->getOperand(OpNum).getImm();
466 unsigned CondBit0 = Mask >> 4 & 1;
467 unsigned NumTZ = CountTrailingZeros_32(Mask);
468 assert(NumTZ <= 3 && "Invalid IT mask!");
469 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
470 bool T = ((Mask >> Pos) & 1) == CondBit0;
478 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
480 const MCOperand &MO1 = MI->getOperand(Op);
481 const MCOperand &MO2 = MI->getOperand(Op+1);
482 O << "[" << getRegisterName(MO1.getReg());
483 O << ", " << getRegisterName(MO2.getReg()) << "]";
486 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
489 const MCOperand &MO1 = MI->getOperand(Op);
490 const MCOperand &MO2 = MI->getOperand(Op+1);
491 const MCOperand &MO3 = MI->getOperand(Op+2);
493 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
494 printOperand(MI, Op, O);
498 O << "[" << getRegisterName(MO1.getReg());
500 O << ", " << getRegisterName(MO3.getReg());
501 else if (unsigned ImmOffs = MO2.getImm())
502 O << ", #" << ImmOffs * Scale;
506 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
508 printThumbAddrModeRI5Operand(MI, Op, O, 1);
511 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
513 printThumbAddrModeRI5Operand(MI, Op, O, 2);
516 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
518 printThumbAddrModeRI5Operand(MI, Op, O, 4);
521 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
523 const MCOperand &MO1 = MI->getOperand(Op);
524 const MCOperand &MO2 = MI->getOperand(Op+1);
525 O << "[" << getRegisterName(MO1.getReg());
526 if (unsigned ImmOffs = MO2.getImm())
527 O << ", #" << ImmOffs*4;
531 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
533 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
534 if (MI->getOpcode() == ARM::t2TBH)
539 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
540 // register with shift forms.
542 // REG IMM, SH_OPC - e.g. R5, LSL #3
543 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
545 const MCOperand &MO1 = MI->getOperand(OpNum);
546 const MCOperand &MO2 = MI->getOperand(OpNum+1);
548 unsigned Reg = MO1.getReg();
549 O << getRegisterName(Reg);
551 // Print the shift opc.
552 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
553 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
554 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
555 if (ShOpc != ARM_AM::rrx)
556 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
559 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
561 const MCOperand &MO1 = MI->getOperand(OpNum);
562 const MCOperand &MO2 = MI->getOperand(OpNum+1);
564 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
565 printOperand(MI, OpNum, O);
569 O << "[" << getRegisterName(MO1.getReg());
571 int32_t OffImm = (int32_t)MO2.getImm();
572 bool isSub = OffImm < 0;
573 // Special value for #-0. All others are normal.
574 if (OffImm == INT32_MIN)
577 O << ", #-" << -OffImm;
579 O << ", #" << OffImm;
583 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
586 const MCOperand &MO1 = MI->getOperand(OpNum);
587 const MCOperand &MO2 = MI->getOperand(OpNum+1);
589 O << "[" << getRegisterName(MO1.getReg());
591 int32_t OffImm = (int32_t)MO2.getImm();
594 O << ", #-" << -OffImm;
596 O << ", #" << OffImm;
600 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
603 const MCOperand &MO1 = MI->getOperand(OpNum);
604 const MCOperand &MO2 = MI->getOperand(OpNum+1);
606 O << "[" << getRegisterName(MO1.getReg());
608 int32_t OffImm = (int32_t)MO2.getImm() / 4;
611 O << ", #-" << -OffImm * 4;
613 O << ", #" << OffImm * 4;
617 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
620 const MCOperand &MO1 = MI->getOperand(OpNum);
621 int32_t OffImm = (int32_t)MO1.getImm();
624 O << "#-" << -OffImm;
629 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
632 const MCOperand &MO1 = MI->getOperand(OpNum);
633 int32_t OffImm = (int32_t)MO1.getImm() / 4;
636 O << "#-" << -OffImm * 4;
638 O << "#" << OffImm * 4;
641 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
644 const MCOperand &MO1 = MI->getOperand(OpNum);
645 const MCOperand &MO2 = MI->getOperand(OpNum+1);
646 const MCOperand &MO3 = MI->getOperand(OpNum+2);
648 O << "[" << getRegisterName(MO1.getReg());
650 assert(MO2.getReg() && "Invalid so_reg load / store address!");
651 O << ", " << getRegisterName(MO2.getReg());
653 unsigned ShAmt = MO3.getImm();
655 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
656 O << ", lsl #" << ShAmt;
661 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
663 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
666 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
668 O << '#' << MI->getOperand(OpNum).getFPImm();
671 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
673 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
675 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
676 O << "#0x" << utohexstr(Val);