1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define DEBUG_TYPE "asm-printer"
27 #include "ARMGenAsmWriter.inc"
29 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
31 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
32 static unsigned translateShiftImm(unsigned imm) {
33 // lsr #32 and asr #32 exist, but should be encoded as a 0.
34 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
41 /// Prints the shift value with an immediate value.
42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
43 unsigned ShImm, bool UseMarkup) {
44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
48 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
49 O << getShiftOpcStr(ShOpc);
51 if (ShOpc != ARM_AM::rrx) {
55 O << "#" << translateShiftImm(ShImm);
61 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI)
63 : MCInstPrinter(MAI, MII, MRI) {}
65 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
66 OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
69 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
70 StringRef Annot, const MCSubtargetInfo &STI) {
71 unsigned Opcode = MI->getOpcode();
75 // Check for HINT instructions w/ canonical names.
79 switch (MI->getOperand(0).getImm()) {
96 if (STI.getFeatureBits()[ARM::HasV8Ops]) {
99 } // Fallthrough for non-v8
101 // Anything else should just print normally.
102 printInstruction(MI, STI, O);
103 printAnnotation(O, Annot);
106 printPredicateOperand(MI, 1, STI, O);
107 if (Opcode == ARM::t2HINT)
109 printAnnotation(O, Annot);
112 // Check for MOVs and print canonical forms, instead.
114 // FIXME: Thumb variants?
115 const MCOperand &Dst = MI->getOperand(0);
116 const MCOperand &MO1 = MI->getOperand(1);
117 const MCOperand &MO2 = MI->getOperand(2);
118 const MCOperand &MO3 = MI->getOperand(3);
120 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
121 printSBitModifierOperand(MI, 6, STI, O);
122 printPredicateOperand(MI, 4, STI, O);
125 printRegName(O, Dst.getReg());
127 printRegName(O, MO1.getReg());
130 printRegName(O, MO2.getReg());
131 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
132 printAnnotation(O, Annot);
137 // FIXME: Thumb variants?
138 const MCOperand &Dst = MI->getOperand(0);
139 const MCOperand &MO1 = MI->getOperand(1);
140 const MCOperand &MO2 = MI->getOperand(2);
142 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
143 printSBitModifierOperand(MI, 5, STI, O);
144 printPredicateOperand(MI, 3, STI, O);
147 printRegName(O, Dst.getReg());
149 printRegName(O, MO1.getReg());
151 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
152 printAnnotation(O, Annot);
156 O << ", " << markup("<imm:") << "#"
157 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
158 printAnnotation(O, Annot);
164 case ARM::t2STMDB_UPD:
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
166 // Should only print PUSH if there are at least two registers in the list.
168 printPredicateOperand(MI, 2, STI, O);
169 if (Opcode == ARM::t2STMDB_UPD)
172 printRegisterList(MI, 4, STI, O);
173 printAnnotation(O, Annot);
178 case ARM::STR_PRE_IMM:
179 if (MI->getOperand(2).getReg() == ARM::SP &&
180 MI->getOperand(3).getImm() == -4) {
182 printPredicateOperand(MI, 4, STI, O);
184 printRegName(O, MI->getOperand(1).getReg());
186 printAnnotation(O, Annot);
193 case ARM::t2LDMIA_UPD:
194 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
195 // Should only print POP if there are at least two registers in the list.
197 printPredicateOperand(MI, 2, STI, O);
198 if (Opcode == ARM::t2LDMIA_UPD)
201 printRegisterList(MI, 4, STI, O);
202 printAnnotation(O, Annot);
207 case ARM::LDR_POST_IMM:
208 if (MI->getOperand(2).getReg() == ARM::SP &&
209 MI->getOperand(4).getImm() == 4) {
211 printPredicateOperand(MI, 5, STI, O);
213 printRegName(O, MI->getOperand(0).getReg());
215 printAnnotation(O, Annot);
221 case ARM::VSTMSDB_UPD:
222 case ARM::VSTMDDB_UPD:
223 if (MI->getOperand(0).getReg() == ARM::SP) {
224 O << '\t' << "vpush";
225 printPredicateOperand(MI, 2, STI, O);
227 printRegisterList(MI, 4, STI, O);
228 printAnnotation(O, Annot);
234 case ARM::VLDMSIA_UPD:
235 case ARM::VLDMDIA_UPD:
236 if (MI->getOperand(0).getReg() == ARM::SP) {
238 printPredicateOperand(MI, 2, STI, O);
240 printRegisterList(MI, 4, STI, O);
241 printAnnotation(O, Annot);
247 bool Writeback = true;
248 unsigned BaseReg = MI->getOperand(0).getReg();
249 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
250 if (MI->getOperand(i).getReg() == BaseReg)
256 printPredicateOperand(MI, 1, STI, O);
258 printRegName(O, BaseReg);
262 printRegisterList(MI, 3, STI, O);
263 printAnnotation(O, Annot);
267 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
268 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
269 // a single GPRPair reg operand is used in the .td file to replace the two
270 // GPRs. However, when decoding them, the two GRPs cannot be automatically
271 // expressed as a GPRPair, so we have to manually merge them.
272 // FIXME: We would really like to be able to tablegen'erate this.
277 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
278 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
279 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
280 if (MRC.contains(Reg)) {
283 NewMI.setOpcode(Opcode);
286 NewMI.addOperand(MI->getOperand(0));
287 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
288 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
289 NewMI.addOperand(NewReg);
291 // Copy the rest operands into NewMI.
292 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
293 NewMI.addOperand(MI->getOperand(i));
294 printInstruction(&NewMI, STI, O);
299 // B9.3.3 ERET (Thumb)
300 // For a target that has Virtualization Extensions, ERET is the preferred
301 // disassembly of SUBS PC, LR, #0
302 case ARM::t2SUBS_PC_LR: {
303 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
304 MI->getOperand(0).getImm() == 0 &&
305 STI.getFeatureBits()[ARM::FeatureVirtualization]) {
307 printPredicateOperand(MI, 1, STI, O);
308 printAnnotation(O, Annot);
315 printInstruction(MI, STI, O);
316 printAnnotation(O, Annot);
319 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
320 const MCSubtargetInfo &STI, raw_ostream &O) {
321 const MCOperand &Op = MI->getOperand(OpNo);
323 unsigned Reg = Op.getReg();
324 printRegName(O, Reg);
325 } else if (Op.isImm()) {
326 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
328 assert(Op.isExpr() && "unknown operand kind in printOperand");
329 const MCExpr *Expr = Op.getExpr();
330 switch (Expr->getKind()) {
334 case MCExpr::Constant: {
335 // If a symbolic branch target was added as a constant expression then
336 // print that address in hex. And only print 32 unsigned bits for the
338 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
339 int64_t TargetAddress;
340 if (!Constant->evaluateAsAbsolute(TargetAddress)) {
344 O.write_hex(static_cast<uint32_t>(TargetAddress));
349 // FIXME: Should we always treat this as if it is a constant literal and
350 // prefix it with '#'?
357 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
358 const MCSubtargetInfo &STI,
360 const MCOperand &MO1 = MI->getOperand(OpNum);
366 O << markup("<mem:") << "[pc, ";
368 int32_t OffImm = (int32_t)MO1.getImm();
369 bool isSub = OffImm < 0;
371 // Special value for #-0. All others are normal.
372 if (OffImm == INT32_MIN)
375 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
377 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
379 O << "]" << markup(">");
382 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
383 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
385 // REG REG 0,SH_OPC - e.g. R5, ROR R3
386 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
387 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
388 const MCSubtargetInfo &STI,
390 const MCOperand &MO1 = MI->getOperand(OpNum);
391 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
392 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
394 printRegName(O, MO1.getReg());
396 // Print the shift opc.
397 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
398 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
399 if (ShOpc == ARM_AM::rrx)
403 printRegName(O, MO2.getReg());
404 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
407 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
408 const MCSubtargetInfo &STI,
410 const MCOperand &MO1 = MI->getOperand(OpNum);
411 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
413 printRegName(O, MO1.getReg());
415 // Print the shift opc.
416 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
417 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
420 //===--------------------------------------------------------------------===//
421 // Addressing Mode #2
422 //===--------------------------------------------------------------------===//
424 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
425 const MCSubtargetInfo &STI,
427 const MCOperand &MO1 = MI->getOperand(Op);
428 const MCOperand &MO2 = MI->getOperand(Op + 1);
429 const MCOperand &MO3 = MI->getOperand(Op + 2);
431 O << markup("<mem:") << "[";
432 printRegName(O, MO1.getReg());
435 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
436 O << ", " << markup("<imm:") << "#"
437 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
438 << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
440 O << "]" << markup(">");
445 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
446 printRegName(O, MO2.getReg());
448 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
449 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
450 O << "]" << markup(">");
453 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
454 const MCSubtargetInfo &STI,
456 const MCOperand &MO1 = MI->getOperand(Op);
457 const MCOperand &MO2 = MI->getOperand(Op + 1);
458 O << markup("<mem:") << "[";
459 printRegName(O, MO1.getReg());
461 printRegName(O, MO2.getReg());
462 O << "]" << markup(">");
465 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
466 const MCSubtargetInfo &STI,
468 const MCOperand &MO1 = MI->getOperand(Op);
469 const MCOperand &MO2 = MI->getOperand(Op + 1);
470 O << markup("<mem:") << "[";
471 printRegName(O, MO1.getReg());
473 printRegName(O, MO2.getReg());
474 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
477 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
478 const MCSubtargetInfo &STI,
480 const MCOperand &MO1 = MI->getOperand(Op);
482 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
483 printOperand(MI, Op, STI, O);
488 const MCOperand &MO3 = MI->getOperand(Op + 2);
489 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
490 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
493 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
496 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
498 const MCSubtargetInfo &STI,
500 const MCOperand &MO1 = MI->getOperand(OpNum);
501 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
504 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
505 O << markup("<imm:") << '#'
506 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
511 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
512 printRegName(O, MO1.getReg());
514 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
515 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
518 //===--------------------------------------------------------------------===//
519 // Addressing Mode #3
520 //===--------------------------------------------------------------------===//
522 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
524 bool AlwaysPrintImm0) {
525 const MCOperand &MO1 = MI->getOperand(Op);
526 const MCOperand &MO2 = MI->getOperand(Op + 1);
527 const MCOperand &MO3 = MI->getOperand(Op + 2);
529 O << markup("<mem:") << '[';
530 printRegName(O, MO1.getReg());
533 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
534 printRegName(O, MO2.getReg());
535 O << ']' << markup(">");
539 // If the op is sub we have to print the immediate even if it is 0
540 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
541 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
543 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
544 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
547 O << ']' << markup(">");
550 template <bool AlwaysPrintImm0>
551 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
552 const MCSubtargetInfo &STI,
554 const MCOperand &MO1 = MI->getOperand(Op);
555 if (!MO1.isReg()) { // For label symbolic references.
556 printOperand(MI, Op, STI, O);
560 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
561 ARMII::IndexModePost &&
562 "unexpected idxmode");
563 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
566 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
568 const MCSubtargetInfo &STI,
570 const MCOperand &MO1 = MI->getOperand(OpNum);
571 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
574 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
575 printRegName(O, MO1.getReg());
579 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
580 O << markup("<imm:") << '#'
581 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
585 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
586 const MCSubtargetInfo &STI,
588 const MCOperand &MO = MI->getOperand(OpNum);
589 unsigned Imm = MO.getImm();
590 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
594 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
595 const MCSubtargetInfo &STI,
597 const MCOperand &MO1 = MI->getOperand(OpNum);
598 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
600 O << (MO2.getImm() ? "" : "-");
601 printRegName(O, MO1.getReg());
604 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
605 const MCSubtargetInfo &STI,
607 const MCOperand &MO = MI->getOperand(OpNum);
608 unsigned Imm = MO.getImm();
609 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
613 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
614 const MCSubtargetInfo &STI,
616 ARM_AM::AMSubMode Mode =
617 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
618 O << ARM_AM::getAMSubModeStr(Mode);
621 template <bool AlwaysPrintImm0>
622 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
623 const MCSubtargetInfo &STI,
625 const MCOperand &MO1 = MI->getOperand(OpNum);
626 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
628 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
629 printOperand(MI, OpNum, STI, O);
633 O << markup("<mem:") << "[";
634 printRegName(O, MO1.getReg());
636 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
637 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
638 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
639 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
640 << ImmOffs * 4 << markup(">");
642 O << "]" << markup(">");
645 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
646 const MCSubtargetInfo &STI,
648 const MCOperand &MO1 = MI->getOperand(OpNum);
649 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
651 O << markup("<mem:") << "[";
652 printRegName(O, MO1.getReg());
654 O << ":" << (MO2.getImm() << 3);
656 O << "]" << markup(">");
659 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
660 const MCSubtargetInfo &STI,
662 const MCOperand &MO1 = MI->getOperand(OpNum);
663 O << markup("<mem:") << "[";
664 printRegName(O, MO1.getReg());
665 O << "]" << markup(">");
668 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
670 const MCSubtargetInfo &STI,
672 const MCOperand &MO = MI->getOperand(OpNum);
673 if (MO.getReg() == 0)
677 printRegName(O, MO.getReg());
681 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
683 const MCSubtargetInfo &STI,
685 const MCOperand &MO = MI->getOperand(OpNum);
686 uint32_t v = ~MO.getImm();
687 int32_t lsb = countTrailingZeros(v);
688 int32_t width = (32 - countLeadingZeros(v)) - lsb;
689 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
690 O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
691 << '#' << width << markup(">");
694 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
695 const MCSubtargetInfo &STI,
697 unsigned val = MI->getOperand(OpNum).getImm();
698 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
701 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
702 const MCSubtargetInfo &STI,
704 unsigned val = MI->getOperand(OpNum).getImm();
705 O << ARM_ISB::InstSyncBOptToString(val);
708 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
709 const MCSubtargetInfo &STI,
711 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
712 bool isASR = (ShiftOp & (1 << 5)) != 0;
713 unsigned Amt = ShiftOp & 0x1f;
715 O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
718 O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
722 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
723 const MCSubtargetInfo &STI,
725 unsigned Imm = MI->getOperand(OpNum).getImm();
728 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
729 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
732 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
733 const MCSubtargetInfo &STI,
735 unsigned Imm = MI->getOperand(OpNum).getImm();
736 // A shift amount of 32 is encoded as 0.
739 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
740 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
743 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
744 const MCSubtargetInfo &STI,
747 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
750 printRegName(O, MI->getOperand(i).getReg());
755 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
756 const MCSubtargetInfo &STI,
758 unsigned Reg = MI->getOperand(OpNum).getReg();
759 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
761 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
764 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
765 const MCSubtargetInfo &STI,
767 const MCOperand &Op = MI->getOperand(OpNum);
774 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
775 const MCSubtargetInfo &STI, raw_ostream &O) {
776 const MCOperand &Op = MI->getOperand(OpNum);
777 O << ARM_PROC::IModToString(Op.getImm());
780 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
781 const MCSubtargetInfo &STI, raw_ostream &O) {
782 const MCOperand &Op = MI->getOperand(OpNum);
783 unsigned IFlags = Op.getImm();
784 for (int i = 2; i >= 0; --i)
785 if (IFlags & (1 << i))
786 O << ARM_PROC::IFlagsToString(1 << i);
792 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
793 const MCSubtargetInfo &STI,
795 const MCOperand &Op = MI->getOperand(OpNum);
796 unsigned SpecRegRBit = Op.getImm() >> 4;
797 unsigned Mask = Op.getImm() & 0xf;
798 const FeatureBitset &FeatureBits = STI.getFeatureBits();
800 if (FeatureBits[ARM::FeatureMClass]) {
801 unsigned SYSm = Op.getImm();
802 unsigned Opcode = MI->getOpcode();
804 // For writes, handle extended mask bits if the DSP extension is present.
805 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
834 // Handle the basic 8-bit mask.
837 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
838 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
839 // alias for MSR APSR_nzcvq.
858 llvm_unreachable("Unexpected mask value!");
904 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
905 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
906 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
910 llvm_unreachable("Unexpected mask value!");
941 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
942 const MCSubtargetInfo &STI,
944 uint32_t Banked = MI->getOperand(OpNum).getImm();
945 uint32_t R = (Banked & 0x20) >> 5;
946 uint32_t SysM = Banked & 0x1f;
948 // Nothing much we can do about this, the encodings are specified in B9.2.3 of
949 // the ARM ARM v7C, and are all over the shop.
976 llvm_unreachable("Invalid banked SPSR register");
980 assert(!R && "should have dealt with SPSR regs");
981 const char *RegNames[] = {
982 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
983 "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
984 "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
985 "sp_abt", "lr_und", "sp_und", "", "", "", "",
986 "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
987 const char *Name = RegNames[SysM];
988 assert(Name[0] && "invalid banked register operand");
993 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
994 const MCSubtargetInfo &STI,
996 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
997 // Handle the undefined 15 CC value here for printing so we don't abort().
998 if ((unsigned)CC == 15)
1000 else if (CC != ARMCC::AL)
1001 O << ARMCondCodeToString(CC);
1004 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1006 const MCSubtargetInfo &STI,
1008 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1009 O << ARMCondCodeToString(CC);
1012 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1013 const MCSubtargetInfo &STI,
1015 if (MI->getOperand(OpNum).getReg()) {
1016 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1017 "Expect ARM CPSR register!");
1022 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1023 const MCSubtargetInfo &STI,
1025 O << MI->getOperand(OpNum).getImm();
1028 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1029 const MCSubtargetInfo &STI,
1031 O << "p" << MI->getOperand(OpNum).getImm();
1034 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1035 const MCSubtargetInfo &STI,
1037 O << "c" << MI->getOperand(OpNum).getImm();
1040 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1041 const MCSubtargetInfo &STI,
1043 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1046 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1047 const MCSubtargetInfo &STI, raw_ostream &O) {
1048 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1051 template <unsigned scale>
1052 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1053 const MCSubtargetInfo &STI,
1055 const MCOperand &MO = MI->getOperand(OpNum);
1062 int32_t OffImm = (int32_t)MO.getImm() << scale;
1064 O << markup("<imm:");
1065 if (OffImm == INT32_MIN)
1067 else if (OffImm < 0)
1068 O << "#-" << -OffImm;
1074 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1075 const MCSubtargetInfo &STI,
1077 O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1081 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1082 const MCSubtargetInfo &STI,
1084 unsigned Imm = MI->getOperand(OpNum).getImm();
1085 O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1089 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1090 const MCSubtargetInfo &STI,
1092 // (3 - the number of trailing zeros) is the number of then / else.
1093 unsigned Mask = MI->getOperand(OpNum).getImm();
1094 unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1095 unsigned CondBit0 = Firstcond & 1;
1096 unsigned NumTZ = countTrailingZeros(Mask);
1097 assert(NumTZ <= 3 && "Invalid IT mask!");
1098 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1099 bool T = ((Mask >> Pos) & 1) == CondBit0;
1107 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1108 const MCSubtargetInfo &STI,
1110 const MCOperand &MO1 = MI->getOperand(Op);
1111 const MCOperand &MO2 = MI->getOperand(Op + 1);
1113 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1114 printOperand(MI, Op, STI, O);
1118 O << markup("<mem:") << "[";
1119 printRegName(O, MO1.getReg());
1120 if (unsigned RegNum = MO2.getReg()) {
1122 printRegName(O, RegNum);
1124 O << "]" << markup(">");
1127 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1129 const MCSubtargetInfo &STI,
1132 const MCOperand &MO1 = MI->getOperand(Op);
1133 const MCOperand &MO2 = MI->getOperand(Op + 1);
1135 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1136 printOperand(MI, Op, STI, O);
1140 O << markup("<mem:") << "[";
1141 printRegName(O, MO1.getReg());
1142 if (unsigned ImmOffs = MO2.getImm()) {
1143 O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1146 O << "]" << markup(">");
1149 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1151 const MCSubtargetInfo &STI,
1153 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1156 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1158 const MCSubtargetInfo &STI,
1160 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1163 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1165 const MCSubtargetInfo &STI,
1167 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1170 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1171 const MCSubtargetInfo &STI,
1173 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1176 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1177 // register with shift forms.
1178 // REG 0 0 - e.g. R5
1179 // REG IMM, SH_OPC - e.g. R5, LSL #3
1180 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1181 const MCSubtargetInfo &STI,
1183 const MCOperand &MO1 = MI->getOperand(OpNum);
1184 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1186 unsigned Reg = MO1.getReg();
1187 printRegName(O, Reg);
1189 // Print the shift opc.
1190 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1191 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1192 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1195 template <bool AlwaysPrintImm0>
1196 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1197 const MCSubtargetInfo &STI,
1199 const MCOperand &MO1 = MI->getOperand(OpNum);
1200 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1202 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1203 printOperand(MI, OpNum, STI, O);
1207 O << markup("<mem:") << "[";
1208 printRegName(O, MO1.getReg());
1210 int32_t OffImm = (int32_t)MO2.getImm();
1211 bool isSub = OffImm < 0;
1212 // Special value for #-0. All others are normal.
1213 if (OffImm == INT32_MIN)
1216 O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1217 } else if (AlwaysPrintImm0 || OffImm > 0) {
1218 O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1220 O << "]" << markup(">");
1223 template <bool AlwaysPrintImm0>
1224 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1226 const MCSubtargetInfo &STI,
1228 const MCOperand &MO1 = MI->getOperand(OpNum);
1229 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1231 O << markup("<mem:") << "[";
1232 printRegName(O, MO1.getReg());
1234 int32_t OffImm = (int32_t)MO2.getImm();
1235 bool isSub = OffImm < 0;
1237 if (OffImm == INT32_MIN)
1240 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1241 } else if (AlwaysPrintImm0 || OffImm > 0) {
1242 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1244 O << "]" << markup(">");
1247 template <bool AlwaysPrintImm0>
1248 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1250 const MCSubtargetInfo &STI,
1252 const MCOperand &MO1 = MI->getOperand(OpNum);
1253 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1255 if (!MO1.isReg()) { // For label symbolic references.
1256 printOperand(MI, OpNum, STI, O);
1260 O << markup("<mem:") << "[";
1261 printRegName(O, MO1.getReg());
1263 int32_t OffImm = (int32_t)MO2.getImm();
1264 bool isSub = OffImm < 0;
1266 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1269 if (OffImm == INT32_MIN)
1272 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1273 } else if (AlwaysPrintImm0 || OffImm > 0) {
1274 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1276 O << "]" << markup(">");
1279 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1280 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1282 const MCOperand &MO1 = MI->getOperand(OpNum);
1283 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1285 O << markup("<mem:") << "[";
1286 printRegName(O, MO1.getReg());
1288 O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1291 O << "]" << markup(">");
1294 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1295 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1297 const MCOperand &MO1 = MI->getOperand(OpNum);
1298 int32_t OffImm = (int32_t)MO1.getImm();
1299 O << ", " << markup("<imm:");
1300 if (OffImm == INT32_MIN)
1302 else if (OffImm < 0)
1303 O << "#-" << -OffImm;
1309 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1310 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1312 const MCOperand &MO1 = MI->getOperand(OpNum);
1313 int32_t OffImm = (int32_t)MO1.getImm();
1315 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1317 O << ", " << markup("<imm:");
1318 if (OffImm == INT32_MIN)
1320 else if (OffImm < 0)
1321 O << "#-" << -OffImm;
1327 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1329 const MCSubtargetInfo &STI,
1331 const MCOperand &MO1 = MI->getOperand(OpNum);
1332 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1333 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1335 O << markup("<mem:") << "[";
1336 printRegName(O, MO1.getReg());
1338 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1340 printRegName(O, MO2.getReg());
1342 unsigned ShAmt = MO3.getImm();
1344 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1345 O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1347 O << "]" << markup(">");
1350 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1351 const MCSubtargetInfo &STI,
1353 const MCOperand &MO = MI->getOperand(OpNum);
1354 O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1358 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1359 const MCSubtargetInfo &STI,
1361 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1363 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1364 O << markup("<imm:") << "#0x";
1369 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1370 const MCSubtargetInfo &STI,
1372 unsigned Imm = MI->getOperand(OpNum).getImm();
1373 O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1376 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1377 const MCSubtargetInfo &STI,
1379 unsigned Imm = MI->getOperand(OpNum).getImm();
1382 assert(Imm <= 3 && "illegal ror immediate!");
1383 O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1386 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1387 const MCSubtargetInfo &STI,
1389 MCOperand Op = MI->getOperand(OpNum);
1391 // Support for fixups (MCFixup)
1393 return printOperand(MI, OpNum, STI, O);
1395 unsigned Bits = Op.getImm() & 0xFF;
1396 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1398 bool PrintUnsigned = false;
1399 switch (MI->getOpcode()) {
1401 // Movs to PC should be treated unsigned
1402 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1405 // Movs to special registers should be treated unsigned
1406 PrintUnsigned = true;
1410 int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1411 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1412 // #rot has the least possible value
1413 O << "#" << markup("<imm:");
1415 O << static_cast<uint32_t>(Rotated);
1422 // Explicit #bits, #rot implied
1423 O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1424 << Rot << markup(">");
1427 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1428 const MCSubtargetInfo &STI, raw_ostream &O) {
1429 O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1433 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1434 const MCSubtargetInfo &STI, raw_ostream &O) {
1435 O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1439 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1440 const MCSubtargetInfo &STI,
1442 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1445 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1446 const MCSubtargetInfo &STI,
1449 printRegName(O, MI->getOperand(OpNum).getReg());
1453 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1454 const MCSubtargetInfo &STI,
1456 unsigned Reg = MI->getOperand(OpNum).getReg();
1457 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1458 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1460 printRegName(O, Reg0);
1462 printRegName(O, Reg1);
1466 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1467 const MCSubtargetInfo &STI,
1469 unsigned Reg = MI->getOperand(OpNum).getReg();
1470 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1471 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1473 printRegName(O, Reg0);
1475 printRegName(O, Reg1);
1479 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1480 const MCSubtargetInfo &STI,
1482 // Normally, it's not safe to use register enum values directly with
1483 // addition to get the next register, but for VFP registers, the
1484 // sort order is guaranteed because they're all of the form D<n>.
1486 printRegName(O, MI->getOperand(OpNum).getReg());
1488 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1490 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1494 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1495 const MCSubtargetInfo &STI,
1497 // Normally, it's not safe to use register enum values directly with
1498 // addition to get the next register, but for VFP registers, the
1499 // sort order is guaranteed because they're all of the form D<n>.
1501 printRegName(O, MI->getOperand(OpNum).getReg());
1503 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1505 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1507 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1511 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1513 const MCSubtargetInfo &STI,
1516 printRegName(O, MI->getOperand(OpNum).getReg());
1520 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1522 const MCSubtargetInfo &STI,
1524 unsigned Reg = MI->getOperand(OpNum).getReg();
1525 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1526 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1528 printRegName(O, Reg0);
1530 printRegName(O, Reg1);
1534 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1536 const MCSubtargetInfo &STI,
1538 // Normally, it's not safe to use register enum values directly with
1539 // addition to get the next register, but for VFP registers, the
1540 // sort order is guaranteed because they're all of the form D<n>.
1542 printRegName(O, MI->getOperand(OpNum).getReg());
1544 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1546 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1550 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1552 const MCSubtargetInfo &STI,
1554 // Normally, it's not safe to use register enum values directly with
1555 // addition to get the next register, but for VFP registers, the
1556 // sort order is guaranteed because they're all of the form D<n>.
1558 printRegName(O, MI->getOperand(OpNum).getReg());
1560 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1562 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1564 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1568 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1569 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1571 unsigned Reg = MI->getOperand(OpNum).getReg();
1572 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1573 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1575 printRegName(O, Reg0);
1577 printRegName(O, Reg1);
1581 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1582 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1584 // Normally, it's not safe to use register enum values directly with
1585 // addition to get the next register, but for VFP registers, the
1586 // sort order is guaranteed because they're all of the form D<n>.
1588 printRegName(O, MI->getOperand(OpNum).getReg());
1590 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1592 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1596 void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1597 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1599 // Normally, it's not safe to use register enum values directly with
1600 // addition to get the next register, but for VFP registers, the
1601 // sort order is guaranteed because they're all of the form D<n>.
1603 printRegName(O, MI->getOperand(OpNum).getReg());
1605 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1607 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1609 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1613 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1615 const MCSubtargetInfo &STI,
1617 // Normally, it's not safe to use register enum values directly with
1618 // addition to get the next register, but for VFP registers, the
1619 // sort order is guaranteed because they're all of the form D<n>.
1621 printRegName(O, MI->getOperand(OpNum).getReg());
1623 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1625 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1629 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1630 const MCSubtargetInfo &STI,
1632 // Normally, it's not safe to use register enum values directly with
1633 // addition to get the next register, but for VFP registers, the
1634 // sort order is guaranteed because they're all of the form D<n>.
1636 printRegName(O, MI->getOperand(OpNum).getReg());
1638 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1640 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 6);