1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #include "ARMGenAsmWriter.inc"
27 static unsigned getDPRSuperRegForSPR(unsigned Reg) {
30 assert(0 && "Unexpected register enum");
31 case ARM::S0: case ARM::S1: return ARM::D0;
32 case ARM::S2: case ARM::S3: return ARM::D1;
33 case ARM::S4: case ARM::S5: return ARM::D2;
34 case ARM::S6: case ARM::S7: return ARM::D3;
35 case ARM::S8: case ARM::S9: return ARM::D4;
36 case ARM::S10: case ARM::S11: return ARM::D5;
37 case ARM::S12: case ARM::S13: return ARM::D6;
38 case ARM::S14: case ARM::S15: return ARM::D7;
39 case ARM::S16: case ARM::S17: return ARM::D8;
40 case ARM::S18: case ARM::S19: return ARM::D9;
41 case ARM::S20: case ARM::S21: return ARM::D10;
42 case ARM::S22: case ARM::S23: return ARM::D11;
43 case ARM::S24: case ARM::S25: return ARM::D12;
44 case ARM::S26: case ARM::S27: return ARM::D13;
45 case ARM::S28: case ARM::S29: return ARM::D14;
46 case ARM::S30: case ARM::S31: return ARM::D15;
50 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
51 // Check for MOVs and print canonical forms, instead.
52 if (MI->getOpcode() == ARM::MOVs) {
53 // FIXME: Thumb variants?
54 const MCOperand &Dst = MI->getOperand(0);
55 const MCOperand &MO1 = MI->getOperand(1);
56 const MCOperand &MO2 = MI->getOperand(2);
57 const MCOperand &MO3 = MI->getOperand(3);
59 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
60 printSBitModifierOperand(MI, 6, O);
61 printPredicateOperand(MI, 4, O);
63 O << '\t' << getRegisterName(Dst.getReg())
64 << ", " << getRegisterName(MO1.getReg());
66 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
72 O << getRegisterName(MO2.getReg());
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
75 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
81 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
82 MI->getOperand(0).getReg() == ARM::SP) {
83 const MCOperand &MO1 = MI->getOperand(2);
84 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
86 printPredicateOperand(MI, 3, O);
88 printRegisterList(MI, 5, O);
94 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
95 MI->getOperand(0).getReg() == ARM::SP) {
96 const MCOperand &MO1 = MI->getOperand(2);
97 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
99 printPredicateOperand(MI, 3, O);
101 printRegisterList(MI, 5, O);
107 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
108 MI->getOperand(0).getReg() == ARM::SP) {
109 const MCOperand &MO1 = MI->getOperand(2);
110 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
111 O << '\t' << "vpush";
112 printPredicateOperand(MI, 3, O);
114 printRegisterList(MI, 5, O);
120 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
121 MI->getOperand(0).getReg() == ARM::SP) {
122 const MCOperand &MO1 = MI->getOperand(2);
123 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
125 printPredicateOperand(MI, 3, O);
127 printRegisterList(MI, 5, O);
132 printInstruction(MI, O);
135 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
136 raw_ostream &O, const char *Modifier) {
137 const MCOperand &Op = MI->getOperand(OpNo);
139 unsigned Reg = Op.getReg();
140 if (Modifier && strcmp(Modifier, "lane") == 0) {
141 unsigned RegNum = getARMRegisterNumbering(Reg);
142 unsigned DReg = getDPRSuperRegForSPR(Reg);
143 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
145 O << getRegisterName(Reg);
147 } else if (Op.isImm()) {
148 assert((Modifier && !strcmp(Modifier, "call")) ||
149 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
150 O << '#' << Op.getImm();
152 if (Modifier && Modifier[0] != 0 && strcmp(Modifier, "call") != 0)
153 llvm_unreachable("Unsupported modifier");
154 assert(Op.isExpr() && "unknown operand kind in printOperand");
159 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
160 const MCAsmInfo *MAI) {
161 // Break it up into two parts that make up a shifter immediate.
162 V = ARM_AM::getSOImmVal(V);
163 assert(V != -1 && "Not a valid so_imm value!");
165 unsigned Imm = ARM_AM::getSOImmValImm(V);
166 unsigned Rot = ARM_AM::getSOImmValRot(V);
168 // Print low-level immediate formation info, per
169 // A5.1.3: "Data-processing operands - Immediate".
171 O << "#" << Imm << ", " << Rot;
172 // Pretty printed version.
174 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
181 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
182 /// immediate in bits 0-7.
183 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
185 const MCOperand &MO = MI->getOperand(OpNum);
186 assert(MO.isImm() && "Not a valid so_imm value!");
187 printSOImm(O, MO.getImm(), CommentStream, &MAI);
190 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
191 /// followed by an 'orr' to materialize.
192 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
194 // FIXME: REMOVE this method.
198 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
199 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
201 // REG REG 0,SH_OPC - e.g. R5, ROR R3
202 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
203 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
205 const MCOperand &MO1 = MI->getOperand(OpNum);
206 const MCOperand &MO2 = MI->getOperand(OpNum+1);
207 const MCOperand &MO3 = MI->getOperand(OpNum+2);
209 O << getRegisterName(MO1.getReg());
211 // Print the shift opc.
212 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
213 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
215 O << ' ' << getRegisterName(MO2.getReg());
216 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
217 } else if (ShOpc != ARM_AM::rrx) {
218 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
223 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
225 const MCOperand &MO1 = MI->getOperand(Op);
226 const MCOperand &MO2 = MI->getOperand(Op+1);
227 const MCOperand &MO3 = MI->getOperand(Op+2);
229 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
230 printOperand(MI, Op, O);
234 O << "[" << getRegisterName(MO1.getReg());
237 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
239 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
240 << ARM_AM::getAM2Offset(MO3.getImm());
246 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
247 << getRegisterName(MO2.getReg());
249 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
251 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
256 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
259 const MCOperand &MO1 = MI->getOperand(OpNum);
260 const MCOperand &MO2 = MI->getOperand(OpNum+1);
263 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
265 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
270 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
271 << getRegisterName(MO1.getReg());
273 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
275 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
279 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
281 const MCOperand &MO1 = MI->getOperand(OpNum);
282 const MCOperand &MO2 = MI->getOperand(OpNum+1);
283 const MCOperand &MO3 = MI->getOperand(OpNum+2);
285 O << '[' << getRegisterName(MO1.getReg());
288 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
289 << getRegisterName(MO2.getReg()) << ']';
293 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
295 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
300 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
303 const MCOperand &MO1 = MI->getOperand(OpNum);
304 const MCOperand &MO2 = MI->getOperand(OpNum+1);
307 O << (char)ARM_AM::getAM3Op(MO2.getImm())
308 << getRegisterName(MO1.getReg());
312 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
314 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
319 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
321 const char *Modifier) {
322 const MCOperand &MO2 = MI->getOperand(OpNum+1);
323 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
324 if (Modifier && strcmp(Modifier, "submode") == 0) {
325 O << ARM_AM::getAMSubModeStr(Mode);
326 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
327 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
328 if (Mode == ARM_AM::ia)
331 printOperand(MI, OpNum, O);
335 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
337 const char *Modifier) {
338 const MCOperand &MO1 = MI->getOperand(OpNum);
339 const MCOperand &MO2 = MI->getOperand(OpNum+1);
341 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
342 printOperand(MI, OpNum, O);
346 O << "[" << getRegisterName(MO1.getReg());
348 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
350 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
356 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
358 const MCOperand &MO1 = MI->getOperand(OpNum);
359 const MCOperand &MO2 = MI->getOperand(OpNum+1);
361 O << "[" << getRegisterName(MO1.getReg());
363 // FIXME: Both darwin as and GNU as violate ARM docs here.
364 O << ", :" << (MO2.getImm() << 3);
369 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
372 const MCOperand &MO = MI->getOperand(OpNum);
373 if (MO.getReg() == 0)
376 O << ", " << getRegisterName(MO.getReg());
379 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
381 const char *Modifier) {
382 // All instructions using addrmodepc are pseudos and should have been
383 // handled explicitly in printInstructionThroughMCStreamer(). If one got
384 // here, it wasn't, so something's wrong.
385 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
388 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
391 const MCOperand &MO = MI->getOperand(OpNum);
392 uint32_t v = ~MO.getImm();
393 int32_t lsb = CountTrailingZeros_32(v);
394 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
395 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
396 O << '#' << lsb << ", #" << width;
399 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
401 unsigned val = MI->getOperand(OpNum).getImm();
402 O << ARM_MB::MemBOptToString(val);
405 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
407 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
408 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
410 case ARM_AM::no_shift:
419 assert(0 && "unexpected shift opcode for shift immediate operand");
421 O << ARM_AM::getSORegOffset(ShiftOp);
424 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
427 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
428 if (i != OpNum) O << ", ";
429 O << getRegisterName(MI->getOperand(i).getReg());
434 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
436 const MCOperand &Op = MI->getOperand(OpNum);
437 unsigned option = Op.getImm();
438 unsigned mode = option & 31;
439 bool changemode = option >> 5 & 1;
440 unsigned AIF = option >> 6 & 7;
441 unsigned imod = option >> 9 & 3;
448 if (AIF & 4) O << 'a';
449 if (AIF & 2) O << 'i';
450 if (AIF & 1) O << 'f';
451 if (AIF > 0 && changemode) O << ", ";
457 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
459 const MCOperand &Op = MI->getOperand(OpNum);
460 unsigned Mask = Op.getImm();
463 if (Mask & 8) O << 'f';
464 if (Mask & 4) O << 's';
465 if (Mask & 2) O << 'x';
466 if (Mask & 1) O << 'c';
470 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
472 const MCOperand &Op = MI->getOperand(OpNum);
475 O << '-' << (-Op.getImm() - 1);
480 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
482 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
484 O << ARMCondCodeToString(CC);
487 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
490 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
491 O << ARMCondCodeToString(CC);
494 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
496 if (MI->getOperand(OpNum).getReg()) {
497 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
498 "Expect ARM CPSR register!");
505 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
507 const char *Modifier) {
508 // FIXME: remove this.
512 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
514 O << MI->getOperand(OpNum).getImm();
518 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
520 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
523 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
525 O << "#" << MI->getOperand(OpNum).getImm() * 4;
528 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
530 // (3 - the number of trailing zeros) is the number of then / else.
531 unsigned Mask = MI->getOperand(OpNum).getImm();
532 unsigned CondBit0 = Mask >> 4 & 1;
533 unsigned NumTZ = CountTrailingZeros_32(Mask);
534 assert(NumTZ <= 3 && "Invalid IT mask!");
535 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
536 bool T = ((Mask >> Pos) & 1) == CondBit0;
544 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
546 const MCOperand &MO1 = MI->getOperand(Op);
547 const MCOperand &MO2 = MI->getOperand(Op+1);
548 O << "[" << getRegisterName(MO1.getReg());
549 O << ", " << getRegisterName(MO2.getReg()) << "]";
552 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
555 const MCOperand &MO1 = MI->getOperand(Op);
556 const MCOperand &MO2 = MI->getOperand(Op+1);
557 const MCOperand &MO3 = MI->getOperand(Op+2);
559 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
560 printOperand(MI, Op, O);
564 O << "[" << getRegisterName(MO1.getReg());
566 O << ", " << getRegisterName(MO3.getReg());
567 else if (unsigned ImmOffs = MO2.getImm())
568 O << ", #" << ImmOffs * Scale;
572 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
574 printThumbAddrModeRI5Operand(MI, Op, O, 1);
577 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
579 printThumbAddrModeRI5Operand(MI, Op, O, 2);
582 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
584 printThumbAddrModeRI5Operand(MI, Op, O, 4);
587 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
589 const MCOperand &MO1 = MI->getOperand(Op);
590 const MCOperand &MO2 = MI->getOperand(Op+1);
591 O << "[" << getRegisterName(MO1.getReg());
592 if (unsigned ImmOffs = MO2.getImm())
593 O << ", #" << ImmOffs*4;
597 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
599 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
600 if (MI->getOpcode() == ARM::t2TBH)
605 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
606 // register with shift forms.
608 // REG IMM, SH_OPC - e.g. R5, LSL #3
609 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
611 const MCOperand &MO1 = MI->getOperand(OpNum);
612 const MCOperand &MO2 = MI->getOperand(OpNum+1);
614 unsigned Reg = MO1.getReg();
615 O << getRegisterName(Reg);
617 // Print the shift opc.
618 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
619 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
620 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
621 if (ShOpc != ARM_AM::rrx)
622 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
625 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
628 const MCOperand &MO1 = MI->getOperand(OpNum);
629 const MCOperand &MO2 = MI->getOperand(OpNum+1);
631 O << "[" << getRegisterName(MO1.getReg());
633 unsigned OffImm = MO2.getImm();
634 if (OffImm) // Don't print +0.
635 O << ", #" << OffImm;
639 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
642 const MCOperand &MO1 = MI->getOperand(OpNum);
643 const MCOperand &MO2 = MI->getOperand(OpNum+1);
645 O << "[" << getRegisterName(MO1.getReg());
647 int32_t OffImm = (int32_t)MO2.getImm();
650 O << ", #-" << -OffImm;
652 O << ", #" << OffImm;
656 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
659 const MCOperand &MO1 = MI->getOperand(OpNum);
660 const MCOperand &MO2 = MI->getOperand(OpNum+1);
662 O << "[" << getRegisterName(MO1.getReg());
664 int32_t OffImm = (int32_t)MO2.getImm() / 4;
667 O << ", #-" << -OffImm * 4;
669 O << ", #" << OffImm * 4;
673 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
676 const MCOperand &MO1 = MI->getOperand(OpNum);
677 int32_t OffImm = (int32_t)MO1.getImm();
680 O << "#-" << -OffImm;
685 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
688 const MCOperand &MO1 = MI->getOperand(OpNum);
689 int32_t OffImm = (int32_t)MO1.getImm() / 4;
692 O << "#-" << -OffImm * 4;
694 O << "#" << OffImm * 4;
697 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
700 const MCOperand &MO1 = MI->getOperand(OpNum);
701 const MCOperand &MO2 = MI->getOperand(OpNum+1);
702 const MCOperand &MO3 = MI->getOperand(OpNum+2);
704 O << "[" << getRegisterName(MO1.getReg());
706 assert(MO2.getReg() && "Invalid so_reg load / store address!");
707 O << ", " << getRegisterName(MO2.getReg());
709 unsigned ShAmt = MO3.getImm();
711 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
712 O << ", lsl #" << ShAmt;
717 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
719 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
722 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
724 O << '#' << MI->getOperand(OpNum).getFPImm();
727 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
729 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
731 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
732 O << "#0x" << utohexstr(Val);