1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
32 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
33 OS << getRegisterName(RegNo);
36 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
37 unsigned Opcode = MI->getOpcode();
39 // Check for MOVs and print canonical forms, instead.
40 if (Opcode == ARM::MOVsr) {
41 // FIXME: Thumb variants?
42 const MCOperand &Dst = MI->getOperand(0);
43 const MCOperand &MO1 = MI->getOperand(1);
44 const MCOperand &MO2 = MI->getOperand(2);
45 const MCOperand &MO3 = MI->getOperand(3);
47 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
48 printSBitModifierOperand(MI, 6, O);
49 printPredicateOperand(MI, 4, O);
51 O << '\t' << getRegisterName(Dst.getReg())
52 << ", " << getRegisterName(MO1.getReg());
54 O << ", " << getRegisterName(MO2.getReg());
55 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
59 if (Opcode == ARM::MOVsi) {
60 // FIXME: Thumb variants?
61 const MCOperand &Dst = MI->getOperand(0);
62 const MCOperand &MO1 = MI->getOperand(1);
63 const MCOperand &MO2 = MI->getOperand(2);
65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
66 printSBitModifierOperand(MI, 5, O);
67 printPredicateOperand(MI, 3, O);
69 O << '\t' << getRegisterName(Dst.getReg())
70 << ", " << getRegisterName(MO1.getReg());
72 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
75 O << ", #" << ARM_AM::getSORegOffset(MO2.getImm());
81 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
82 MI->getOperand(0).getReg() == ARM::SP) {
84 printPredicateOperand(MI, 2, O);
85 if (Opcode == ARM::t2STMDB_UPD)
88 printRegisterList(MI, 4, O);
93 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
94 MI->getOperand(0).getReg() == ARM::SP) {
96 printPredicateOperand(MI, 2, O);
97 if (Opcode == ARM::t2LDMIA_UPD)
100 printRegisterList(MI, 4, O);
105 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
106 MI->getOperand(0).getReg() == ARM::SP) {
107 O << '\t' << "vpush";
108 printPredicateOperand(MI, 2, O);
110 printRegisterList(MI, 4, O);
115 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
116 MI->getOperand(0).getReg() == ARM::SP) {
118 printPredicateOperand(MI, 2, O);
120 printRegisterList(MI, 4, O);
124 if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
125 bool Writeback = true;
126 unsigned BaseReg = MI->getOperand(0).getReg();
127 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
128 if (MI->getOperand(i).getReg() == BaseReg)
132 if (Opcode == ARM::tLDMIA)
134 else if (Opcode == ARM::tSTMIA)
137 llvm_unreachable("Unknown opcode!");
139 printPredicateOperand(MI, 1, O);
140 O << '\t' << getRegisterName(BaseReg);
141 if (Writeback) O << "!";
143 printRegisterList(MI, 3, O);
147 printInstruction(MI, O);
150 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
152 const MCOperand &Op = MI->getOperand(OpNo);
154 unsigned Reg = Op.getReg();
155 O << getRegisterName(Reg);
156 } else if (Op.isImm()) {
157 O << '#' << Op.getImm();
159 assert(Op.isExpr() && "unknown operand kind in printOperand");
164 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
165 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
167 // REG REG 0,SH_OPC - e.g. R5, ROR R3
168 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
169 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
171 const MCOperand &MO1 = MI->getOperand(OpNum);
172 const MCOperand &MO2 = MI->getOperand(OpNum+1);
173 const MCOperand &MO3 = MI->getOperand(OpNum+2);
175 O << getRegisterName(MO1.getReg());
177 // Print the shift opc.
178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
179 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
180 if (ShOpc == ARM_AM::rrx)
183 O << ' ' << getRegisterName(MO2.getReg());
184 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
187 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
189 const MCOperand &MO1 = MI->getOperand(OpNum);
190 const MCOperand &MO2 = MI->getOperand(OpNum+1);
192 O << getRegisterName(MO1.getReg());
194 // Print the shift opc.
195 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
196 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
197 if (ShOpc == ARM_AM::rrx)
199 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
203 //===--------------------------------------------------------------------===//
204 // Addressing Mode #2
205 //===--------------------------------------------------------------------===//
207 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
209 const MCOperand &MO1 = MI->getOperand(Op);
210 const MCOperand &MO2 = MI->getOperand(Op+1);
211 const MCOperand &MO3 = MI->getOperand(Op+2);
213 O << "[" << getRegisterName(MO1.getReg());
216 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
218 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
219 << ARM_AM::getAM2Offset(MO3.getImm());
225 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
226 << getRegisterName(MO2.getReg());
228 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
230 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
235 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
237 const MCOperand &MO1 = MI->getOperand(Op);
238 const MCOperand &MO2 = MI->getOperand(Op+1);
239 const MCOperand &MO3 = MI->getOperand(Op+2);
241 O << "[" << getRegisterName(MO1.getReg()) << "], ";
244 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
246 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
251 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
252 << getRegisterName(MO2.getReg());
254 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
256 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
260 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
262 const MCOperand &MO1 = MI->getOperand(Op);
264 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
265 printOperand(MI, Op, O);
269 const MCOperand &MO3 = MI->getOperand(Op+2);
270 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
272 if (IdxMode == ARMII::IndexModePost) {
273 printAM2PostIndexOp(MI, Op, O);
276 printAM2PreOrOffsetIndexOp(MI, Op, O);
279 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
282 const MCOperand &MO1 = MI->getOperand(OpNum);
283 const MCOperand &MO2 = MI->getOperand(OpNum+1);
286 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
288 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
293 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
294 << getRegisterName(MO1.getReg());
296 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
298 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
302 //===--------------------------------------------------------------------===//
303 // Addressing Mode #3
304 //===--------------------------------------------------------------------===//
306 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
308 const MCOperand &MO1 = MI->getOperand(Op);
309 const MCOperand &MO2 = MI->getOperand(Op+1);
310 const MCOperand &MO3 = MI->getOperand(Op+2);
312 O << "[" << getRegisterName(MO1.getReg()) << "], ";
315 O << (char)ARM_AM::getAM3Op(MO3.getImm())
316 << getRegisterName(MO2.getReg());
320 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
322 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
326 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
328 const MCOperand &MO1 = MI->getOperand(Op);
329 const MCOperand &MO2 = MI->getOperand(Op+1);
330 const MCOperand &MO3 = MI->getOperand(Op+2);
332 O << '[' << getRegisterName(MO1.getReg());
335 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
336 << getRegisterName(MO2.getReg()) << ']';
340 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
342 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
347 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
349 const MCOperand &MO3 = MI->getOperand(Op+2);
350 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
352 if (IdxMode == ARMII::IndexModePost) {
353 printAM3PostIndexOp(MI, Op, O);
356 printAM3PreOrOffsetIndexOp(MI, Op, O);
359 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
362 const MCOperand &MO1 = MI->getOperand(OpNum);
363 const MCOperand &MO2 = MI->getOperand(OpNum+1);
366 O << (char)ARM_AM::getAM3Op(MO2.getImm())
367 << getRegisterName(MO1.getReg());
371 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
373 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
377 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
379 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
381 O << ARM_AM::getAMSubModeStr(Mode);
384 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
386 const MCOperand &MO1 = MI->getOperand(OpNum);
387 const MCOperand &MO2 = MI->getOperand(OpNum+1);
389 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
390 printOperand(MI, OpNum, O);
394 O << "[" << getRegisterName(MO1.getReg());
396 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
398 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
404 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
406 const MCOperand &MO1 = MI->getOperand(OpNum);
407 const MCOperand &MO2 = MI->getOperand(OpNum+1);
409 O << "[" << getRegisterName(MO1.getReg());
411 // FIXME: Both darwin as and GNU as violate ARM docs here.
412 O << ", :" << (MO2.getImm() << 3);
417 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
419 const MCOperand &MO1 = MI->getOperand(OpNum);
420 O << "[" << getRegisterName(MO1.getReg()) << "]";
423 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
426 const MCOperand &MO = MI->getOperand(OpNum);
427 if (MO.getReg() == 0)
430 O << ", " << getRegisterName(MO.getReg());
433 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
436 const MCOperand &MO = MI->getOperand(OpNum);
437 uint32_t v = ~MO.getImm();
438 int32_t lsb = CountTrailingZeros_32(v);
439 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
440 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
441 O << '#' << lsb << ", #" << width;
444 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
446 unsigned val = MI->getOperand(OpNum).getImm();
447 O << ARM_MB::MemBOptToString(val);
450 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
452 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
453 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
455 case ARM_AM::no_shift:
464 assert(0 && "unexpected shift opcode for shift immediate operand");
466 O << ARM_AM::getSORegOffset(ShiftOp);
469 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
471 unsigned Imm = MI->getOperand(OpNum).getImm();
474 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
475 O << ", lsl #" << Imm;
478 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
480 unsigned Imm = MI->getOperand(OpNum).getImm();
481 // A shift amount of 32 is encoded as 0.
484 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
485 O << ", asr #" << Imm;
488 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
491 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
492 if (i != OpNum) O << ", ";
493 O << getRegisterName(MI->getOperand(i).getReg());
498 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
500 const MCOperand &Op = MI->getOperand(OpNum);
507 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
509 const MCOperand &Op = MI->getOperand(OpNum);
510 O << ARM_PROC::IModToString(Op.getImm());
513 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
515 const MCOperand &Op = MI->getOperand(OpNum);
516 unsigned IFlags = Op.getImm();
517 for (int i=2; i >= 0; --i)
518 if (IFlags & (1 << i))
519 O << ARM_PROC::IFlagsToString(1 << i);
522 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
524 const MCOperand &Op = MI->getOperand(OpNum);
525 unsigned SpecRegRBit = Op.getImm() >> 4;
526 unsigned Mask = Op.getImm() & 0xf;
528 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
529 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
530 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
534 case 4: O << "g"; return;
535 case 8: O << "nzcvq"; return;
536 case 12: O << "nzcvqg"; return;
538 llvm_unreachable("Unexpected mask value!");
548 if (Mask & 8) O << 'f';
549 if (Mask & 4) O << 's';
550 if (Mask & 2) O << 'x';
551 if (Mask & 1) O << 'c';
555 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
557 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
559 O << ARMCondCodeToString(CC);
562 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
565 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
566 O << ARMCondCodeToString(CC);
569 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
571 if (MI->getOperand(OpNum).getReg()) {
572 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
573 "Expect ARM CPSR register!");
578 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
580 O << MI->getOperand(OpNum).getImm();
583 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
585 O << "p" << MI->getOperand(OpNum).getImm();
588 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
590 O << "c" << MI->getOperand(OpNum).getImm();
593 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
595 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
598 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
600 O << "#" << MI->getOperand(OpNum).getImm() * 4;
603 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
605 // (3 - the number of trailing zeros) is the number of then / else.
606 unsigned Mask = MI->getOperand(OpNum).getImm();
607 unsigned CondBit0 = Mask >> 4 & 1;
608 unsigned NumTZ = CountTrailingZeros_32(Mask);
609 assert(NumTZ <= 3 && "Invalid IT mask!");
610 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
611 bool T = ((Mask >> Pos) & 1) == CondBit0;
619 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
621 const MCOperand &MO1 = MI->getOperand(Op);
622 const MCOperand &MO2 = MI->getOperand(Op + 1);
624 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
625 printOperand(MI, Op, O);
629 O << "[" << getRegisterName(MO1.getReg());
630 if (unsigned RegNum = MO2.getReg())
631 O << ", " << getRegisterName(RegNum);
635 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
639 const MCOperand &MO1 = MI->getOperand(Op);
640 const MCOperand &MO2 = MI->getOperand(Op + 1);
642 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
643 printOperand(MI, Op, O);
647 O << "[" << getRegisterName(MO1.getReg());
648 if (unsigned ImmOffs = MO2.getImm())
649 O << ", #" << ImmOffs * Scale;
653 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
656 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
659 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
662 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
665 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
668 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
671 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
673 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
676 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
677 // register with shift forms.
679 // REG IMM, SH_OPC - e.g. R5, LSL #3
680 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
682 const MCOperand &MO1 = MI->getOperand(OpNum);
683 const MCOperand &MO2 = MI->getOperand(OpNum+1);
685 unsigned Reg = MO1.getReg();
686 O << getRegisterName(Reg);
688 // Print the shift opc.
689 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
690 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
691 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
692 if (ShOpc != ARM_AM::rrx)
693 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
696 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
698 const MCOperand &MO1 = MI->getOperand(OpNum);
699 const MCOperand &MO2 = MI->getOperand(OpNum+1);
701 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
702 printOperand(MI, OpNum, O);
706 O << "[" << getRegisterName(MO1.getReg());
708 int32_t OffImm = (int32_t)MO2.getImm();
709 bool isSub = OffImm < 0;
710 // Special value for #-0. All others are normal.
711 if (OffImm == INT32_MIN)
714 O << ", #-" << -OffImm;
716 O << ", #" << OffImm;
720 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
723 const MCOperand &MO1 = MI->getOperand(OpNum);
724 const MCOperand &MO2 = MI->getOperand(OpNum+1);
726 O << "[" << getRegisterName(MO1.getReg());
728 int32_t OffImm = (int32_t)MO2.getImm();
731 O << ", #-" << -OffImm;
733 O << ", #" << OffImm;
737 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
740 const MCOperand &MO1 = MI->getOperand(OpNum);
741 const MCOperand &MO2 = MI->getOperand(OpNum+1);
743 O << "[" << getRegisterName(MO1.getReg());
745 int32_t OffImm = (int32_t)MO2.getImm() / 4;
748 O << ", #-" << -OffImm * 4;
750 O << ", #" << OffImm * 4;
754 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
757 const MCOperand &MO1 = MI->getOperand(OpNum);
758 int32_t OffImm = (int32_t)MO1.getImm();
761 O << "#-" << -OffImm;
766 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
769 const MCOperand &MO1 = MI->getOperand(OpNum);
770 int32_t OffImm = (int32_t)MO1.getImm() / 4;
773 O << "#-" << -OffImm * 4;
775 O << "#" << OffImm * 4;
778 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
781 const MCOperand &MO1 = MI->getOperand(OpNum);
782 const MCOperand &MO2 = MI->getOperand(OpNum+1);
783 const MCOperand &MO3 = MI->getOperand(OpNum+2);
785 O << "[" << getRegisterName(MO1.getReg());
787 assert(MO2.getReg() && "Invalid so_reg load / store address!");
788 O << ", " << getRegisterName(MO2.getReg());
790 unsigned ShAmt = MO3.getImm();
792 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
793 O << ", lsl #" << ShAmt;
798 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
800 const MCOperand &MO = MI->getOperand(OpNum);
803 O << (float)MO.getFPImm();
810 FPUnion.I = MO.getImm();
815 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
817 const MCOperand &MO = MI->getOperand(OpNum);
822 // We expect the binary encoding of a floating point number here.
828 FPUnion.I = MO.getImm();
833 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
835 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
837 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
838 O << "#0x" << utohexstr(Val);