1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
32 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
33 OS << getRegisterName(RegNo);
36 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
37 unsigned Opcode = MI->getOpcode();
39 // Check for MOVs and print canonical forms, instead.
40 if (Opcode == ARM::MOVs) {
41 // FIXME: Thumb variants?
42 const MCOperand &Dst = MI->getOperand(0);
43 const MCOperand &MO1 = MI->getOperand(1);
44 const MCOperand &MO2 = MI->getOperand(2);
45 const MCOperand &MO3 = MI->getOperand(3);
47 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
48 printSBitModifierOperand(MI, 6, O);
49 printPredicateOperand(MI, 4, O);
51 O << '\t' << getRegisterName(Dst.getReg())
52 << ", " << getRegisterName(MO1.getReg());
54 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
60 O << getRegisterName(MO2.getReg());
61 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
63 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
69 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
70 MI->getOperand(0).getReg() == ARM::SP) {
72 printPredicateOperand(MI, 2, O);
73 if (Opcode == ARM::t2STMDB_UPD)
76 printRegisterList(MI, 4, O);
81 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
82 MI->getOperand(0).getReg() == ARM::SP) {
84 printPredicateOperand(MI, 2, O);
85 if (Opcode == ARM::t2LDMIA_UPD)
88 printRegisterList(MI, 4, O);
93 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
94 MI->getOperand(0).getReg() == ARM::SP) {
96 printPredicateOperand(MI, 2, O);
98 printRegisterList(MI, 4, O);
103 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
104 MI->getOperand(0).getReg() == ARM::SP) {
106 printPredicateOperand(MI, 2, O);
108 printRegisterList(MI, 4, O);
112 printInstruction(MI, O);
115 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
117 const MCOperand &Op = MI->getOperand(OpNo);
119 unsigned Reg = Op.getReg();
120 O << getRegisterName(Reg);
121 } else if (Op.isImm()) {
122 O << '#' << Op.getImm();
124 assert(Op.isExpr() && "unknown operand kind in printOperand");
129 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
130 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
132 // REG REG 0,SH_OPC - e.g. R5, ROR R3
133 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
134 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
136 const MCOperand &MO1 = MI->getOperand(OpNum);
137 const MCOperand &MO2 = MI->getOperand(OpNum+1);
138 const MCOperand &MO3 = MI->getOperand(OpNum+2);
140 O << getRegisterName(MO1.getReg());
142 // Print the shift opc.
143 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
144 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
146 O << ' ' << getRegisterName(MO2.getReg());
147 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
148 } else if (ShOpc != ARM_AM::rrx) {
149 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
153 //===--------------------------------------------------------------------===//
154 // Addressing Mode #2
155 //===--------------------------------------------------------------------===//
157 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
159 const MCOperand &MO1 = MI->getOperand(Op);
160 const MCOperand &MO2 = MI->getOperand(Op+1);
161 const MCOperand &MO3 = MI->getOperand(Op+2);
163 O << "[" << getRegisterName(MO1.getReg());
166 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
168 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
169 << ARM_AM::getAM2Offset(MO3.getImm());
175 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
176 << getRegisterName(MO2.getReg());
178 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
180 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
185 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
187 const MCOperand &MO1 = MI->getOperand(Op);
188 const MCOperand &MO2 = MI->getOperand(Op+1);
189 const MCOperand &MO3 = MI->getOperand(Op+2);
191 O << "[" << getRegisterName(MO1.getReg()) << "], ";
194 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
196 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
201 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
202 << getRegisterName(MO2.getReg());
204 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
206 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
210 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
212 const MCOperand &MO1 = MI->getOperand(Op);
214 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
215 printOperand(MI, Op, O);
219 const MCOperand &MO3 = MI->getOperand(Op+2);
220 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
222 if (IdxMode == ARMII::IndexModePost) {
223 printAM2PostIndexOp(MI, Op, O);
226 printAM2PreOrOffsetIndexOp(MI, Op, O);
229 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
232 const MCOperand &MO1 = MI->getOperand(OpNum);
233 const MCOperand &MO2 = MI->getOperand(OpNum+1);
236 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
238 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
243 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
244 << getRegisterName(MO1.getReg());
246 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
248 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
252 //===--------------------------------------------------------------------===//
253 // Addressing Mode #3
254 //===--------------------------------------------------------------------===//
256 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
258 const MCOperand &MO1 = MI->getOperand(Op);
259 const MCOperand &MO2 = MI->getOperand(Op+1);
260 const MCOperand &MO3 = MI->getOperand(Op+2);
262 O << "[" << getRegisterName(MO1.getReg()) << "], ";
265 O << (char)ARM_AM::getAM3Op(MO3.getImm())
266 << getRegisterName(MO2.getReg());
270 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
272 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
276 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
278 const MCOperand &MO1 = MI->getOperand(Op);
279 const MCOperand &MO2 = MI->getOperand(Op+1);
280 const MCOperand &MO3 = MI->getOperand(Op+2);
282 O << '[' << getRegisterName(MO1.getReg());
285 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
286 << getRegisterName(MO2.getReg()) << ']';
290 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
292 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
297 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
299 const MCOperand &MO3 = MI->getOperand(Op+2);
300 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
302 if (IdxMode == ARMII::IndexModePost) {
303 printAM3PostIndexOp(MI, Op, O);
306 printAM3PreOrOffsetIndexOp(MI, Op, O);
309 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
312 const MCOperand &MO1 = MI->getOperand(OpNum);
313 const MCOperand &MO2 = MI->getOperand(OpNum+1);
316 O << (char)ARM_AM::getAM3Op(MO2.getImm())
317 << getRegisterName(MO1.getReg());
321 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
323 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
327 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
329 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
331 O << ARM_AM::getAMSubModeStr(Mode);
334 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
336 const MCOperand &MO1 = MI->getOperand(OpNum);
337 const MCOperand &MO2 = MI->getOperand(OpNum+1);
339 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
340 printOperand(MI, OpNum, O);
344 O << "[" << getRegisterName(MO1.getReg());
346 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
348 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
354 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
356 const MCOperand &MO1 = MI->getOperand(OpNum);
357 const MCOperand &MO2 = MI->getOperand(OpNum+1);
359 O << "[" << getRegisterName(MO1.getReg());
361 // FIXME: Both darwin as and GNU as violate ARM docs here.
362 O << ", :" << (MO2.getImm() << 3);
367 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
369 const MCOperand &MO1 = MI->getOperand(OpNum);
370 O << "[" << getRegisterName(MO1.getReg()) << "]";
373 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
376 const MCOperand &MO = MI->getOperand(OpNum);
377 if (MO.getReg() == 0)
380 O << ", " << getRegisterName(MO.getReg());
383 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
386 const MCOperand &MO = MI->getOperand(OpNum);
387 uint32_t v = ~MO.getImm();
388 int32_t lsb = CountTrailingZeros_32(v);
389 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
390 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
391 O << '#' << lsb << ", #" << width;
394 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
396 unsigned val = MI->getOperand(OpNum).getImm();
397 O << ARM_MB::MemBOptToString(val);
400 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
402 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
403 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
405 case ARM_AM::no_shift:
414 assert(0 && "unexpected shift opcode for shift immediate operand");
416 O << ARM_AM::getSORegOffset(ShiftOp);
419 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
422 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
423 if (i != OpNum) O << ", ";
424 O << getRegisterName(MI->getOperand(i).getReg());
429 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
431 const MCOperand &Op = MI->getOperand(OpNum);
438 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
440 const MCOperand &Op = MI->getOperand(OpNum);
441 O << ARM_PROC::IModToString(Op.getImm());
444 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
446 const MCOperand &Op = MI->getOperand(OpNum);
447 unsigned IFlags = Op.getImm();
448 for (int i=2; i >= 0; --i)
449 if (IFlags & (1 << i))
450 O << ARM_PROC::IFlagsToString(1 << i);
453 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
455 const MCOperand &Op = MI->getOperand(OpNum);
456 unsigned SpecRegRBit = Op.getImm() >> 4;
457 unsigned Mask = Op.getImm() & 0xf;
466 if (Mask & 8) O << 'f';
467 if (Mask & 4) O << 's';
468 if (Mask & 2) O << 'x';
469 if (Mask & 1) O << 'c';
473 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
475 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
477 O << ARMCondCodeToString(CC);
480 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
483 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
484 O << ARMCondCodeToString(CC);
487 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
489 if (MI->getOperand(OpNum).getReg()) {
490 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
491 "Expect ARM CPSR register!");
496 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
498 O << MI->getOperand(OpNum).getImm();
501 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
503 O << "p" << MI->getOperand(OpNum).getImm();
506 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
508 O << "c" << MI->getOperand(OpNum).getImm();
511 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
513 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
516 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
518 O << "#" << MI->getOperand(OpNum).getImm() * 4;
521 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
523 // (3 - the number of trailing zeros) is the number of then / else.
524 unsigned Mask = MI->getOperand(OpNum).getImm();
525 unsigned CondBit0 = Mask >> 4 & 1;
526 unsigned NumTZ = CountTrailingZeros_32(Mask);
527 assert(NumTZ <= 3 && "Invalid IT mask!");
528 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
529 bool T = ((Mask >> Pos) & 1) == CondBit0;
537 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
539 const MCOperand &MO1 = MI->getOperand(Op);
540 const MCOperand &MO2 = MI->getOperand(Op + 1);
542 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
543 printOperand(MI, Op, O);
547 O << "[" << getRegisterName(MO1.getReg());
548 if (unsigned RegNum = MO2.getReg())
549 O << ", " << getRegisterName(RegNum);
553 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
557 const MCOperand &MO1 = MI->getOperand(Op);
558 const MCOperand &MO2 = MI->getOperand(Op + 1);
560 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
561 printOperand(MI, Op, O);
565 O << "[" << getRegisterName(MO1.getReg());
566 if (unsigned ImmOffs = MO2.getImm())
567 O << ", #" << ImmOffs * Scale;
571 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
574 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
577 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
580 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
583 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
586 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
589 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
591 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
594 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
595 // register with shift forms.
597 // REG IMM, SH_OPC - e.g. R5, LSL #3
598 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
600 const MCOperand &MO1 = MI->getOperand(OpNum);
601 const MCOperand &MO2 = MI->getOperand(OpNum+1);
603 unsigned Reg = MO1.getReg();
604 O << getRegisterName(Reg);
606 // Print the shift opc.
607 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
608 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
609 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
610 if (ShOpc != ARM_AM::rrx)
611 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
614 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
616 const MCOperand &MO1 = MI->getOperand(OpNum);
617 const MCOperand &MO2 = MI->getOperand(OpNum+1);
619 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
620 printOperand(MI, OpNum, O);
624 O << "[" << getRegisterName(MO1.getReg());
626 int32_t OffImm = (int32_t)MO2.getImm();
627 bool isSub = OffImm < 0;
628 // Special value for #-0. All others are normal.
629 if (OffImm == INT32_MIN)
632 O << ", #-" << -OffImm;
634 O << ", #" << OffImm;
638 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
641 const MCOperand &MO1 = MI->getOperand(OpNum);
642 const MCOperand &MO2 = MI->getOperand(OpNum+1);
644 O << "[" << getRegisterName(MO1.getReg());
646 int32_t OffImm = (int32_t)MO2.getImm();
649 O << ", #-" << -OffImm;
651 O << ", #" << OffImm;
655 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
658 const MCOperand &MO1 = MI->getOperand(OpNum);
659 const MCOperand &MO2 = MI->getOperand(OpNum+1);
661 O << "[" << getRegisterName(MO1.getReg());
663 int32_t OffImm = (int32_t)MO2.getImm() / 4;
666 O << ", #-" << -OffImm * 4;
668 O << ", #" << OffImm * 4;
672 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
675 const MCOperand &MO1 = MI->getOperand(OpNum);
676 int32_t OffImm = (int32_t)MO1.getImm();
679 O << "#-" << -OffImm;
684 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
687 const MCOperand &MO1 = MI->getOperand(OpNum);
688 int32_t OffImm = (int32_t)MO1.getImm() / 4;
691 O << "#-" << -OffImm * 4;
693 O << "#" << OffImm * 4;
696 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
699 const MCOperand &MO1 = MI->getOperand(OpNum);
700 const MCOperand &MO2 = MI->getOperand(OpNum+1);
701 const MCOperand &MO3 = MI->getOperand(OpNum+2);
703 O << "[" << getRegisterName(MO1.getReg());
705 assert(MO2.getReg() && "Invalid so_reg load / store address!");
706 O << ", " << getRegisterName(MO2.getReg());
708 unsigned ShAmt = MO3.getImm();
710 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
711 O << ", lsl #" << ShAmt;
716 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
718 const MCOperand &MO = MI->getOperand(OpNum);
721 O << (float)MO.getFPImm();
728 FPUnion.I = MO.getImm();
733 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
735 const MCOperand &MO = MI->getOperand(OpNum);
740 // We expect the binary encoding of a floating point number here.
746 FPUnion.I = MO.getImm();
751 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
753 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
755 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
756 O << "#0x" << utohexstr(Val);