1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
33 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
34 // Check for MOVs and print canonical forms, instead.
35 if (MI->getOpcode() == ARM::MOVs) {
36 // FIXME: Thumb variants?
37 const MCOperand &Dst = MI->getOperand(0);
38 const MCOperand &MO1 = MI->getOperand(1);
39 const MCOperand &MO2 = MI->getOperand(2);
40 const MCOperand &MO3 = MI->getOperand(3);
42 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
43 printSBitModifierOperand(MI, 6, O);
44 printPredicateOperand(MI, 4, O);
46 O << '\t' << getRegisterName(Dst.getReg())
47 << ", " << getRegisterName(MO1.getReg());
49 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
55 O << getRegisterName(MO2.getReg());
56 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
58 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
64 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
65 MI->getOperand(0).getReg() == ARM::SP) {
66 const MCOperand &MO1 = MI->getOperand(2);
67 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
69 printPredicateOperand(MI, 3, O);
71 printRegisterList(MI, 5, O);
77 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
78 MI->getOperand(0).getReg() == ARM::SP) {
79 const MCOperand &MO1 = MI->getOperand(2);
80 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
82 printPredicateOperand(MI, 3, O);
84 printRegisterList(MI, 5, O);
90 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
91 MI->getOperand(0).getReg() == ARM::SP) {
92 const MCOperand &MO1 = MI->getOperand(2);
93 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
95 printPredicateOperand(MI, 3, O);
97 printRegisterList(MI, 5, O);
103 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
104 MI->getOperand(0).getReg() == ARM::SP) {
105 const MCOperand &MO1 = MI->getOperand(2);
106 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
108 printPredicateOperand(MI, 3, O);
110 printRegisterList(MI, 5, O);
115 printInstruction(MI, O);
118 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
119 raw_ostream &O, const char *Modifier) {
120 const MCOperand &Op = MI->getOperand(OpNo);
122 unsigned Reg = Op.getReg();
123 O << getRegisterName(Reg);
124 } else if (Op.isImm()) {
125 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
126 O << '#' << Op.getImm();
128 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
129 assert(Op.isExpr() && "unknown operand kind in printOperand");
134 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
135 const MCAsmInfo *MAI) {
136 // Break it up into two parts that make up a shifter immediate.
137 V = ARM_AM::getSOImmVal(V);
138 assert(V != -1 && "Not a valid so_imm value!");
140 unsigned Imm = ARM_AM::getSOImmValImm(V);
141 unsigned Rot = ARM_AM::getSOImmValRot(V);
143 // Print low-level immediate formation info, per
144 // A5.1.3: "Data-processing operands - Immediate".
146 O << "#" << Imm << ", " << Rot;
147 // Pretty printed version.
149 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
156 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
157 /// immediate in bits 0-7.
158 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
160 const MCOperand &MO = MI->getOperand(OpNum);
161 assert(MO.isImm() && "Not a valid so_imm value!");
162 printSOImm(O, MO.getImm(), CommentStream, &MAI);
165 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
166 /// followed by an 'orr' to materialize.
167 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
169 // FIXME: REMOVE this method.
173 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
174 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
176 // REG REG 0,SH_OPC - e.g. R5, ROR R3
177 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
178 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
180 const MCOperand &MO1 = MI->getOperand(OpNum);
181 const MCOperand &MO2 = MI->getOperand(OpNum+1);
182 const MCOperand &MO3 = MI->getOperand(OpNum+2);
184 O << getRegisterName(MO1.getReg());
186 // Print the shift opc.
187 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
188 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
190 O << ' ' << getRegisterName(MO2.getReg());
191 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
192 } else if (ShOpc != ARM_AM::rrx) {
193 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
198 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
200 const MCOperand &MO1 = MI->getOperand(Op);
201 const MCOperand &MO2 = MI->getOperand(Op+1);
202 const MCOperand &MO3 = MI->getOperand(Op+2);
204 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
205 printOperand(MI, Op, O);
209 O << "[" << getRegisterName(MO1.getReg());
212 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
214 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
215 << ARM_AM::getAM2Offset(MO3.getImm());
221 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
222 << getRegisterName(MO2.getReg());
224 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
226 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
231 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
234 const MCOperand &MO1 = MI->getOperand(OpNum);
235 const MCOperand &MO2 = MI->getOperand(OpNum+1);
238 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
240 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
245 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
246 << getRegisterName(MO1.getReg());
248 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
250 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
254 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
256 const MCOperand &MO1 = MI->getOperand(OpNum);
257 const MCOperand &MO2 = MI->getOperand(OpNum+1);
258 const MCOperand &MO3 = MI->getOperand(OpNum+2);
260 O << '[' << getRegisterName(MO1.getReg());
263 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
264 << getRegisterName(MO2.getReg()) << ']';
268 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
270 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
275 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
278 const MCOperand &MO1 = MI->getOperand(OpNum);
279 const MCOperand &MO2 = MI->getOperand(OpNum+1);
282 O << (char)ARM_AM::getAM3Op(MO2.getImm())
283 << getRegisterName(MO1.getReg());
287 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
289 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
294 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
296 const char *Modifier) {
297 const MCOperand &MO2 = MI->getOperand(OpNum+1);
298 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
299 if (Modifier && strcmp(Modifier, "submode") == 0) {
300 O << ARM_AM::getAMSubModeStr(Mode);
301 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
302 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
303 if (Mode == ARM_AM::ia)
306 printOperand(MI, OpNum, O);
310 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
312 const char *Modifier) {
313 const MCOperand &MO1 = MI->getOperand(OpNum);
314 const MCOperand &MO2 = MI->getOperand(OpNum+1);
316 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
317 printOperand(MI, OpNum, O);
321 O << "[" << getRegisterName(MO1.getReg());
323 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
325 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
331 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
333 const MCOperand &MO1 = MI->getOperand(OpNum);
334 const MCOperand &MO2 = MI->getOperand(OpNum+1);
336 O << "[" << getRegisterName(MO1.getReg());
338 // FIXME: Both darwin as and GNU as violate ARM docs here.
339 O << ", :" << (MO2.getImm() << 3);
344 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
347 const MCOperand &MO = MI->getOperand(OpNum);
348 if (MO.getReg() == 0)
351 O << ", " << getRegisterName(MO.getReg());
354 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
356 const char *Modifier) {
357 // All instructions using addrmodepc are pseudos and should have been
358 // handled explicitly in printInstructionThroughMCStreamer(). If one got
359 // here, it wasn't, so something's wrong.
360 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
363 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
366 const MCOperand &MO = MI->getOperand(OpNum);
367 uint32_t v = ~MO.getImm();
368 int32_t lsb = CountTrailingZeros_32(v);
369 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
370 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
371 O << '#' << lsb << ", #" << width;
374 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
376 unsigned val = MI->getOperand(OpNum).getImm();
377 O << ARM_MB::MemBOptToString(val);
380 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
382 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
383 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
385 case ARM_AM::no_shift:
394 assert(0 && "unexpected shift opcode for shift immediate operand");
396 O << ARM_AM::getSORegOffset(ShiftOp);
399 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
402 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
403 if (i != OpNum) O << ", ";
404 O << getRegisterName(MI->getOperand(i).getReg());
409 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
411 const MCOperand &Op = MI->getOperand(OpNum);
418 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
420 const MCOperand &Op = MI->getOperand(OpNum);
421 unsigned option = Op.getImm();
422 unsigned mode = option & 31;
423 bool changemode = option >> 5 & 1;
424 unsigned AIF = option >> 6 & 7;
425 unsigned imod = option >> 9 & 3;
432 if (AIF & 4) O << 'a';
433 if (AIF & 2) O << 'i';
434 if (AIF & 1) O << 'f';
435 if (AIF > 0 && changemode) O << ", ";
441 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
443 const MCOperand &Op = MI->getOperand(OpNum);
444 unsigned Mask = Op.getImm();
447 if (Mask & 8) O << 'f';
448 if (Mask & 4) O << 's';
449 if (Mask & 2) O << 'x';
450 if (Mask & 1) O << 'c';
454 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
456 const MCOperand &Op = MI->getOperand(OpNum);
459 O << '-' << (-Op.getImm() - 1);
464 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
466 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
468 O << ARMCondCodeToString(CC);
471 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
474 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
475 O << ARMCondCodeToString(CC);
478 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
480 if (MI->getOperand(OpNum).getReg()) {
481 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
482 "Expect ARM CPSR register!");
489 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
491 const char *Modifier) {
492 // FIXME: remove this.
496 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
498 O << MI->getOperand(OpNum).getImm();
502 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
504 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
507 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
509 O << "#" << MI->getOperand(OpNum).getImm() * 4;
512 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
514 // (3 - the number of trailing zeros) is the number of then / else.
515 unsigned Mask = MI->getOperand(OpNum).getImm();
516 unsigned CondBit0 = Mask >> 4 & 1;
517 unsigned NumTZ = CountTrailingZeros_32(Mask);
518 assert(NumTZ <= 3 && "Invalid IT mask!");
519 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
520 bool T = ((Mask >> Pos) & 1) == CondBit0;
528 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
530 const MCOperand &MO1 = MI->getOperand(Op);
531 const MCOperand &MO2 = MI->getOperand(Op+1);
532 O << "[" << getRegisterName(MO1.getReg());
533 O << ", " << getRegisterName(MO2.getReg()) << "]";
536 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
539 const MCOperand &MO1 = MI->getOperand(Op);
540 const MCOperand &MO2 = MI->getOperand(Op+1);
541 const MCOperand &MO3 = MI->getOperand(Op+2);
543 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
544 printOperand(MI, Op, O);
548 O << "[" << getRegisterName(MO1.getReg());
550 O << ", " << getRegisterName(MO3.getReg());
551 else if (unsigned ImmOffs = MO2.getImm())
552 O << ", #" << ImmOffs * Scale;
556 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
558 printThumbAddrModeRI5Operand(MI, Op, O, 1);
561 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
563 printThumbAddrModeRI5Operand(MI, Op, O, 2);
566 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
568 printThumbAddrModeRI5Operand(MI, Op, O, 4);
571 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
573 const MCOperand &MO1 = MI->getOperand(Op);
574 const MCOperand &MO2 = MI->getOperand(Op+1);
575 O << "[" << getRegisterName(MO1.getReg());
576 if (unsigned ImmOffs = MO2.getImm())
577 O << ", #" << ImmOffs*4;
581 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
583 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
584 if (MI->getOpcode() == ARM::t2TBH)
589 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
590 // register with shift forms.
592 // REG IMM, SH_OPC - e.g. R5, LSL #3
593 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
595 const MCOperand &MO1 = MI->getOperand(OpNum);
596 const MCOperand &MO2 = MI->getOperand(OpNum+1);
598 unsigned Reg = MO1.getReg();
599 O << getRegisterName(Reg);
601 // Print the shift opc.
602 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
603 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
604 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
605 if (ShOpc != ARM_AM::rrx)
606 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
609 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
611 const MCOperand &MO1 = MI->getOperand(OpNum);
612 const MCOperand &MO2 = MI->getOperand(OpNum+1);
614 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
615 printOperand(MI, OpNum, O);
619 O << "[" << getRegisterName(MO1.getReg());
621 int32_t OffImm = (int32_t)MO2.getImm();
622 bool isSub = OffImm < 0;
623 // Special value for #-0. All others are normal.
624 if (OffImm == INT32_MIN)
627 O << ", #-" << -OffImm;
629 O << ", #" << OffImm;
633 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
636 const MCOperand &MO1 = MI->getOperand(OpNum);
637 const MCOperand &MO2 = MI->getOperand(OpNum+1);
639 O << "[" << getRegisterName(MO1.getReg());
641 int32_t OffImm = (int32_t)MO2.getImm();
644 O << ", #-" << -OffImm;
646 O << ", #" << OffImm;
650 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
653 const MCOperand &MO1 = MI->getOperand(OpNum);
654 const MCOperand &MO2 = MI->getOperand(OpNum+1);
656 O << "[" << getRegisterName(MO1.getReg());
658 int32_t OffImm = (int32_t)MO2.getImm() / 4;
661 O << ", #-" << -OffImm * 4;
663 O << ", #" << OffImm * 4;
667 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
670 const MCOperand &MO1 = MI->getOperand(OpNum);
671 int32_t OffImm = (int32_t)MO1.getImm();
674 O << "#-" << -OffImm;
679 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
682 const MCOperand &MO1 = MI->getOperand(OpNum);
683 int32_t OffImm = (int32_t)MO1.getImm() / 4;
686 O << "#-" << -OffImm * 4;
688 O << "#" << OffImm * 4;
691 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
694 const MCOperand &MO1 = MI->getOperand(OpNum);
695 const MCOperand &MO2 = MI->getOperand(OpNum+1);
696 const MCOperand &MO3 = MI->getOperand(OpNum+2);
698 O << "[" << getRegisterName(MO1.getReg());
700 assert(MO2.getReg() && "Invalid so_reg load / store address!");
701 O << ", " << getRegisterName(MO2.getReg());
703 unsigned ShAmt = MO3.getImm();
705 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
706 O << ", lsl #" << ShAmt;
711 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
713 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
716 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
718 O << '#' << MI->getOperand(OpNum).getFPImm();
721 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
723 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
725 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
726 O << "#0x" << utohexstr(Val);