1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
32 StringRef ARMInstPrinter::getRegName(unsigned RegNo) const {
33 return getRegisterName(RegNo);
36 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
37 unsigned Opcode = MI->getOpcode();
39 // Check for MOVs and print canonical forms, instead.
40 if (Opcode == ARM::MOVs) {
41 // FIXME: Thumb variants?
42 const MCOperand &Dst = MI->getOperand(0);
43 const MCOperand &MO1 = MI->getOperand(1);
44 const MCOperand &MO2 = MI->getOperand(2);
45 const MCOperand &MO3 = MI->getOperand(3);
47 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
48 printSBitModifierOperand(MI, 6, O);
49 printPredicateOperand(MI, 4, O);
51 O << '\t' << getRegisterName(Dst.getReg())
52 << ", " << getRegisterName(MO1.getReg());
54 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
60 O << getRegisterName(MO2.getReg());
61 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
63 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
69 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
70 MI->getOperand(0).getReg() == ARM::SP) {
72 printPredicateOperand(MI, 2, O);
73 if (Opcode == ARM::t2STMDB_UPD)
76 printRegisterList(MI, 4, O);
81 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
82 MI->getOperand(0).getReg() == ARM::SP) {
84 printPredicateOperand(MI, 2, O);
85 if (Opcode == ARM::t2LDMIA_UPD)
88 printRegisterList(MI, 4, O);
93 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
94 MI->getOperand(0).getReg() == ARM::SP) {
96 printPredicateOperand(MI, 2, O);
98 printRegisterList(MI, 4, O);
103 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
104 MI->getOperand(0).getReg() == ARM::SP) {
106 printPredicateOperand(MI, 2, O);
108 printRegisterList(MI, 4, O);
112 printInstruction(MI, O);
115 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
117 const MCOperand &Op = MI->getOperand(OpNo);
119 unsigned Reg = Op.getReg();
120 O << getRegisterName(Reg);
121 } else if (Op.isImm()) {
122 O << '#' << Op.getImm();
124 assert(Op.isExpr() && "unknown operand kind in printOperand");
129 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
130 const MCAsmInfo *MAI) {
131 // Break it up into two parts that make up a shifter immediate.
132 V = ARM_AM::getSOImmVal(V);
133 assert(V != -1 && "Not a valid so_imm value!");
135 unsigned Imm = ARM_AM::getSOImmValImm(V);
136 unsigned Rot = ARM_AM::getSOImmValRot(V);
138 // Print low-level immediate formation info, per
139 // A5.1.3: "Data-processing operands - Immediate".
141 O << "#" << Imm << ", " << Rot;
142 // Pretty printed version.
144 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
151 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
152 /// immediate in bits 0-7.
153 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
155 const MCOperand &MO = MI->getOperand(OpNum);
156 assert(MO.isImm() && "Not a valid so_imm value!");
157 printSOImm(O, MO.getImm(), CommentStream, &MAI);
160 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
161 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
163 // REG REG 0,SH_OPC - e.g. R5, ROR R3
164 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
165 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
167 const MCOperand &MO1 = MI->getOperand(OpNum);
168 const MCOperand &MO2 = MI->getOperand(OpNum+1);
169 const MCOperand &MO3 = MI->getOperand(OpNum+2);
171 O << getRegisterName(MO1.getReg());
173 // Print the shift opc.
174 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
175 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
177 O << ' ' << getRegisterName(MO2.getReg());
178 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
179 } else if (ShOpc != ARM_AM::rrx) {
180 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
184 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
186 const MCOperand &MO1 = MI->getOperand(Op);
187 const MCOperand &MO2 = MI->getOperand(Op+1);
188 const MCOperand &MO3 = MI->getOperand(Op+2);
190 O << "[" << getRegisterName(MO1.getReg());
193 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
195 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
196 << ARM_AM::getAM2Offset(MO3.getImm());
202 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
203 << getRegisterName(MO2.getReg());
205 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
207 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
212 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
214 const MCOperand &MO1 = MI->getOperand(Op);
215 const MCOperand &MO2 = MI->getOperand(Op+1);
216 const MCOperand &MO3 = MI->getOperand(Op+2);
218 O << "[" << getRegisterName(MO1.getReg()) << "], ";
221 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
223 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
228 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
229 << getRegisterName(MO2.getReg());
231 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
233 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
237 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
239 const MCOperand &MO1 = MI->getOperand(Op);
241 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
242 printOperand(MI, Op, O);
246 const MCOperand &MO3 = MI->getOperand(Op+2);
247 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
249 if (IdxMode == ARMII::IndexModePost) {
250 printAM2PostIndexOp(MI, Op, O);
253 printAM2PreOrOffsetIndexOp(MI, Op, O);
256 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
259 const MCOperand &MO1 = MI->getOperand(OpNum);
260 const MCOperand &MO2 = MI->getOperand(OpNum+1);
263 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
265 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
270 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
271 << getRegisterName(MO1.getReg());
273 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
275 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
279 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
281 const MCOperand &MO1 = MI->getOperand(OpNum);
282 const MCOperand &MO2 = MI->getOperand(OpNum+1);
283 const MCOperand &MO3 = MI->getOperand(OpNum+2);
285 O << '[' << getRegisterName(MO1.getReg());
288 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
289 << getRegisterName(MO2.getReg()) << ']';
293 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
295 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
300 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
303 const MCOperand &MO1 = MI->getOperand(OpNum);
304 const MCOperand &MO2 = MI->getOperand(OpNum+1);
307 O << (char)ARM_AM::getAM3Op(MO2.getImm())
308 << getRegisterName(MO1.getReg());
312 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
314 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
318 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
320 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
322 O << ARM_AM::getAMSubModeStr(Mode);
325 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
327 const MCOperand &MO1 = MI->getOperand(OpNum);
328 const MCOperand &MO2 = MI->getOperand(OpNum+1);
330 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
331 printOperand(MI, OpNum, O);
335 O << "[" << getRegisterName(MO1.getReg());
337 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
339 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
345 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
347 const MCOperand &MO1 = MI->getOperand(OpNum);
348 const MCOperand &MO2 = MI->getOperand(OpNum+1);
350 O << "[" << getRegisterName(MO1.getReg());
352 // FIXME: Both darwin as and GNU as violate ARM docs here.
353 O << ", :" << (MO2.getImm() << 3);
358 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
360 const MCOperand &MO1 = MI->getOperand(OpNum);
361 O << "[" << getRegisterName(MO1.getReg()) << "]";
364 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
367 const MCOperand &MO = MI->getOperand(OpNum);
368 if (MO.getReg() == 0)
371 O << ", " << getRegisterName(MO.getReg());
374 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
377 const MCOperand &MO = MI->getOperand(OpNum);
378 uint32_t v = ~MO.getImm();
379 int32_t lsb = CountTrailingZeros_32(v);
380 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
381 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
382 O << '#' << lsb << ", #" << width;
385 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
387 unsigned val = MI->getOperand(OpNum).getImm();
388 O << ARM_MB::MemBOptToString(val);
391 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
393 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
394 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
396 case ARM_AM::no_shift:
405 assert(0 && "unexpected shift opcode for shift immediate operand");
407 O << ARM_AM::getSORegOffset(ShiftOp);
410 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
413 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
414 if (i != OpNum) O << ", ";
415 O << getRegisterName(MI->getOperand(i).getReg());
420 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
422 const MCOperand &Op = MI->getOperand(OpNum);
429 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
431 const MCOperand &Op = MI->getOperand(OpNum);
432 O << ARM_PROC::IModToString(Op.getImm());
435 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
437 const MCOperand &Op = MI->getOperand(OpNum);
438 unsigned IFlags = Op.getImm();
439 for (int i=2; i >= 0; --i)
440 if (IFlags & (1 << i))
441 O << ARM_PROC::IFlagsToString(1 << i);
444 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
446 const MCOperand &Op = MI->getOperand(OpNum);
447 unsigned SpecRegRBit = Op.getImm() >> 4;
448 unsigned Mask = Op.getImm() & 0xf;
457 if (Mask & 8) O << 'f';
458 if (Mask & 4) O << 's';
459 if (Mask & 2) O << 'x';
460 if (Mask & 1) O << 'c';
464 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
466 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
468 O << ARMCondCodeToString(CC);
471 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
474 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
475 O << ARMCondCodeToString(CC);
478 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
480 if (MI->getOperand(OpNum).getReg()) {
481 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
482 "Expect ARM CPSR register!");
487 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
489 O << MI->getOperand(OpNum).getImm();
492 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
494 O << "p" << MI->getOperand(OpNum).getImm();
497 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
499 O << "c" << MI->getOperand(OpNum).getImm();
502 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
504 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
507 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
509 O << "#" << MI->getOperand(OpNum).getImm() * 4;
512 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
514 // (3 - the number of trailing zeros) is the number of then / else.
515 unsigned Mask = MI->getOperand(OpNum).getImm();
516 unsigned CondBit0 = Mask >> 4 & 1;
517 unsigned NumTZ = CountTrailingZeros_32(Mask);
518 assert(NumTZ <= 3 && "Invalid IT mask!");
519 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
520 bool T = ((Mask >> Pos) & 1) == CondBit0;
528 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
530 const MCOperand &MO1 = MI->getOperand(Op);
531 const MCOperand &MO2 = MI->getOperand(Op + 1);
533 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
534 printOperand(MI, Op, O);
538 O << "[" << getRegisterName(MO1.getReg());
539 if (unsigned RegNum = MO2.getReg())
540 O << ", " << getRegisterName(RegNum);
544 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
548 const MCOperand &MO1 = MI->getOperand(Op);
549 const MCOperand &MO2 = MI->getOperand(Op + 1);
551 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
552 printOperand(MI, Op, O);
556 O << "[" << getRegisterName(MO1.getReg());
557 if (unsigned ImmOffs = MO2.getImm())
558 O << ", #" << ImmOffs * Scale;
562 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
565 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
568 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
571 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
574 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
577 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
580 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
582 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
585 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
586 // register with shift forms.
588 // REG IMM, SH_OPC - e.g. R5, LSL #3
589 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
591 const MCOperand &MO1 = MI->getOperand(OpNum);
592 const MCOperand &MO2 = MI->getOperand(OpNum+1);
594 unsigned Reg = MO1.getReg();
595 O << getRegisterName(Reg);
597 // Print the shift opc.
598 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
599 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
600 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
601 if (ShOpc != ARM_AM::rrx)
602 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
605 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
607 const MCOperand &MO1 = MI->getOperand(OpNum);
608 const MCOperand &MO2 = MI->getOperand(OpNum+1);
610 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
611 printOperand(MI, OpNum, O);
615 O << "[" << getRegisterName(MO1.getReg());
617 int32_t OffImm = (int32_t)MO2.getImm();
618 bool isSub = OffImm < 0;
619 // Special value for #-0. All others are normal.
620 if (OffImm == INT32_MIN)
623 O << ", #-" << -OffImm;
625 O << ", #" << OffImm;
629 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
632 const MCOperand &MO1 = MI->getOperand(OpNum);
633 const MCOperand &MO2 = MI->getOperand(OpNum+1);
635 O << "[" << getRegisterName(MO1.getReg());
637 int32_t OffImm = (int32_t)MO2.getImm();
640 O << ", #-" << -OffImm;
642 O << ", #" << OffImm;
646 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
649 const MCOperand &MO1 = MI->getOperand(OpNum);
650 const MCOperand &MO2 = MI->getOperand(OpNum+1);
652 O << "[" << getRegisterName(MO1.getReg());
654 int32_t OffImm = (int32_t)MO2.getImm() / 4;
657 O << ", #-" << -OffImm * 4;
659 O << ", #" << OffImm * 4;
663 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
666 const MCOperand &MO1 = MI->getOperand(OpNum);
667 int32_t OffImm = (int32_t)MO1.getImm();
670 O << "#-" << -OffImm;
675 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
678 const MCOperand &MO1 = MI->getOperand(OpNum);
679 int32_t OffImm = (int32_t)MO1.getImm() / 4;
682 O << "#-" << -OffImm * 4;
684 O << "#" << OffImm * 4;
687 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
690 const MCOperand &MO1 = MI->getOperand(OpNum);
691 const MCOperand &MO2 = MI->getOperand(OpNum+1);
692 const MCOperand &MO3 = MI->getOperand(OpNum+2);
694 O << "[" << getRegisterName(MO1.getReg());
696 assert(MO2.getReg() && "Invalid so_reg load / store address!");
697 O << ", " << getRegisterName(MO2.getReg());
699 unsigned ShAmt = MO3.getImm();
701 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
702 O << ", lsl #" << ShAmt;
707 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
709 const MCOperand &MO = MI->getOperand(OpNum);
712 O << (float)MO.getFPImm();
719 FPUnion.I = MO.getImm();
724 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
726 const MCOperand &MO = MI->getOperand(OpNum);
731 // We expect the binary encoding of a floating point number here.
737 FPUnion.I = MO.getImm();
742 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
744 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
746 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
747 O << "#0x" << utohexstr(Val);