1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMFixupKinds.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/MC/MCAsmBackend.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDirectives.h"
19 #include "llvm/MC/MCELFObjectWriter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCFixupKindInfo.h"
22 #include "llvm/MC/MCMachObjectWriter.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCSectionELF.h"
25 #include "llvm/MC/MCSectionMachO.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/Support/ELF.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MachO.h"
31 #include "llvm/Support/raw_ostream.h"
35 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
37 ARMELFObjectWriter(uint8_t OSABI)
38 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
39 /*HasRelocationAddend*/ false) {}
42 class ARMAsmBackend : public MCAsmBackend {
43 const MCSubtargetInfo* STI;
44 bool isThumbMode; // Currently emitting Thumb code.
45 bool IsLittleEndian; // Big or little endian.
47 ARMAsmBackend(const Target &T, const StringRef TT, bool IsLittle)
48 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
49 isThumbMode(TT.startswith("thumb")), IsLittleEndian(IsLittle) {}
55 unsigned getNumFixupKinds() const override {
56 return ARM::NumTargetFixupKinds;
60 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
63 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
64 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
65 // This table *must* be in the order that the fixup_* kinds are defined in
68 // Name Offset (bits) Size (bits) Flags
69 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
72 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
73 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
77 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
78 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
80 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
81 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
88 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
89 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
90 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
91 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
92 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
93 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
94 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
95 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
96 { "fixup_arm_movt_hi16", 0, 20, 0 },
97 { "fixup_arm_movw_lo16", 0, 20, 0 },
98 { "fixup_t2_movt_hi16", 0, 20, 0 },
99 { "fixup_t2_movw_lo16", 0, 20, 0 },
101 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
102 // This table *must* be in the order that the fixup_* kinds are defined in
105 // Name Offset (bits) Size (bits) Flags
106 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
107 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
108 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
109 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
112 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
113 { "fixup_thumb_adr_pcrel_10",8, 8, MCFixupKindInfo::FKF_IsPCRel |
114 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
115 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
117 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
118 { "fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
119 { "fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
120 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
121 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
122 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
123 { "fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
124 { "fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
125 { "fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
126 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
127 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
128 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
129 { "fixup_arm_thumb_cp", 8, 8, MCFixupKindInfo::FKF_IsPCRel |
130 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
131 { "fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel },
132 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
133 { "fixup_arm_movt_hi16", 12, 20, 0 },
134 { "fixup_arm_movw_lo16", 12, 20, 0 },
135 { "fixup_t2_movt_hi16", 12, 20, 0 },
136 { "fixup_t2_movw_lo16", 12, 20, 0 },
139 if (Kind < FirstTargetFixupKind)
140 return MCAsmBackend::getFixupKindInfo(Kind);
142 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
144 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
147 /// processFixupValue - Target hook to process the literal value of a fixup
149 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
150 const MCFixup &Fixup, const MCFragment *DF,
151 const MCValue &Target, uint64_t &Value,
152 bool &IsResolved) override;
155 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
156 uint64_t Value, bool IsPCRel) const override;
158 bool mayNeedRelaxation(const MCInst &Inst) const override;
160 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
161 const MCRelaxableFragment *DF,
162 const MCAsmLayout &Layout) const override;
164 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
166 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
168 void handleAssemblerFlag(MCAssemblerFlag Flag) override {
180 unsigned getPointerSize() const { return 4; }
181 bool isThumb() const { return isThumbMode; }
182 void setIsThumb(bool it) { isThumbMode = it; }
183 bool isLittle() const { return IsLittleEndian; }
185 } // end anonymous namespace
187 static unsigned getRelaxedOpcode(unsigned Op) {
190 case ARM::tBcc: return ARM::t2Bcc;
191 case ARM::tLDRpci: return ARM::t2LDRpci;
192 case ARM::tADR: return ARM::t2ADR;
193 case ARM::tB: return ARM::t2B;
194 case ARM::tCBZ: return ARM::tHINT;
195 case ARM::tCBNZ: return ARM::tHINT;
199 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
200 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
205 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
207 const MCRelaxableFragment *DF,
208 const MCAsmLayout &Layout) const {
209 switch ((unsigned)Fixup.getKind()) {
210 case ARM::fixup_arm_thumb_br: {
211 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
212 // low bit being an implied zero. There's an implied +4 offset for the
213 // branch, so we adjust the other way here to determine what's
216 // Relax if the value is too big for a (signed) i8.
217 int64_t Offset = int64_t(Value) - 4;
218 return Offset > 2046 || Offset < -2048;
220 case ARM::fixup_arm_thumb_bcc: {
221 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
222 // low bit being an implied zero. There's an implied +4 offset for the
223 // branch, so we adjust the other way here to determine what's
226 // Relax if the value is too big for a (signed) i8.
227 int64_t Offset = int64_t(Value) - 4;
228 return Offset > 254 || Offset < -256;
230 case ARM::fixup_thumb_adr_pcrel_10:
231 case ARM::fixup_arm_thumb_cp: {
232 // If the immediate is negative, greater than 1020, or not a multiple
233 // of four, the wide version of the instruction must be used.
234 int64_t Offset = int64_t(Value) - 4;
235 return Offset > 1020 || Offset < 0 || Offset & 3;
237 case ARM::fixup_arm_thumb_cb:
238 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
239 // instruction it is is actually out of range for the instruction.
240 // It will be changed to a NOP.
241 int64_t Offset = (Value & ~1);
244 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
247 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
248 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
250 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
251 if (RelaxedOp == Inst.getOpcode()) {
252 SmallString<256> Tmp;
253 raw_svector_ostream OS(Tmp);
254 Inst.dump_pretty(OS);
256 report_fatal_error("unexpected instruction to relax: " + OS.str());
259 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
260 // have to change the operands too.
261 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
262 RelaxedOp == ARM::tHINT) {
263 Res.setOpcode(RelaxedOp);
264 Res.addOperand(MCOperand::CreateImm(0));
265 Res.addOperand(MCOperand::CreateImm(14));
266 Res.addOperand(MCOperand::CreateReg(0));
270 // The rest of instructions we're relaxing have the same operands.
271 // We just need to update to the proper opcode.
273 Res.setOpcode(RelaxedOp);
276 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
277 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
278 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
279 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
280 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
282 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
283 : Thumb1_16bitNopEncoding;
284 uint64_t NumNops = Count / 2;
285 for (uint64_t i = 0; i != NumNops; ++i)
286 OW->Write16(nopEncoding);
292 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
294 uint64_t NumNops = Count / 4;
295 for (uint64_t i = 0; i != NumNops; ++i)
296 OW->Write32(nopEncoding);
297 // FIXME: should this function return false when unable to write exactly
298 // 'Count' bytes with NOP encodings?
300 default: break; // No leftover bytes to write
301 case 1: OW->Write8(0); break;
302 case 2: OW->Write16(0); break;
303 case 3: OW->Write16(0); OW->Write8(0xa0); break;
309 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
310 bool IsPCRel, MCContext *Ctx) {
311 unsigned Kind = Fixup.getKind();
314 llvm_unreachable("Unknown fixup kind!");
319 case ARM::fixup_arm_movt_hi16:
323 case ARM::fixup_arm_movw_lo16: {
324 unsigned Hi4 = (Value & 0xF000) >> 12;
325 unsigned Lo12 = Value & 0x0FFF;
326 // inst{19-16} = Hi4;
327 // inst{11-0} = Lo12;
328 Value = (Hi4 << 16) | (Lo12);
331 case ARM::fixup_t2_movt_hi16:
335 case ARM::fixup_t2_movw_lo16: {
336 unsigned Hi4 = (Value & 0xF000) >> 12;
337 unsigned i = (Value & 0x800) >> 11;
338 unsigned Mid3 = (Value & 0x700) >> 8;
339 unsigned Lo8 = Value & 0x0FF;
340 // inst{19-16} = Hi4;
342 // inst{14-12} = Mid3;
344 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
345 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
346 swapped |= (Value & 0x0000FFFF) << 16;
349 case ARM::fixup_arm_ldst_pcrel_12:
350 // ARM PC-relative values are offset by 8.
353 case ARM::fixup_t2_ldst_pcrel_12: {
354 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
357 if ((int64_t)Value < 0) {
361 if (Ctx && Value >= 4096)
362 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
363 Value |= isAdd << 23;
365 // Same addressing mode as fixup_arm_pcrel_10,
366 // but with 16-bit halfwords swapped.
367 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
368 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
369 swapped |= (Value & 0x0000FFFF) << 16;
375 case ARM::fixup_thumb_adr_pcrel_10:
376 return ((Value - 4) >> 2) & 0xff;
377 case ARM::fixup_arm_adr_pcrel_12: {
378 // ARM PC-relative values are offset by 8.
380 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
381 if ((int64_t)Value < 0) {
385 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
386 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
387 // Encode the immediate and shift the opcode into place.
388 return ARM_AM::getSOImmVal(Value) | (opc << 21);
391 case ARM::fixup_t2_adr_pcrel_12: {
394 if ((int64_t)Value < 0) {
399 uint32_t out = (opc << 21);
400 out |= (Value & 0x800) << 15;
401 out |= (Value & 0x700) << 4;
402 out |= (Value & 0x0FF);
404 uint64_t swapped = (out & 0xFFFF0000) >> 16;
405 swapped |= (out & 0x0000FFFF) << 16;
409 case ARM::fixup_arm_condbranch:
410 case ARM::fixup_arm_uncondbranch:
411 case ARM::fixup_arm_uncondbl:
412 case ARM::fixup_arm_condbl:
413 case ARM::fixup_arm_blx:
414 // These values don't encode the low two bits since they're always zero.
415 // Offset by 8 just as above.
416 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
417 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
419 return 0xffffff & ((Value - 8) >> 2);
420 case ARM::fixup_t2_uncondbranch: {
422 Value >>= 1; // Low bit is not encoded.
425 bool I = Value & 0x800000;
426 bool J1 = Value & 0x400000;
427 bool J2 = Value & 0x200000;
431 out |= I << 26; // S bit
432 out |= !J1 << 13; // J1 bit
433 out |= !J2 << 11; // J2 bit
434 out |= (Value & 0x1FF800) << 5; // imm6 field
435 out |= (Value & 0x0007FF); // imm11 field
437 uint64_t swapped = (out & 0xFFFF0000) >> 16;
438 swapped |= (out & 0x0000FFFF) << 16;
441 case ARM::fixup_t2_condbranch: {
443 Value >>= 1; // Low bit is not encoded.
446 out |= (Value & 0x80000) << 7; // S bit
447 out |= (Value & 0x40000) >> 7; // J2 bit
448 out |= (Value & 0x20000) >> 4; // J1 bit
449 out |= (Value & 0x1F800) << 5; // imm6 field
450 out |= (Value & 0x007FF); // imm11 field
452 uint32_t swapped = (out & 0xFFFF0000) >> 16;
453 swapped |= (out & 0x0000FFFF) << 16;
456 case ARM::fixup_arm_thumb_bl: {
457 // The value doesn't encode the low bit (always zero) and is offset by
458 // four. The 32-bit immediate value is encoded as
459 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
460 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
461 // The value is encoded into disjoint bit positions in the destination
462 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
463 // J = either J1 or J2 bit
465 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
467 // Note that the halfwords are stored high first, low second; so we need
468 // to transpose the fixup value here to map properly.
469 uint32_t offset = (Value - 4) >> 1;
470 uint32_t signBit = (offset & 0x800000) >> 23;
471 uint32_t I1Bit = (offset & 0x400000) >> 22;
472 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
473 uint32_t I2Bit = (offset & 0x200000) >> 21;
474 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
475 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
476 uint32_t imm11Bits = (offset & 0x000007FF);
479 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
480 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
481 (uint16_t)imm11Bits);
482 Binary |= secondHalf << 16;
486 case ARM::fixup_arm_thumb_blx: {
487 // The value doesn't encode the low two bits (always zero) and is offset by
488 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
489 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
490 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
491 // The value is encoded into disjoint bit positions in the destination
492 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
493 // J = either J1 or J2 bit, 0 = zero.
495 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
497 // Note that the halfwords are stored high first, low second; so we need
498 // to transpose the fixup value here to map properly.
499 uint32_t offset = (Value - 2) >> 2;
500 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
501 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
503 uint32_t signBit = (offset & 0x400000) >> 22;
504 uint32_t I1Bit = (offset & 0x200000) >> 21;
505 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
506 uint32_t I2Bit = (offset & 0x100000) >> 20;
507 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
508 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
509 uint32_t imm10LBits = (offset & 0x3FF);
512 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
513 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
514 ((uint16_t)imm10LBits) << 1);
515 Binary |= secondHalf << 16;
519 case ARM::fixup_arm_thumb_cp:
520 // Offset by 4, and don't encode the low two bits. Two bytes of that
521 // 'off by 4' is implicitly handled by the half-word ordering of the
522 // Thumb encoding, so we only need to adjust by 2 here.
523 return ((Value - 2) >> 2) & 0xff;
524 case ARM::fixup_arm_thumb_cb: {
525 // Offset by 4 and don't encode the lower bit, which is always 0.
526 uint32_t Binary = (Value - 4) >> 1;
527 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
529 case ARM::fixup_arm_thumb_br:
530 // Offset by 4 and don't encode the lower bit, which is always 0.
531 return ((Value - 4) >> 1) & 0x7ff;
532 case ARM::fixup_arm_thumb_bcc:
533 // Offset by 4 and don't encode the lower bit, which is always 0.
534 return ((Value - 4) >> 1) & 0xff;
535 case ARM::fixup_arm_pcrel_10_unscaled: {
536 Value = Value - 8; // ARM fixups offset by an additional word and don't
537 // need to adjust for the half-word ordering.
539 if ((int64_t)Value < 0) {
543 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
544 if (Ctx && Value >= 256)
545 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
546 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
547 return Value | (isAdd << 23);
549 case ARM::fixup_arm_pcrel_10:
550 Value = Value - 4; // ARM fixups offset by an additional word and don't
551 // need to adjust for the half-word ordering.
553 case ARM::fixup_t2_pcrel_10: {
554 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
557 if ((int64_t)Value < 0) {
561 // These values don't encode the low two bits since they're always zero.
563 if (Ctx && Value >= 256)
564 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
565 Value |= isAdd << 23;
567 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
569 if (Kind == ARM::fixup_t2_pcrel_10) {
570 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
571 swapped |= (Value & 0x0000FFFF) << 16;
580 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
581 const MCAsmLayout &Layout,
582 const MCFixup &Fixup,
583 const MCFragment *DF,
584 const MCValue &Target, uint64_t &Value,
586 const MCSymbolRefExpr *A = Target.getSymA();
587 // Some fixups to thumb function symbols need the low bit (thumb bit)
589 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
590 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
591 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
592 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
593 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
594 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
596 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
597 if (Asm.isThumbFunc(&Sym))
601 // For Thumb1 BL instruction, it is possible to be a long jump between
602 // the basic blocks of the same function. Thus, we would like to resolve
603 // the offset when the destination has the same MCFragment.
604 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
605 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
606 MCSymbolData &SymData = Asm.getSymbolData(Sym);
607 IsResolved = (SymData.getFragment() == DF);
609 // We must always generate a relocation for BL/BLX instructions if we have
610 // a symbol to reference, as the linker relies on knowing the destination
611 // symbol's thumb-ness to get interworking right.
612 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
613 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
614 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
615 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
618 // Try to get the encoded value for the fixup as-if we're mapping it into
619 // the instruction. This allows adjustFixupValue() to issue a diagnostic
620 // if the value aren't invalid.
621 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext());
624 /// getFixupKindNumBytes - The number of bytes the fixup may change.
625 static unsigned getFixupKindNumBytes(unsigned Kind) {
628 llvm_unreachable("Unknown fixup kind!");
631 case ARM::fixup_arm_thumb_bcc:
632 case ARM::fixup_arm_thumb_cp:
633 case ARM::fixup_thumb_adr_pcrel_10:
637 case ARM::fixup_arm_thumb_br:
638 case ARM::fixup_arm_thumb_cb:
641 case ARM::fixup_arm_pcrel_10_unscaled:
642 case ARM::fixup_arm_ldst_pcrel_12:
643 case ARM::fixup_arm_pcrel_10:
644 case ARM::fixup_arm_adr_pcrel_12:
645 case ARM::fixup_arm_uncondbl:
646 case ARM::fixup_arm_condbl:
647 case ARM::fixup_arm_blx:
648 case ARM::fixup_arm_condbranch:
649 case ARM::fixup_arm_uncondbranch:
653 case ARM::fixup_t2_ldst_pcrel_12:
654 case ARM::fixup_t2_condbranch:
655 case ARM::fixup_t2_uncondbranch:
656 case ARM::fixup_t2_pcrel_10:
657 case ARM::fixup_t2_adr_pcrel_12:
658 case ARM::fixup_arm_thumb_bl:
659 case ARM::fixup_arm_thumb_blx:
660 case ARM::fixup_arm_movt_hi16:
661 case ARM::fixup_arm_movw_lo16:
662 case ARM::fixup_t2_movt_hi16:
663 case ARM::fixup_t2_movw_lo16:
668 /// getFixupKindContainerSizeBytes - The number of bytes of the
669 /// container involved in big endian.
670 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
673 llvm_unreachable("Unknown fixup kind!");
682 case ARM::fixup_arm_thumb_bcc:
683 case ARM::fixup_arm_thumb_cp:
684 case ARM::fixup_thumb_adr_pcrel_10:
685 case ARM::fixup_arm_thumb_br:
686 case ARM::fixup_arm_thumb_cb:
687 // Instruction size is 2 bytes.
690 case ARM::fixup_arm_pcrel_10_unscaled:
691 case ARM::fixup_arm_ldst_pcrel_12:
692 case ARM::fixup_arm_pcrel_10:
693 case ARM::fixup_arm_adr_pcrel_12:
694 case ARM::fixup_arm_uncondbl:
695 case ARM::fixup_arm_condbl:
696 case ARM::fixup_arm_blx:
697 case ARM::fixup_arm_condbranch:
698 case ARM::fixup_arm_uncondbranch:
699 case ARM::fixup_t2_ldst_pcrel_12:
700 case ARM::fixup_t2_condbranch:
701 case ARM::fixup_t2_uncondbranch:
702 case ARM::fixup_t2_pcrel_10:
703 case ARM::fixup_t2_adr_pcrel_12:
704 case ARM::fixup_arm_thumb_bl:
705 case ARM::fixup_arm_thumb_blx:
706 case ARM::fixup_arm_movt_hi16:
707 case ARM::fixup_arm_movw_lo16:
708 case ARM::fixup_t2_movt_hi16:
709 case ARM::fixup_t2_movw_lo16:
710 // Instruction size is 4 bytes.
715 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
716 unsigned DataSize, uint64_t Value,
717 bool IsPCRel) const {
718 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
719 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr);
720 if (!Value) return; // Doesn't change encoding.
722 unsigned Offset = Fixup.getOffset();
723 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
725 // Used to point to big endian bytes.
726 unsigned FullSizeBytes;
728 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
730 // For each byte of the fragment that the fixup touches, mask in the bits from
731 // the fixup value. The Value has been "split up" into the appropriate
733 for (unsigned i = 0; i != NumBytes; ++i) {
734 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
735 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
741 // FIXME: This should be in a separate file.
742 // ELF is an ELF of course...
743 class ELFARMAsmBackend : public ARMAsmBackend {
746 ELFARMAsmBackend(const Target &T, const StringRef TT,
747 uint8_t _OSABI, bool _IsLittle)
748 : ARMAsmBackend(T, TT, _IsLittle), OSABI(_OSABI) { }
750 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
751 return createARMELFObjectWriter(OS, OSABI, isLittle());
755 // FIXME: This should be in a separate file.
756 class DarwinARMAsmBackend : public ARMAsmBackend {
758 const MachO::CPUSubTypeARM Subtype;
759 DarwinARMAsmBackend(const Target &T, const StringRef TT,
760 MachO::CPUSubTypeARM st)
761 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
762 HasDataInCodeSupport = true;
765 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
766 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
772 } // end anonymous namespace
774 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
775 const MCRegisterInfo &MRI,
776 StringRef TT, StringRef CPU,
778 Triple TheTriple(TT);
780 if (TheTriple.isOSBinFormatMachO()) {
781 MachO::CPUSubTypeARM CS =
782 StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName())
783 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T)
784 .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ)
785 .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6)
786 .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M)
787 .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM)
788 .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K)
789 .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M)
790 .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S)
791 .Default(MachO::CPU_SUBTYPE_ARM_V7);
793 return new DarwinARMAsmBackend(T, TT, CS);
797 // FIXME: Introduce yet another checker but assert(0).
798 if (TheTriple.isOSBinFormatCOFF())
799 assert(0 && "Windows not supported on ARM");
802 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
803 return new ELFARMAsmBackend(T, TT, OSABI, isLittle);
806 MCAsmBackend *llvm::createARMleAsmBackend(const Target &T,
807 const MCRegisterInfo &MRI,
808 StringRef TT, StringRef CPU) {
809 return createARMAsmBackend(T, MRI, TT, CPU, true);
812 MCAsmBackend *llvm::createARMbeAsmBackend(const Target &T,
813 const MCRegisterInfo &MRI,
814 StringRef TT, StringRef CPU) {
815 return createARMAsmBackend(T, MRI, TT, CPU, false);
818 MCAsmBackend *llvm::createThumbleAsmBackend(const Target &T,
819 const MCRegisterInfo &MRI,
820 StringRef TT, StringRef CPU) {
821 return createARMAsmBackend(T, MRI, TT, CPU, true);
824 MCAsmBackend *llvm::createThumbbeAsmBackend(const Target &T,
825 const MCRegisterInfo &MRI,
826 StringRef TT, StringRef CPU) {
827 return createARMAsmBackend(T, MRI, TT, CPU, false);