1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMAsmBackend.h"
13 #include "MCTargetDesc/ARMAsmBackendDarwin.h"
14 #include "MCTargetDesc/ARMAsmBackendELF.h"
15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDirectives.h"
23 #include "llvm/MC/MCELFObjectWriter.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixupKindInfo.h"
26 #include "llvm/MC/MCMachObjectWriter.h"
27 #include "llvm/MC/MCObjectWriter.h"
28 #include "llvm/MC/MCSectionELF.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/MC/MCValue.h"
32 #include "llvm/Support/ELF.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MachO.h"
35 #include "llvm/Support/TargetParser.h"
36 #include "llvm/Support/raw_ostream.h"
40 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
42 ARMELFObjectWriter(uint8_t OSABI)
43 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
44 /*HasRelocationAddend*/ false) {}
47 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
48 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
49 // This table *must* be in the order that the fixup_* kinds are defined in
52 // Name Offset (bits) Size (bits) Flags
53 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
54 {"fixup_t2_ldst_pcrel_12", 0, 32,
55 MCFixupKindInfo::FKF_IsPCRel |
56 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
57 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
58 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
59 {"fixup_t2_pcrel_10", 0, 32,
60 MCFixupKindInfo::FKF_IsPCRel |
61 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
62 {"fixup_thumb_adr_pcrel_10", 0, 8,
63 MCFixupKindInfo::FKF_IsPCRel |
64 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
65 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
66 {"fixup_t2_adr_pcrel_12", 0, 32,
67 MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
74 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
75 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
76 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
77 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
78 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
79 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
80 {"fixup_arm_thumb_cp", 0, 8,
81 MCFixupKindInfo::FKF_IsPCRel |
82 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
83 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
86 {"fixup_arm_movt_hi16", 0, 20, 0},
87 {"fixup_arm_movw_lo16", 0, 20, 0},
88 {"fixup_t2_movt_hi16", 0, 20, 0},
89 {"fixup_t2_movw_lo16", 0, 20, 0},
91 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
92 // This table *must* be in the order that the fixup_* kinds are defined in
95 // Name Offset (bits) Size (bits) Flags
96 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
97 {"fixup_t2_ldst_pcrel_12", 0, 32,
98 MCFixupKindInfo::FKF_IsPCRel |
99 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
100 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
102 {"fixup_t2_pcrel_10", 0, 32,
103 MCFixupKindInfo::FKF_IsPCRel |
104 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
105 {"fixup_thumb_adr_pcrel_10", 8, 8,
106 MCFixupKindInfo::FKF_IsPCRel |
107 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
108 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
109 {"fixup_t2_adr_pcrel_12", 0, 32,
110 MCFixupKindInfo::FKF_IsPCRel |
111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
112 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
113 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
114 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
115 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
116 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
117 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
118 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
119 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
120 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
121 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
122 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
123 {"fixup_arm_thumb_cp", 8, 8,
124 MCFixupKindInfo::FKF_IsPCRel |
125 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
126 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
127 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
129 {"fixup_arm_movt_hi16", 12, 20, 0},
130 {"fixup_arm_movw_lo16", 12, 20, 0},
131 {"fixup_t2_movt_hi16", 12, 20, 0},
132 {"fixup_t2_movw_lo16", 12, 20, 0},
135 if (Kind < FirstTargetFixupKind)
136 return MCAsmBackend::getFixupKindInfo(Kind);
138 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
140 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
143 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
155 } // end anonymous namespace
157 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
158 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2];
164 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
166 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
168 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
170 return HasThumb2 ? (unsigned)ARM::t2B : Op;
178 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
179 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
184 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
185 const MCRelaxableFragment *DF,
186 const MCAsmLayout &Layout) const {
187 switch ((unsigned)Fixup.getKind()) {
188 case ARM::fixup_arm_thumb_br: {
189 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
190 // low bit being an implied zero. There's an implied +4 offset for the
191 // branch, so we adjust the other way here to determine what's
194 // Relax if the value is too big for a (signed) i8.
195 int64_t Offset = int64_t(Value) - 4;
196 return Offset > 2046 || Offset < -2048;
198 case ARM::fixup_arm_thumb_bcc: {
199 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
200 // low bit being an implied zero. There's an implied +4 offset for the
201 // branch, so we adjust the other way here to determine what's
204 // Relax if the value is too big for a (signed) i8.
205 int64_t Offset = int64_t(Value) - 4;
206 return Offset > 254 || Offset < -256;
208 case ARM::fixup_thumb_adr_pcrel_10:
209 case ARM::fixup_arm_thumb_cp: {
210 // If the immediate is negative, greater than 1020, or not a multiple
211 // of four, the wide version of the instruction must be used.
212 int64_t Offset = int64_t(Value) - 4;
213 return Offset > 1020 || Offset < 0 || Offset & 3;
215 case ARM::fixup_arm_thumb_cb:
216 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
217 // instruction it is is actually out of range for the instruction.
218 // It will be changed to a NOP.
219 int64_t Offset = (Value & ~1);
222 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
225 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
226 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
228 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
229 if (RelaxedOp == Inst.getOpcode()) {
230 SmallString<256> Tmp;
231 raw_svector_ostream OS(Tmp);
232 Inst.dump_pretty(OS);
234 report_fatal_error("unexpected instruction to relax: " + OS.str());
237 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
238 // have to change the operands too.
239 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
240 RelaxedOp == ARM::tHINT) {
241 Res.setOpcode(RelaxedOp);
242 Res.addOperand(MCOperand::createImm(0));
243 Res.addOperand(MCOperand::createImm(14));
244 Res.addOperand(MCOperand::createReg(0));
248 // The rest of instructions we're relaxing have the same operands.
249 // We just need to update to the proper opcode.
251 Res.setOpcode(RelaxedOp);
254 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
255 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
256 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
257 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
258 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
260 const uint16_t nopEncoding =
261 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
262 uint64_t NumNops = Count / 2;
263 for (uint64_t i = 0; i != NumNops; ++i)
264 OW->write16(nopEncoding);
270 const uint32_t nopEncoding =
271 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
272 uint64_t NumNops = Count / 4;
273 for (uint64_t i = 0; i != NumNops; ++i)
274 OW->write32(nopEncoding);
275 // FIXME: should this function return false when unable to write exactly
276 // 'Count' bytes with NOP encodings?
279 break; // No leftover bytes to write
295 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
296 if (IsLittleEndian) {
297 // Note that the halfwords are stored high first and low second in thumb;
298 // so we need to swap the fixup value here to map properly.
299 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
300 Swapped |= (Value & 0x0000FFFF) << 16;
306 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
307 bool IsLittleEndian) {
310 if (IsLittleEndian) {
311 Value = (SecondHalf & 0xFFFF) << 16;
312 Value |= (FirstHalf & 0xFFFF);
314 Value = (SecondHalf & 0xFFFF);
315 Value |= (FirstHalf & 0xFFFF) << 16;
321 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
322 bool IsPCRel, MCContext *Ctx,
323 bool IsLittleEndian) {
324 unsigned Kind = Fixup.getKind();
327 llvm_unreachable("Unknown fixup kind!");
336 case ARM::fixup_arm_movt_hi16:
340 case ARM::fixup_arm_movw_lo16: {
341 unsigned Hi4 = (Value & 0xF000) >> 12;
342 unsigned Lo12 = Value & 0x0FFF;
343 // inst{19-16} = Hi4;
344 // inst{11-0} = Lo12;
345 Value = (Hi4 << 16) | (Lo12);
348 case ARM::fixup_t2_movt_hi16:
352 case ARM::fixup_t2_movw_lo16: {
353 unsigned Hi4 = (Value & 0xF000) >> 12;
354 unsigned i = (Value & 0x800) >> 11;
355 unsigned Mid3 = (Value & 0x700) >> 8;
356 unsigned Lo8 = Value & 0x0FF;
357 // inst{19-16} = Hi4;
359 // inst{14-12} = Mid3;
361 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
362 return swapHalfWords(Value, IsLittleEndian);
364 case ARM::fixup_arm_ldst_pcrel_12:
365 // ARM PC-relative values are offset by 8.
368 case ARM::fixup_t2_ldst_pcrel_12: {
369 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
372 if ((int64_t)Value < 0) {
376 if (Ctx && Value >= 4096)
377 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
378 Value |= isAdd << 23;
380 // Same addressing mode as fixup_arm_pcrel_10,
381 // but with 16-bit halfwords swapped.
382 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
383 return swapHalfWords(Value, IsLittleEndian);
387 case ARM::fixup_thumb_adr_pcrel_10:
388 return ((Value - 4) >> 2) & 0xff;
389 case ARM::fixup_arm_adr_pcrel_12: {
390 // ARM PC-relative values are offset by 8.
392 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
393 if ((int64_t)Value < 0) {
397 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
398 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
399 // Encode the immediate and shift the opcode into place.
400 return ARM_AM::getSOImmVal(Value) | (opc << 21);
403 case ARM::fixup_t2_adr_pcrel_12: {
406 if ((int64_t)Value < 0) {
411 uint32_t out = (opc << 21);
412 out |= (Value & 0x800) << 15;
413 out |= (Value & 0x700) << 4;
414 out |= (Value & 0x0FF);
416 return swapHalfWords(out, IsLittleEndian);
419 case ARM::fixup_arm_condbranch:
420 case ARM::fixup_arm_uncondbranch:
421 case ARM::fixup_arm_uncondbl:
422 case ARM::fixup_arm_condbl:
423 case ARM::fixup_arm_blx:
424 // These values don't encode the low two bits since they're always zero.
425 // Offset by 8 just as above.
426 if (const MCSymbolRefExpr *SRE =
427 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
428 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
430 return 0xffffff & ((Value - 8) >> 2);
431 case ARM::fixup_t2_uncondbranch: {
433 Value >>= 1; // Low bit is not encoded.
436 bool I = Value & 0x800000;
437 bool J1 = Value & 0x400000;
438 bool J2 = Value & 0x200000;
442 out |= I << 26; // S bit
443 out |= !J1 << 13; // J1 bit
444 out |= !J2 << 11; // J2 bit
445 out |= (Value & 0x1FF800) << 5; // imm6 field
446 out |= (Value & 0x0007FF); // imm11 field
448 return swapHalfWords(out, IsLittleEndian);
450 case ARM::fixup_t2_condbranch: {
452 Value >>= 1; // Low bit is not encoded.
455 out |= (Value & 0x80000) << 7; // S bit
456 out |= (Value & 0x40000) >> 7; // J2 bit
457 out |= (Value & 0x20000) >> 4; // J1 bit
458 out |= (Value & 0x1F800) << 5; // imm6 field
459 out |= (Value & 0x007FF); // imm11 field
461 return swapHalfWords(out, IsLittleEndian);
463 case ARM::fixup_arm_thumb_bl: {
464 // The value doesn't encode the low bit (always zero) and is offset by
465 // four. The 32-bit immediate value is encoded as
466 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
467 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
468 // The value is encoded into disjoint bit positions in the destination
469 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
470 // J = either J1 or J2 bit
472 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
474 // Note that the halfwords are stored high first, low second; so we need
475 // to transpose the fixup value here to map properly.
476 uint32_t offset = (Value - 4) >> 1;
477 uint32_t signBit = (offset & 0x800000) >> 23;
478 uint32_t I1Bit = (offset & 0x400000) >> 22;
479 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
480 uint32_t I2Bit = (offset & 0x200000) >> 21;
481 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
482 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
483 uint32_t imm11Bits = (offset & 0x000007FF);
485 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
486 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
487 (uint16_t)imm11Bits);
488 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
490 case ARM::fixup_arm_thumb_blx: {
491 // The value doesn't encode the low two bits (always zero) and is offset by
492 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
493 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
494 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
495 // The value is encoded into disjoint bit positions in the destination
496 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
497 // J = either J1 or J2 bit, 0 = zero.
499 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
501 // Note that the halfwords are stored high first, low second; so we need
502 // to transpose the fixup value here to map properly.
503 uint32_t offset = (Value - 2) >> 2;
504 if (const MCSymbolRefExpr *SRE =
505 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
506 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
508 uint32_t signBit = (offset & 0x400000) >> 22;
509 uint32_t I1Bit = (offset & 0x200000) >> 21;
510 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
511 uint32_t I2Bit = (offset & 0x100000) >> 20;
512 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
513 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
514 uint32_t imm10LBits = (offset & 0x3FF);
516 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
517 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
518 ((uint16_t)imm10LBits) << 1);
519 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
521 case ARM::fixup_arm_thumb_cp:
522 // Offset by 4, and don't encode the low two bits. Two bytes of that
523 // 'off by 4' is implicitly handled by the half-word ordering of the
524 // Thumb encoding, so we only need to adjust by 2 here.
525 return ((Value - 2) >> 2) & 0xff;
526 case ARM::fixup_arm_thumb_cb: {
527 // Offset by 4 and don't encode the lower bit, which is always 0.
528 uint32_t Binary = (Value - 4) >> 1;
529 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
531 case ARM::fixup_arm_thumb_br:
532 // Offset by 4 and don't encode the lower bit, which is always 0.
533 return ((Value - 4) >> 1) & 0x7ff;
534 case ARM::fixup_arm_thumb_bcc:
535 // Offset by 4 and don't encode the lower bit, which is always 0.
536 return ((Value - 4) >> 1) & 0xff;
537 case ARM::fixup_arm_pcrel_10_unscaled: {
538 Value = Value - 8; // ARM fixups offset by an additional word and don't
539 // need to adjust for the half-word ordering.
541 if ((int64_t)Value < 0) {
545 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
546 if (Ctx && Value >= 256)
547 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
548 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
549 return Value | (isAdd << 23);
551 case ARM::fixup_arm_pcrel_10:
552 Value = Value - 4; // ARM fixups offset by an additional word and don't
553 // need to adjust for the half-word ordering.
555 case ARM::fixup_t2_pcrel_10: {
556 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
559 if ((int64_t)Value < 0) {
563 // These values don't encode the low two bits since they're always zero.
565 if (Ctx && Value >= 256)
566 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
567 Value |= isAdd << 23;
569 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
571 if (Kind == ARM::fixup_t2_pcrel_10)
572 return swapHalfWords(Value, IsLittleEndian);
579 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
580 const MCAsmLayout &Layout,
581 const MCFixup &Fixup,
582 const MCFragment *DF,
583 const MCValue &Target, uint64_t &Value,
585 const MCSymbolRefExpr *A = Target.getSymA();
586 // Some fixups to thumb function symbols need the low bit (thumb bit)
588 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
589 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
590 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
591 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
592 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
593 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
595 const MCSymbol &Sym = A->getSymbol();
596 if (Asm.isThumbFunc(&Sym))
600 // For Thumb1 BL instruction, it is possible to be a long jump between
601 // the basic blocks of the same function. Thus, we would like to resolve
602 // the offset when the destination has the same MCFragment.
603 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
604 const MCSymbol &Sym = A->getSymbol();
605 IsResolved = (Sym.getFragment() == DF);
607 // We must always generate a relocation for BL/BLX instructions if we have
608 // a symbol to reference, as the linker relies on knowing the destination
609 // symbol's thumb-ness to get interworking right.
610 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
611 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
612 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
613 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
616 // Try to get the encoded value for the fixup as-if we're mapping it into
617 // the instruction. This allows adjustFixupValue() to issue a diagnostic
618 // if the value aren't invalid.
619 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(),
623 /// getFixupKindNumBytes - The number of bytes the fixup may change.
624 static unsigned getFixupKindNumBytes(unsigned Kind) {
627 llvm_unreachable("Unknown fixup kind!");
630 case ARM::fixup_arm_thumb_bcc:
631 case ARM::fixup_arm_thumb_cp:
632 case ARM::fixup_thumb_adr_pcrel_10:
636 case ARM::fixup_arm_thumb_br:
637 case ARM::fixup_arm_thumb_cb:
640 case ARM::fixup_arm_pcrel_10_unscaled:
641 case ARM::fixup_arm_ldst_pcrel_12:
642 case ARM::fixup_arm_pcrel_10:
643 case ARM::fixup_arm_adr_pcrel_12:
644 case ARM::fixup_arm_uncondbl:
645 case ARM::fixup_arm_condbl:
646 case ARM::fixup_arm_blx:
647 case ARM::fixup_arm_condbranch:
648 case ARM::fixup_arm_uncondbranch:
652 case ARM::fixup_t2_ldst_pcrel_12:
653 case ARM::fixup_t2_condbranch:
654 case ARM::fixup_t2_uncondbranch:
655 case ARM::fixup_t2_pcrel_10:
656 case ARM::fixup_t2_adr_pcrel_12:
657 case ARM::fixup_arm_thumb_bl:
658 case ARM::fixup_arm_thumb_blx:
659 case ARM::fixup_arm_movt_hi16:
660 case ARM::fixup_arm_movw_lo16:
661 case ARM::fixup_t2_movt_hi16:
662 case ARM::fixup_t2_movw_lo16:
672 /// getFixupKindContainerSizeBytes - The number of bytes of the
673 /// container involved in big endian.
674 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
677 llvm_unreachable("Unknown fixup kind!");
686 case ARM::fixup_arm_thumb_bcc:
687 case ARM::fixup_arm_thumb_cp:
688 case ARM::fixup_thumb_adr_pcrel_10:
689 case ARM::fixup_arm_thumb_br:
690 case ARM::fixup_arm_thumb_cb:
691 // Instruction size is 2 bytes.
694 case ARM::fixup_arm_pcrel_10_unscaled:
695 case ARM::fixup_arm_ldst_pcrel_12:
696 case ARM::fixup_arm_pcrel_10:
697 case ARM::fixup_arm_adr_pcrel_12:
698 case ARM::fixup_arm_uncondbl:
699 case ARM::fixup_arm_condbl:
700 case ARM::fixup_arm_blx:
701 case ARM::fixup_arm_condbranch:
702 case ARM::fixup_arm_uncondbranch:
703 case ARM::fixup_t2_ldst_pcrel_12:
704 case ARM::fixup_t2_condbranch:
705 case ARM::fixup_t2_uncondbranch:
706 case ARM::fixup_t2_pcrel_10:
707 case ARM::fixup_t2_adr_pcrel_12:
708 case ARM::fixup_arm_thumb_bl:
709 case ARM::fixup_arm_thumb_blx:
710 case ARM::fixup_arm_movt_hi16:
711 case ARM::fixup_arm_movw_lo16:
712 case ARM::fixup_t2_movt_hi16:
713 case ARM::fixup_t2_movw_lo16:
714 // Instruction size is 4 bytes.
719 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
720 unsigned DataSize, uint64_t Value,
721 bool IsPCRel) const {
722 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
723 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian);
725 return; // Doesn't change encoding.
727 unsigned Offset = Fixup.getOffset();
728 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
730 // Used to point to big endian bytes.
731 unsigned FullSizeBytes;
732 if (!IsLittleEndian) {
733 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
734 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!");
735 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
738 // For each byte of the fragment that the fixup touches, mask in the bits from
739 // the fixup value. The Value has been "split up" into the appropriate
741 for (unsigned i = 0; i != NumBytes; ++i) {
742 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
743 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
747 static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
748 unsigned AK = ARM::parseArch(Arch);
751 return MachO::CPU_SUBTYPE_ARM_V7;
753 return MachO::CPU_SUBTYPE_ARM_V4T;
756 return MachO::CPU_SUBTYPE_ARM_V6;
758 return MachO::CPU_SUBTYPE_ARM_V5;
761 case ARM::AK_ARMV5TE:
762 case ARM::AK_ARMV5TEJ:
763 return MachO::CPU_SUBTYPE_ARM_V5TEJ;
765 return MachO::CPU_SUBTYPE_ARM_V7;
767 return MachO::CPU_SUBTYPE_ARM_V7S;
769 return MachO::CPU_SUBTYPE_ARM_V7K;
771 case ARM::AK_ARMV6SM:
772 return MachO::CPU_SUBTYPE_ARM_V6M;
774 return MachO::CPU_SUBTYPE_ARM_V7M;
775 case ARM::AK_ARMV7EM:
776 return MachO::CPU_SUBTYPE_ARM_V7EM;
780 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
781 const MCRegisterInfo &MRI,
782 const TargetTuple &TT, StringRef CPU,
784 switch (TT.getObjectFormat()) {
786 llvm_unreachable("unsupported object format");
787 case TargetTuple::MachO: {
788 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
789 return new ARMAsmBackendDarwin(T, TT, CS);
791 case TargetTuple::COFF:
792 assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
793 return new ARMAsmBackendWinCOFF(T, TT);
794 case TargetTuple::ELF:
795 assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
796 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
797 return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
801 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
802 const MCRegisterInfo &MRI,
803 const TargetTuple &TT,
805 return createARMAsmBackend(T, MRI, TT, CPU, true);
808 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
809 const MCRegisterInfo &MRI,
810 const TargetTuple &TT,
812 return createARMAsmBackend(T, MRI, TT, CPU, false);
815 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
816 const MCRegisterInfo &MRI,
817 const TargetTuple &TT,
819 return createARMAsmBackend(T, MRI, TT, CPU, true);
822 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
823 const MCRegisterInfo &MRI,
824 const TargetTuple &TT,
826 return createARMAsmBackend(T, MRI, TT, CPU, false);