1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
20 #include "ARMMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
25 // Enums corresponding to ARM condition codes
27 // The CondCodes constants map directly to the 4-bit encoding of the
28 // condition field for predicated instructions.
29 enum CondCodes { // Meaning (integer) Meaning (floating-point)
31 NE, // Not equal Not equal, or unordered
32 HS, // Carry set >, ==, or unordered
33 LO, // Carry clear Less than
34 MI, // Minus, negative Less than
35 PL, // Plus, positive or zero >, ==, or unordered
36 VS, // Overflow Unordered
37 VC, // No overflow Not unordered
38 HI, // Unsigned higher Greater than, or unordered
39 LS, // Unsigned lower or same Less than or equal
40 GE, // Greater than or equal Greater than or equal
41 LT, // Less than Less than, or unordered
42 GT, // Greater than Greater than
43 LE, // Less than or equal <, ==, or unordered
44 AL // Always (unconditional) Always (unconditional)
47 inline static CondCodes getOppositeCondition(CondCodes CC) {
49 default: llvm_unreachable("Unknown condition code");
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
70 default: llvm_unreachable("Unknown condition code");
71 case ARMCC::EQ: return "eq";
72 case ARMCC::NE: return "ne";
73 case ARMCC::HS: return "hs";
74 case ARMCC::LO: return "lo";
75 case ARMCC::MI: return "mi";
76 case ARMCC::PL: return "pl";
77 case ARMCC::VS: return "vs";
78 case ARMCC::VC: return "vc";
79 case ARMCC::HI: return "hi";
80 case ARMCC::LS: return "ls";
81 case ARMCC::GE: return "ge";
82 case ARMCC::LT: return "lt";
83 case ARMCC::GT: return "gt";
84 case ARMCC::LE: return "le";
85 case ARMCC::AL: return "al";
101 inline static const char *IFlagsToString(unsigned val) {
103 default: llvm_unreachable("Unknown iflags operand");
110 inline static const char *IModToString(unsigned val) {
112 default: llvm_unreachable("Unknown imod operand");
113 case IE: return "ie";
114 case ID: return "id";
120 // The Memory Barrier Option constants map directly to the 4-bit encoding of
121 // the option field for memory barrier operations.
133 inline static const char *MemBOptToString(unsigned val) {
135 default: llvm_unreachable("Unknown memory operation");
136 case SY: return "sy";
137 case ST: return "st";
138 case ISH: return "ish";
139 case ISHST: return "ishst";
140 case NSH: return "nsh";
141 case NSHST: return "nshst";
142 case OSH: return "osh";
143 case OSHST: return "oshst";
146 } // namespace ARM_MB
148 /// getARMRegisterNumbering - Given the enum value for some register, e.g.
149 /// ARM::LR, return the number that it corresponds to (e.g. 14).
150 inline static unsigned getARMRegisterNumbering(unsigned Reg) {
154 llvm_unreachable("Unknown ARM register!");
155 case R0: case S0: case D0: case Q0: return 0;
156 case R1: case S1: case D1: case Q1: return 1;
157 case R2: case S2: case D2: case Q2: return 2;
158 case R3: case S3: case D3: case Q3: return 3;
159 case R4: case S4: case D4: case Q4: return 4;
160 case R5: case S5: case D5: case Q5: return 5;
161 case R6: case S6: case D6: case Q6: return 6;
162 case R7: case S7: case D7: case Q7: return 7;
163 case R8: case S8: case D8: case Q8: return 8;
164 case R9: case S9: case D9: case Q9: return 9;
165 case R10: case S10: case D10: case Q10: return 10;
166 case R11: case S11: case D11: case Q11: return 11;
167 case R12: case S12: case D12: case Q12: return 12;
168 case SP: case S13: case D13: case Q13: return 13;
169 case LR: case S14: case D14: case Q14: return 14;
170 case PC: case S15: case D15: case Q15: return 15;
172 case S16: case D16: return 16;
173 case S17: case D17: return 17;
174 case S18: case D18: return 18;
175 case S19: case D19: return 19;
176 case S20: case D20: return 20;
177 case S21: case D21: return 21;
178 case S22: case D22: return 22;
179 case S23: case D23: return 23;
180 case S24: case D24: return 24;
181 case S25: case D25: return 25;
182 case S26: case D26: return 26;
183 case S27: case D27: return 27;
184 case S28: case D28: return 28;
185 case S29: case D29: return 29;
186 case S30: case D30: return 30;
187 case S31: case D31: return 31;
191 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
193 static inline bool isARMLowRegister(unsigned Reg) {
196 case R0: case R1: case R2: case R3:
197 case R4: case R5: case R6: case R7:
204 /// ARMII - This namespace holds all of the target specific flags that
205 /// instruction info tracks.
217 /// ARM Addressing Modes
229 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
233 AddrModeT2_pc = 14, // +/- i12 for pc relative data
234 AddrModeT2_i8s4 = 15, // i8 * 4
238 inline static const char *AddrModeToString(AddrMode addrmode) {
240 case AddrModeNone: return "AddrModeNone";
241 case AddrMode1: return "AddrMode1";
242 case AddrMode2: return "AddrMode2";
243 case AddrMode3: return "AddrMode3";
244 case AddrMode4: return "AddrMode4";
245 case AddrMode5: return "AddrMode5";
246 case AddrMode6: return "AddrMode6";
247 case AddrModeT1_1: return "AddrModeT1_1";
248 case AddrModeT1_2: return "AddrModeT1_2";
249 case AddrModeT1_4: return "AddrModeT1_4";
250 case AddrModeT1_s: return "AddrModeT1_s";
251 case AddrModeT2_i12: return "AddrModeT2_i12";
252 case AddrModeT2_i8: return "AddrModeT2_i8";
253 case AddrModeT2_so: return "AddrModeT2_so";
254 case AddrModeT2_pc: return "AddrModeT2_pc";
255 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
256 case AddrMode_i12: return "AddrMode_i12";
260 /// Target Operand Flag enum.
262 //===------------------------------------------------------------------===//
263 // ARM Specific MachineOperand flags.
267 /// MO_LO16 - On a symbol operand, this represents a relocation containing
268 /// lower 16 bit of the address. Used only via movw instruction.
271 /// MO_HI16 - On a symbol operand, this represents a relocation containing
272 /// higher 16 bit of the address. Used only via movt instruction.
275 /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
276 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
277 /// i.e. "FOO$non_lazy_ptr".
278 /// Used only via movw instruction.
281 /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
282 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
283 /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
286 /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
287 /// relocation containing lower 16 bit of the PC relative address of the
288 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
289 /// Used only via movw instruction.
292 /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
293 /// relocation containing lower 16 bit of the PC relative address of the
294 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
295 /// Used only via movt instruction.
298 /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
304 //===------------------------------------------------------------------===//
305 // Instruction Flags.
307 //===------------------------------------------------------------------===//
308 // This four-bit field describes the addressing mode used.
309 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
311 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
312 // and store ops only. Generic "updating" flag is used for ld/st multiple.
313 // The index mode enums are declared in ARMBaseInfo.h
315 IndexModeMask = 3 << IndexModeShift,
317 //===------------------------------------------------------------------===//
318 // Instruction encoding formats.
321 FormMask = 0x3f << FormShift,
323 // Pseudo instructions
324 Pseudo = 0 << FormShift,
326 // Multiply instructions
327 MulFrm = 1 << FormShift,
329 // Branch instructions
330 BrFrm = 2 << FormShift,
331 BrMiscFrm = 3 << FormShift,
333 // Data Processing instructions
334 DPFrm = 4 << FormShift,
335 DPSoRegFrm = 5 << FormShift,
338 LdFrm = 6 << FormShift,
339 StFrm = 7 << FormShift,
340 LdMiscFrm = 8 << FormShift,
341 StMiscFrm = 9 << FormShift,
342 LdStMulFrm = 10 << FormShift,
344 LdStExFrm = 11 << FormShift,
346 // Miscellaneous arithmetic instructions
347 ArithMiscFrm = 12 << FormShift,
348 SatFrm = 13 << FormShift,
350 // Extend instructions
351 ExtFrm = 14 << FormShift,
354 VFPUnaryFrm = 15 << FormShift,
355 VFPBinaryFrm = 16 << FormShift,
356 VFPConv1Frm = 17 << FormShift,
357 VFPConv2Frm = 18 << FormShift,
358 VFPConv3Frm = 19 << FormShift,
359 VFPConv4Frm = 20 << FormShift,
360 VFPConv5Frm = 21 << FormShift,
361 VFPLdStFrm = 22 << FormShift,
362 VFPLdStMulFrm = 23 << FormShift,
363 VFPMiscFrm = 24 << FormShift,
366 ThumbFrm = 25 << FormShift,
368 // Miscelleaneous format
369 MiscFrm = 26 << FormShift,
372 NGetLnFrm = 27 << FormShift,
373 NSetLnFrm = 28 << FormShift,
374 NDupFrm = 29 << FormShift,
375 NLdStFrm = 30 << FormShift,
376 N1RegModImmFrm= 31 << FormShift,
377 N2RegFrm = 32 << FormShift,
378 NVCVTFrm = 33 << FormShift,
379 NVDupLnFrm = 34 << FormShift,
380 N2RegVShLFrm = 35 << FormShift,
381 N2RegVShRFrm = 36 << FormShift,
382 N3RegFrm = 37 << FormShift,
383 N3RegVShFrm = 38 << FormShift,
384 NVExtFrm = 39 << FormShift,
385 NVMulSLFrm = 40 << FormShift,
386 NVTBLFrm = 41 << FormShift,
388 //===------------------------------------------------------------------===//
391 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
392 // it doesn't have a Rn operand.
395 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
396 // a 16-bit Thumb instruction if certain conditions are met.
397 Xform16Bit = 1 << 14,
399 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
400 // instruction. Used by the parser to determine whether to require the 'S'
401 // suffix on the mnemonic (when not in an IT block) or preclude it (when
403 ThumbArithFlagSetting = 1 << 18,
405 //===------------------------------------------------------------------===//
408 DomainMask = 7 << DomainShift,
409 DomainGeneral = 0 << DomainShift,
410 DomainVFP = 1 << DomainShift,
411 DomainNEON = 2 << DomainShift,
412 DomainNEONA8 = 4 << DomainShift,
414 //===------------------------------------------------------------------===//
415 // Field shifts - such shifts are used to set field while generating
416 // machine instructions.
418 // FIXME: This list will need adjusting/fixing as the MC code emitter
419 // takes shape and the ARMCodeEmitter.cpp bits go away.
444 } // end namespace ARMII
446 } // end namespace llvm;