1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
11 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
13 #include "llvm/MC/MCFixup.h"
18 // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
20 fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
22 // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
23 // the 16-bit halfwords reordered.
24 fixup_t2_ldst_pcrel_12,
26 // fixup_arm_pcrel_10_unscaled - 10-bit PC relative relocation for symbol
27 // addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
28 fixup_arm_pcrel_10_unscaled,
29 // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
30 // used in VFP instructions where the lower 2 bits are not encoded
31 // (so it's encoded as an 8-bit immediate).
33 // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
34 // the short-swapped encoding of Thumb2 instructions.
36 // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
37 // addresses where the lower 2 bits are not encoded (so it's encoded as an
39 fixup_thumb_adr_pcrel_10,
40 // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
42 fixup_arm_adr_pcrel_12,
43 // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
45 fixup_t2_adr_pcrel_12,
46 // fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
49 // fixup_arm_uncondbranch - 24-bit PC relative relocation for
50 // branch instructions. (unconditional)
51 fixup_arm_uncondbranch,
52 // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
53 // uconditional branch instructions.
55 // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
56 // branch unconditional branch instructions.
57 fixup_t2_uncondbranch,
59 // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
62 // The following fixups handle the ARM BL instructions. These can be
63 // conditionalised; however, the ARM ELF ABI requires a different relocation
64 // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
65 // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
66 // no conditional version; R_ARM_JUMP24 would have to insert a veneer.
68 // MachO does not draw a distinction between the two cases, so it will treat
69 // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
71 // fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions.
74 // fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial
75 // conditionalisation.
78 // fixup_arm_blx - Fixup for ARM BLX instructions.
81 // fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
84 // fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
87 // fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
90 // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
93 // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
96 // The next two are for the movt/movw pair
97 // the 16bit imm field are split into imm{15-12} and imm{11-0}
98 fixup_arm_movt_hi16, // :upper16:
99 fixup_arm_movw_lo16, // :lower16:
100 fixup_t2_movt_hi16, // :upper16:
101 fixup_t2_movw_lo16, // :lower16:
105 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind