1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/ADT/APFloat.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/raw_ostream.h"
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
34 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
37 class ARMMCCodeEmitter : public MCCodeEmitter {
38 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
40 const MCInstrInfo &MCII;
41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
50 ~ARMMCCodeEmitter() {}
52 bool isThumb() const {
53 // FIXME: Can tablegen auto-generate this?
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2() const {
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetDarwin() const {
60 Triple TT(STI.getTargetTriple());
61 Triple::OSType OS = TT.getOS();
62 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
65 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
67 // getBinaryCodeForInstr - TableGen'erated function for getting the
68 // binary encoding for an instruction.
69 uint64_t getBinaryCodeForInstr(const MCInst &MI,
70 SmallVectorImpl<MCFixup> &Fixups) const;
72 /// getMachineOpValue - Return binary encoding of operand. If the machine
73 /// operand requires relocation, record the relocation and return zero.
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
78 /// the specified operand. This is used for operands with :lower16: and
79 /// :upper16: prefixes.
80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 SmallVectorImpl<MCFixup> &Fixups) const;
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
84 unsigned &Reg, unsigned &Imm,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
93 /// BLX branch target.
94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 SmallVectorImpl<MCFixup> &Fixups) const;
97 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups) const;
101 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 SmallVectorImpl<MCFixup> &Fixups) const;
105 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups) const;
109 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const;
114 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
115 /// immediate Thumb2 direct branch target.
116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
117 SmallVectorImpl<MCFixup> &Fixups) const;
119 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
123 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
125 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups) const;
128 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
129 /// ADR label target.
130 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
132 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
134 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
138 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
140 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
144 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
145 SmallVectorImpl<MCFixup> &Fixups)const;
147 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
149 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups) const;
152 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
154 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
159 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
160 SmallVectorImpl<MCFixup> &Fixups) const;
163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
164 /// operand as needed by load/store instructions.
165 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
169 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
170 SmallVectorImpl<MCFixup> &Fixups) const {
171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
173 default: llvm_unreachable("Unknown addressing sub-mode!");
174 case ARM_AM::da: return 0;
175 case ARM_AM::ia: return 1;
176 case ARM_AM::db: return 2;
177 case ARM_AM::ib: return 3;
180 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
182 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
184 case ARM_AM::no_shift:
185 case ARM_AM::lsl: return 0;
186 case ARM_AM::lsr: return 1;
187 case ARM_AM::asr: return 2;
189 case ARM_AM::rrx: return 3;
191 llvm_unreachable("Invalid ShiftOpc!");
194 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
195 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
196 SmallVectorImpl<MCFixup> &Fixups) const;
198 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
199 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
200 SmallVectorImpl<MCFixup> &Fixups) const;
202 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
203 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
204 SmallVectorImpl<MCFixup> &Fixups) const;
206 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
207 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups) const;
210 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
211 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
212 SmallVectorImpl<MCFixup> &Fixups) const;
214 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
216 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
217 SmallVectorImpl<MCFixup> &Fixups) const;
219 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
220 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups) const;
223 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
224 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
225 SmallVectorImpl<MCFixup> &Fixups) const;
227 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
228 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups) const;
231 /// getCCOutOpValue - Return encoding of the 's' bit.
232 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
233 SmallVectorImpl<MCFixup> &Fixups) const {
234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
236 return MI.getOperand(Op).getReg() == ARM::CPSR;
239 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
240 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
241 SmallVectorImpl<MCFixup> &Fixups) const {
242 unsigned SoImm = MI.getOperand(Op).getImm();
243 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
244 assert(SoImmVal != -1 && "Not a valid so_imm value!");
246 // Encode rotate_imm.
247 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
248 << ARMII::SoRotImmShift;
251 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
255 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
256 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const {
258 unsigned SoImm = MI.getOperand(Op).getImm();
259 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
260 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
265 SmallVectorImpl<MCFixup> &Fixups) const;
266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
267 SmallVectorImpl<MCFixup> &Fixups) const;
268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
269 SmallVectorImpl<MCFixup> &Fixups) const;
270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
271 SmallVectorImpl<MCFixup> &Fixups) const;
273 /// getSORegOpValue - Return an encoded so_reg shifted register value.
274 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const;
281 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
282 SmallVectorImpl<MCFixup> &Fixups) const {
283 return 64 - MI.getOperand(Op).getImm();
286 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
291 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
294 SmallVectorImpl<MCFixup> &Fixups) const;
295 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
297 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
298 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
306 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups) const;
309 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
310 SmallVectorImpl<MCFixup> &Fixups) const;
312 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
314 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
316 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
317 unsigned EncodedValue) const;
319 unsigned VFPThumb2PostEncoder(const MCInst &MI,
320 unsigned EncodedValue) const;
322 void EmitByte(unsigned char C, raw_ostream &OS) const {
326 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
327 // Output the constant in little endian byte order.
328 for (unsigned i = 0; i != Size; ++i) {
329 EmitByte(Val & 255, OS);
334 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
335 SmallVectorImpl<MCFixup> &Fixups) const;
338 } // end anonymous namespace
340 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
341 const MCRegisterInfo &MRI,
342 const MCSubtargetInfo &STI,
344 return new ARMMCCodeEmitter(MCII, STI, Ctx);
347 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
348 /// instructions, and rewrite them to their Thumb2 form if we are currently in
350 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
351 unsigned EncodedValue) const {
353 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
354 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
356 unsigned Bit24 = EncodedValue & 0x01000000;
357 unsigned Bit28 = Bit24 << 4;
358 EncodedValue &= 0xEFFFFFFF;
359 EncodedValue |= Bit28;
360 EncodedValue |= 0x0F000000;
366 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
367 /// instructions, and rewrite them to their Thumb2 form if we are currently in
369 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
370 unsigned EncodedValue) const {
372 EncodedValue &= 0xF0FFFFFF;
373 EncodedValue |= 0x09000000;
379 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
380 /// instructions, and rewrite them to their Thumb2 form if we are currently in
382 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
383 unsigned EncodedValue) const {
385 EncodedValue &= 0x00FFFFFF;
386 EncodedValue |= 0xEE000000;
392 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
393 /// them to their Thumb2 form if we are currently in Thumb2 mode.
394 unsigned ARMMCCodeEmitter::
395 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
397 EncodedValue &= 0x0FFFFFFF;
398 EncodedValue |= 0xE0000000;
403 /// getMachineOpValue - Return binary encoding of operand. If the machine
404 /// operand requires relocation, record the relocation and return zero.
405 unsigned ARMMCCodeEmitter::
406 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
407 SmallVectorImpl<MCFixup> &Fixups) const {
409 unsigned Reg = MO.getReg();
410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
412 // Q registers are encoded as 2x their register number.
416 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
417 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
418 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
419 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
422 } else if (MO.isImm()) {
423 return static_cast<unsigned>(MO.getImm());
424 } else if (MO.isFPImm()) {
425 return static_cast<unsigned>(APFloat(MO.getFPImm())
426 .bitcastToAPInt().getHiBits(32).getLimitedValue());
429 llvm_unreachable("Unable to encode MCOperand!");
432 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
433 bool ARMMCCodeEmitter::
434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
436 const MCOperand &MO = MI.getOperand(OpIdx);
437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
439 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
441 int32_t SImm = MO1.getImm();
444 // Special value for #-0
445 if (SImm == INT32_MIN) {
450 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
460 /// getBranchTargetOpValue - Helper function to get the branch target operand,
461 /// which is either an immediate or requires a fixup.
462 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
464 SmallVectorImpl<MCFixup> &Fixups) {
465 const MCOperand &MO = MI.getOperand(OpIdx);
467 // If the destination is an immediate, we have nothing to do.
468 if (MO.isImm()) return MO.getImm();
469 assert(MO.isExpr() && "Unexpected branch target type!");
470 const MCExpr *Expr = MO.getExpr();
471 MCFixupKind Kind = MCFixupKind(FixupKind);
472 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
474 // All of the information is in the fixup.
478 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
479 // determined by negating them and XOR'ing them with bit 23.
480 static int32_t encodeThumbBLOffset(int32_t offset) {
482 uint32_t S = (offset & 0x800000) >> 23;
483 uint32_t J1 = (offset & 0x400000) >> 22;
484 uint32_t J2 = (offset & 0x200000) >> 21;
497 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
498 uint32_t ARMMCCodeEmitter::
499 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
500 SmallVectorImpl<MCFixup> &Fixups) const {
501 const MCOperand MO = MI.getOperand(OpIdx);
503 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
505 return encodeThumbBLOffset(MO.getImm());
508 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
509 /// BLX branch target.
510 uint32_t ARMMCCodeEmitter::
511 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
512 SmallVectorImpl<MCFixup> &Fixups) const {
513 const MCOperand MO = MI.getOperand(OpIdx);
515 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
517 return encodeThumbBLOffset(MO.getImm());
520 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
521 uint32_t ARMMCCodeEmitter::
522 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups) const {
524 const MCOperand MO = MI.getOperand(OpIdx);
526 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
528 return (MO.getImm() >> 1);
531 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
532 uint32_t ARMMCCodeEmitter::
533 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
534 SmallVectorImpl<MCFixup> &Fixups) const {
535 const MCOperand MO = MI.getOperand(OpIdx);
537 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
539 return (MO.getImm() >> 1);
542 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
543 uint32_t ARMMCCodeEmitter::
544 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
545 SmallVectorImpl<MCFixup> &Fixups) const {
546 const MCOperand MO = MI.getOperand(OpIdx);
548 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
549 return (MO.getImm() >> 1);
552 /// Return true if this branch has a non-always predication
553 static bool HasConditionalBranch(const MCInst &MI) {
554 int NumOp = MI.getNumOperands();
556 for (int i = 0; i < NumOp-1; ++i) {
557 const MCOperand &MCOp1 = MI.getOperand(i);
558 const MCOperand &MCOp2 = MI.getOperand(i + 1);
559 if (MCOp1.isImm() && MCOp2.isReg() &&
560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
561 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
569 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
571 uint32_t ARMMCCodeEmitter::
572 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
573 SmallVectorImpl<MCFixup> &Fixups) const {
574 // FIXME: This really, really shouldn't use TargetMachine. We don't want
575 // coupling between MC and TM anywhere we can help it.
578 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
579 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
582 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
584 uint32_t ARMMCCodeEmitter::
585 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
586 SmallVectorImpl<MCFixup> &Fixups) const {
587 const MCOperand MO = MI.getOperand(OpIdx);
589 if (HasConditionalBranch(MI))
590 return ::getBranchTargetOpValue(MI, OpIdx,
591 ARM::fixup_arm_condbranch, Fixups);
592 return ::getBranchTargetOpValue(MI, OpIdx,
593 ARM::fixup_arm_uncondbranch, Fixups);
596 return MO.getImm() >> 2;
599 uint32_t ARMMCCodeEmitter::
600 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
601 SmallVectorImpl<MCFixup> &Fixups) const {
602 const MCOperand MO = MI.getOperand(OpIdx);
604 if (HasConditionalBranch(MI))
605 return ::getBranchTargetOpValue(MI, OpIdx,
606 ARM::fixup_arm_condbl, Fixups);
607 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
610 return MO.getImm() >> 2;
613 uint32_t ARMMCCodeEmitter::
614 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
615 SmallVectorImpl<MCFixup> &Fixups) const {
616 const MCOperand MO = MI.getOperand(OpIdx);
618 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
620 return MO.getImm() >> 1;
623 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
624 /// immediate branch target.
625 uint32_t ARMMCCodeEmitter::
626 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
627 SmallVectorImpl<MCFixup> &Fixups) const {
629 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
630 bool I = (Val & 0x800000);
631 bool J1 = (Val & 0x400000);
632 bool J2 = (Val & 0x200000);
646 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
647 /// ADR label target.
648 uint32_t ARMMCCodeEmitter::
649 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
650 SmallVectorImpl<MCFixup> &Fixups) const {
651 const MCOperand MO = MI.getOperand(OpIdx);
653 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
655 int32_t offset = MO.getImm();
656 uint32_t Val = 0x2000;
658 if (offset == INT32_MIN) {
661 } else if (offset < 0) {
666 int SoImmVal = ARM_AM::getSOImmVal(offset);
667 assert(SoImmVal != -1 && "Not a valid so_imm value!");
673 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
675 uint32_t ARMMCCodeEmitter::
676 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
677 SmallVectorImpl<MCFixup> &Fixups) const {
678 const MCOperand MO = MI.getOperand(OpIdx);
680 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
682 int32_t Val = MO.getImm();
683 if (Val == INT32_MIN)
692 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
694 uint32_t ARMMCCodeEmitter::
695 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
696 SmallVectorImpl<MCFixup> &Fixups) const {
697 const MCOperand MO = MI.getOperand(OpIdx);
699 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
704 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
706 uint32_t ARMMCCodeEmitter::
707 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
708 SmallVectorImpl<MCFixup> &) const {
712 const MCOperand &MO1 = MI.getOperand(OpIdx);
713 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
714 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
715 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
716 return (Rm << 3) | Rn;
719 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
720 uint32_t ARMMCCodeEmitter::
721 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
722 SmallVectorImpl<MCFixup> &Fixups) const {
724 // {12} = (U)nsigned (add == '1', sub == '0')
728 // If The first operand isn't a register, we have a label reference.
729 const MCOperand &MO = MI.getOperand(OpIdx);
731 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
733 isAdd = false ; // 'U' bit is set as part of the fixup.
736 const MCExpr *Expr = MO.getExpr();
740 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
742 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
743 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
745 ++MCNumCPRelocations;
748 int32_t Offset = MO.getImm();
749 // FIXME: Handle #-0.
757 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
759 uint32_t Binary = Imm12 & 0xfff;
760 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
763 Binary |= (Reg << 13);
767 /// getT2Imm8s4OpValue - Return encoding info for
768 /// '+/- imm8<<2' operand.
769 uint32_t ARMMCCodeEmitter::
770 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
771 SmallVectorImpl<MCFixup> &Fixups) const {
772 // FIXME: The immediate operand should have already been encoded like this
773 // before ever getting here. The encoder method should just need to combine
774 // the MI operands for the register and the offset into a single
775 // representation for the complex operand in the .td file. This isn't just
776 // style, unfortunately. As-is, we can't represent the distinct encoding
779 // {8} = (U)nsigned (add == '1', sub == '0')
781 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
782 bool isAdd = Imm8 >= 0;
784 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
786 Imm8 = -(uint32_t)Imm8;
791 uint32_t Binary = Imm8 & 0xff;
792 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
798 /// getT2AddrModeImm8s4OpValue - Return encoding info for
799 /// 'reg +/- imm8<<2' operand.
800 uint32_t ARMMCCodeEmitter::
801 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
802 SmallVectorImpl<MCFixup> &Fixups) const {
804 // {8} = (U)nsigned (add == '1', sub == '0')
808 // If The first operand isn't a register, we have a label reference.
809 const MCOperand &MO = MI.getOperand(OpIdx);
811 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
813 isAdd = false ; // 'U' bit is set as part of the fixup.
815 assert(MO.isExpr() && "Unexpected machine operand type!");
816 const MCExpr *Expr = MO.getExpr();
817 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
818 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
820 ++MCNumCPRelocations;
822 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
824 // FIXME: The immediate operand should have already been encoded like this
825 // before ever getting here. The encoder method should just need to combine
826 // the MI operands for the register and the offset into a single
827 // representation for the complex operand in the .td file. This isn't just
828 // style, unfortunately. As-is, we can't represent the distinct encoding
830 uint32_t Binary = (Imm8 >> 2) & 0xff;
831 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
834 Binary |= (Reg << 9);
838 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
839 /// 'reg + imm8<<2' operand.
840 uint32_t ARMMCCodeEmitter::
841 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
842 SmallVectorImpl<MCFixup> &Fixups) const {
845 const MCOperand &MO = MI.getOperand(OpIdx);
846 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
847 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
848 unsigned Imm8 = MO1.getImm();
849 return (Reg << 8) | Imm8;
852 // FIXME: This routine assumes that a binary
853 // expression will always result in a PCRel expression
854 // In reality, its only true if one or more subexpressions
855 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
856 // but this is good enough for now.
857 static bool EvaluateAsPCRel(const MCExpr *Expr) {
858 switch (Expr->getKind()) {
859 default: llvm_unreachable("Unexpected expression type");
860 case MCExpr::SymbolRef: return false;
861 case MCExpr::Binary: return true;
866 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
867 SmallVectorImpl<MCFixup> &Fixups) const {
868 // {20-16} = imm{15-12}
869 // {11-0} = imm{11-0}
870 const MCOperand &MO = MI.getOperand(OpIdx);
872 // Hi / lo 16 bits already extracted during earlier passes.
873 return static_cast<unsigned>(MO.getImm());
875 // Handle :upper16: and :lower16: assembly prefixes.
876 const MCExpr *E = MO.getExpr();
878 if (E->getKind() == MCExpr::Target) {
879 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
880 E = ARM16Expr->getSubExpr();
882 switch (ARM16Expr->getKind()) {
883 default: llvm_unreachable("Unsupported ARMFixup");
884 case ARMMCExpr::VK_ARM_HI16:
885 if (!isTargetDarwin() && EvaluateAsPCRel(E))
886 Kind = MCFixupKind(isThumb2()
887 ? ARM::fixup_t2_movt_hi16_pcrel
888 : ARM::fixup_arm_movt_hi16_pcrel);
890 Kind = MCFixupKind(isThumb2()
891 ? ARM::fixup_t2_movt_hi16
892 : ARM::fixup_arm_movt_hi16);
894 case ARMMCExpr::VK_ARM_LO16:
895 if (!isTargetDarwin() && EvaluateAsPCRel(E))
896 Kind = MCFixupKind(isThumb2()
897 ? ARM::fixup_t2_movw_lo16_pcrel
898 : ARM::fixup_arm_movw_lo16_pcrel);
900 Kind = MCFixupKind(isThumb2()
901 ? ARM::fixup_t2_movw_lo16
902 : ARM::fixup_arm_movw_lo16);
905 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
908 // If the expression doesn't have :upper16: or :lower16: on it,
909 // it's just a plain immediate expression, and those evaluate to
910 // the lower 16 bits of the expression regardless of whether
911 // we have a movt or a movw.
912 if (!isTargetDarwin() && EvaluateAsPCRel(E))
913 Kind = MCFixupKind(isThumb2()
914 ? ARM::fixup_t2_movw_lo16_pcrel
915 : ARM::fixup_arm_movw_lo16_pcrel);
917 Kind = MCFixupKind(isThumb2()
918 ? ARM::fixup_t2_movw_lo16
919 : ARM::fixup_arm_movw_lo16);
920 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
924 uint32_t ARMMCCodeEmitter::
925 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
926 SmallVectorImpl<MCFixup> &Fixups) const {
927 const MCOperand &MO = MI.getOperand(OpIdx);
928 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
929 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
930 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
931 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
932 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
933 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
934 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
935 unsigned SBits = getShiftOp(ShOp);
944 uint32_t Binary = Rm;
946 Binary |= SBits << 5;
947 Binary |= ShImm << 7;
953 uint32_t ARMMCCodeEmitter::
954 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
955 SmallVectorImpl<MCFixup> &Fixups) const {
957 // {13} 1 == imm12, 0 == Rm
960 const MCOperand &MO = MI.getOperand(OpIdx);
961 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
962 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
967 uint32_t ARMMCCodeEmitter::
968 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
969 SmallVectorImpl<MCFixup> &Fixups) const {
970 // {13} 1 == imm12, 0 == Rm
973 const MCOperand &MO = MI.getOperand(OpIdx);
974 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
975 unsigned Imm = MO1.getImm();
976 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
977 bool isReg = MO.getReg() != 0;
978 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
979 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
981 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
982 Binary <<= 7; // Shift amount is bits [11:7]
983 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
984 Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
986 return Binary | (isAdd << 12) | (isReg << 13);
989 uint32_t ARMMCCodeEmitter::
990 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
991 SmallVectorImpl<MCFixup> &Fixups) const {
994 const MCOperand &MO = MI.getOperand(OpIdx);
995 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
996 bool isAdd = MO1.getImm() != 0;
997 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
1000 uint32_t ARMMCCodeEmitter::
1001 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1002 SmallVectorImpl<MCFixup> &Fixups) const {
1003 // {9} 1 == imm8, 0 == Rm
1005 // {7-4} imm7_4/zero
1007 const MCOperand &MO = MI.getOperand(OpIdx);
1008 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1009 unsigned Imm = MO1.getImm();
1010 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1011 bool isImm = MO.getReg() == 0;
1012 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1013 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1015 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1016 return Imm8 | (isAdd << 8) | (isImm << 9);
1019 uint32_t ARMMCCodeEmitter::
1020 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1021 SmallVectorImpl<MCFixup> &Fixups) const {
1022 // {13} 1 == imm8, 0 == Rm
1025 // {7-4} imm7_4/zero
1027 const MCOperand &MO = MI.getOperand(OpIdx);
1028 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1029 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1031 // If The first operand isn't a register, we have a label reference.
1033 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
1035 assert(MO.isExpr() && "Unexpected machine operand type!");
1036 const MCExpr *Expr = MO.getExpr();
1037 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1038 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1040 ++MCNumCPRelocations;
1041 return (Rn << 9) | (1 << 13);
1043 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1044 unsigned Imm = MO2.getImm();
1045 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1046 bool isImm = MO1.getReg() == 0;
1047 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1048 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1050 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1051 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1054 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1055 uint32_t ARMMCCodeEmitter::
1056 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1057 SmallVectorImpl<MCFixup> &Fixups) const {
1060 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1061 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1062 "Unexpected base register!");
1064 // The immediate is already shifted for the implicit zeroes, so no change
1066 return MO1.getImm() & 0xff;
1069 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1070 uint32_t ARMMCCodeEmitter::
1071 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1072 SmallVectorImpl<MCFixup> &Fixups) const {
1076 const MCOperand &MO = MI.getOperand(OpIdx);
1077 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1078 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1079 unsigned Imm5 = MO1.getImm();
1080 return ((Imm5 & 0x1f) << 3) | Rn;
1083 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1084 uint32_t ARMMCCodeEmitter::
1085 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1086 SmallVectorImpl<MCFixup> &Fixups) const {
1087 const MCOperand MO = MI.getOperand(OpIdx);
1089 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1090 return (MO.getImm() >> 2);
1093 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1094 uint32_t ARMMCCodeEmitter::
1095 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1096 SmallVectorImpl<MCFixup> &Fixups) const {
1098 // {8} = (U)nsigned (add == '1', sub == '0')
1102 // If The first operand isn't a register, we have a label reference.
1103 const MCOperand &MO = MI.getOperand(OpIdx);
1105 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
1107 isAdd = false; // 'U' bit is handled as part of the fixup.
1109 assert(MO.isExpr() && "Unexpected machine operand type!");
1110 const MCExpr *Expr = MO.getExpr();
1113 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1115 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1116 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1118 ++MCNumCPRelocations;
1120 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1121 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1124 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1125 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1128 Binary |= (Reg << 9);
1132 unsigned ARMMCCodeEmitter::
1133 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1134 SmallVectorImpl<MCFixup> &Fixups) const {
1135 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1136 // shifted. The second is Rs, the amount to shift by, and the third specifies
1137 // the type of the shift.
1145 const MCOperand &MO = MI.getOperand(OpIdx);
1146 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1147 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1148 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1151 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1153 // Encode the shift opcode.
1155 unsigned Rs = MO1.getReg();
1157 // Set shift operand (bit[7:4]).
1163 default: llvm_unreachable("Unknown shift opc!");
1164 case ARM_AM::lsl: SBits = 0x1; break;
1165 case ARM_AM::lsr: SBits = 0x3; break;
1166 case ARM_AM::asr: SBits = 0x5; break;
1167 case ARM_AM::ror: SBits = 0x7; break;
1171 Binary |= SBits << 4;
1173 // Encode the shift operation Rs.
1174 // Encode Rs bit[11:8].
1175 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1176 return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
1179 unsigned ARMMCCodeEmitter::
1180 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1181 SmallVectorImpl<MCFixup> &Fixups) const {
1182 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1183 // shifted. The second is the amount to shift by.
1190 const MCOperand &MO = MI.getOperand(OpIdx);
1191 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1192 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1195 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1197 // Encode the shift opcode.
1200 // Set shift operand (bit[6:4]).
1205 // RRX - 110 and bit[11:8] clear.
1207 default: llvm_unreachable("Unknown shift opc!");
1208 case ARM_AM::lsl: SBits = 0x0; break;
1209 case ARM_AM::lsr: SBits = 0x2; break;
1210 case ARM_AM::asr: SBits = 0x4; break;
1211 case ARM_AM::ror: SBits = 0x6; break;
1217 // Encode shift_imm bit[11:7].
1218 Binary |= SBits << 4;
1219 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1220 assert(Offset < 32 && "Offset must be in range 0-31!");
1221 return Binary | (Offset << 7);
1225 unsigned ARMMCCodeEmitter::
1226 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1227 SmallVectorImpl<MCFixup> &Fixups) const {
1228 const MCOperand &MO1 = MI.getOperand(OpNum);
1229 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1230 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1232 // Encoded as [Rn, Rm, imm].
1233 // FIXME: Needs fixup support.
1234 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1236 Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
1238 Value |= MO3.getImm();
1243 unsigned ARMMCCodeEmitter::
1244 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1245 SmallVectorImpl<MCFixup> &Fixups) const {
1246 const MCOperand &MO1 = MI.getOperand(OpNum);
1247 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1249 // FIXME: Needs fixup support.
1250 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1252 // Even though the immediate is 8 bits long, we need 9 bits in order
1253 // to represent the (inverse of the) sign bit.
1255 int32_t tmp = (int32_t)MO2.getImm();
1259 Value |= 256; // Set the ADD bit
1264 unsigned ARMMCCodeEmitter::
1265 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1266 SmallVectorImpl<MCFixup> &Fixups) const {
1267 const MCOperand &MO1 = MI.getOperand(OpNum);
1269 // FIXME: Needs fixup support.
1271 int32_t tmp = (int32_t)MO1.getImm();
1275 Value |= 256; // Set the ADD bit
1280 unsigned ARMMCCodeEmitter::
1281 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1282 SmallVectorImpl<MCFixup> &Fixups) const {
1283 const MCOperand &MO1 = MI.getOperand(OpNum);
1285 // FIXME: Needs fixup support.
1287 int32_t tmp = (int32_t)MO1.getImm();
1291 Value |= 4096; // Set the ADD bit
1292 Value |= tmp & 4095;
1296 unsigned ARMMCCodeEmitter::
1297 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1298 SmallVectorImpl<MCFixup> &Fixups) const {
1299 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1300 // shifted. The second is the amount to shift by.
1307 const MCOperand &MO = MI.getOperand(OpIdx);
1308 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1309 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1312 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1314 // Encode the shift opcode.
1316 // Set shift operand (bit[6:4]).
1322 default: llvm_unreachable("Unknown shift opc!");
1323 case ARM_AM::lsl: SBits = 0x0; break;
1324 case ARM_AM::lsr: SBits = 0x2; break;
1325 case ARM_AM::asr: SBits = 0x4; break;
1326 case ARM_AM::rrx: // FALLTHROUGH
1327 case ARM_AM::ror: SBits = 0x6; break;
1330 Binary |= SBits << 4;
1331 if (SOpc == ARM_AM::rrx)
1334 // Encode shift_imm bit[11:7].
1335 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1338 unsigned ARMMCCodeEmitter::
1339 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1340 SmallVectorImpl<MCFixup> &Fixups) const {
1341 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1343 const MCOperand &MO = MI.getOperand(Op);
1344 uint32_t v = ~MO.getImm();
1345 uint32_t lsb = CountTrailingZeros_32(v);
1346 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1347 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1348 return lsb | (msb << 5);
1351 unsigned ARMMCCodeEmitter::
1352 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1353 SmallVectorImpl<MCFixup> &Fixups) const {
1356 // {7-0} = Number of registers
1359 // {15-0} = Bitfield of GPRs.
1360 unsigned Reg = MI.getOperand(Op).getReg();
1361 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1362 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1364 unsigned Binary = 0;
1366 if (SPRRegs || DPRRegs) {
1368 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
1369 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1370 Binary |= (RegNo & 0x1f) << 8;
1374 Binary |= NumRegs * 2;
1376 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1377 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
1378 Binary |= 1 << RegNo;
1385 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1386 /// with the alignment operand.
1387 unsigned ARMMCCodeEmitter::
1388 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1389 SmallVectorImpl<MCFixup> &Fixups) const {
1390 const MCOperand &Reg = MI.getOperand(Op);
1391 const MCOperand &Imm = MI.getOperand(Op + 1);
1393 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1396 switch (Imm.getImm()) {
1400 case 8: Align = 0x01; break;
1401 case 16: Align = 0x02; break;
1402 case 32: Align = 0x03; break;
1405 return RegNo | (Align << 4);
1408 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1409 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1410 unsigned ARMMCCodeEmitter::
1411 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1412 SmallVectorImpl<MCFixup> &Fixups) const {
1413 const MCOperand &Reg = MI.getOperand(Op);
1414 const MCOperand &Imm = MI.getOperand(Op + 1);
1416 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1419 switch (Imm.getImm()) {
1423 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1424 case 2: Align = 0x00; break;
1425 case 4: Align = 0x03; break;
1428 return RegNo | (Align << 4);
1432 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1433 /// alignment operand for use in VLD-dup instructions. This is the same as
1434 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1435 /// different for VLD4-dup.
1436 unsigned ARMMCCodeEmitter::
1437 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1438 SmallVectorImpl<MCFixup> &Fixups) const {
1439 const MCOperand &Reg = MI.getOperand(Op);
1440 const MCOperand &Imm = MI.getOperand(Op + 1);
1442 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1445 switch (Imm.getImm()) {
1449 case 8: Align = 0x01; break;
1450 case 16: Align = 0x03; break;
1453 return RegNo | (Align << 4);
1456 unsigned ARMMCCodeEmitter::
1457 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1458 SmallVectorImpl<MCFixup> &Fixups) const {
1459 const MCOperand &MO = MI.getOperand(Op);
1460 if (MO.getReg() == 0) return 0x0D;
1461 return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1464 unsigned ARMMCCodeEmitter::
1465 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1466 SmallVectorImpl<MCFixup> &Fixups) const {
1467 return 8 - MI.getOperand(Op).getImm();
1470 unsigned ARMMCCodeEmitter::
1471 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1472 SmallVectorImpl<MCFixup> &Fixups) const {
1473 return 16 - MI.getOperand(Op).getImm();
1476 unsigned ARMMCCodeEmitter::
1477 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1478 SmallVectorImpl<MCFixup> &Fixups) const {
1479 return 32 - MI.getOperand(Op).getImm();
1482 unsigned ARMMCCodeEmitter::
1483 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1484 SmallVectorImpl<MCFixup> &Fixups) const {
1485 return 64 - MI.getOperand(Op).getImm();
1488 void ARMMCCodeEmitter::
1489 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1490 SmallVectorImpl<MCFixup> &Fixups) const {
1491 // Pseudo instructions don't get encoded.
1492 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1493 uint64_t TSFlags = Desc.TSFlags;
1494 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1498 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1499 Size = Desc.getSize();
1501 llvm_unreachable("Unexpected instruction size!");
1503 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1504 // Thumb 32-bit wide instructions need to emit the high order halfword
1506 if (isThumb() && Size == 4) {
1507 EmitConstant(Binary >> 16, 2, OS);
1508 EmitConstant(Binary & 0xffff, 2, OS);
1510 EmitConstant(Binary, Size, OS);
1511 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1514 #include "ARMGenMCCodeEmitter.inc"