1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
48 ~ARMMCCodeEmitter() {}
50 bool isThumb() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
54 bool isThumb2() const {
55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
57 bool isTargetDarwin() const {
58 Triple TT(STI.getTargetTriple());
59 Triple::OSType OS = TT.getOS();
60 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
63 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 unsigned getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76 /// the specified operand. This is used for operands with :lower16: and
77 /// :upper16: prefixes.
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82 unsigned &Reg, unsigned &Imm,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91 /// BLX branch target.
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113 /// immediate Thumb2 direct branch target.
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
121 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
124 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
125 /// ADR label target.
126 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127 SmallVectorImpl<MCFixup> &Fixups) const;
128 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
130 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
134 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
136 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl<MCFixup> &Fixups) const;
139 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
140 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups)const;
143 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
145 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
146 SmallVectorImpl<MCFixup> &Fixups) const;
148 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
150 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
151 SmallVectorImpl<MCFixup> &Fixups) const;
153 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
155 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups) const;
159 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
160 /// operand as needed by load/store instructions.
161 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups) const;
164 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
165 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const {
167 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
169 default: assert(0 && "Unknown addressing sub-mode!");
170 case ARM_AM::da: return 0;
171 case ARM_AM::ia: return 1;
172 case ARM_AM::db: return 2;
173 case ARM_AM::ib: return 3;
176 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
178 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
180 default: llvm_unreachable("Unknown shift opc!");
181 case ARM_AM::no_shift:
182 case ARM_AM::lsl: return 0;
183 case ARM_AM::lsr: return 1;
184 case ARM_AM::asr: return 2;
186 case ARM_AM::rrx: return 3;
191 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
192 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
193 SmallVectorImpl<MCFixup> &Fixups) const;
195 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
196 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
197 SmallVectorImpl<MCFixup> &Fixups) const;
199 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
200 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &Fixups) const;
203 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
204 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
205 SmallVectorImpl<MCFixup> &Fixups) const;
207 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
208 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
209 SmallVectorImpl<MCFixup> &Fixups) const;
211 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
213 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
214 SmallVectorImpl<MCFixup> &Fixups) const;
216 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
217 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
218 SmallVectorImpl<MCFixup> &Fixups) const;
220 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
221 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
222 SmallVectorImpl<MCFixup> &Fixups) const;
224 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
225 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
226 SmallVectorImpl<MCFixup> &Fixups) const;
228 /// getCCOutOpValue - Return encoding of the 's' bit.
229 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
230 SmallVectorImpl<MCFixup> &Fixups) const {
231 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
233 return MI.getOperand(Op).getReg() == ARM::CPSR;
236 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
237 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
238 SmallVectorImpl<MCFixup> &Fixups) const {
239 unsigned SoImm = MI.getOperand(Op).getImm();
240 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
241 assert(SoImmVal != -1 && "Not a valid so_imm value!");
243 // Encode rotate_imm.
244 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
245 << ARMII::SoRotImmShift;
248 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
252 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
253 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
254 SmallVectorImpl<MCFixup> &Fixups) const {
255 unsigned SoImm = MI.getOperand(Op).getImm();
256 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
257 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
261 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
262 SmallVectorImpl<MCFixup> &Fixups) const;
263 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
264 SmallVectorImpl<MCFixup> &Fixups) const;
265 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
266 SmallVectorImpl<MCFixup> &Fixups) const;
267 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
268 SmallVectorImpl<MCFixup> &Fixups) const;
270 /// getSORegOpValue - Return an encoded so_reg shifted register value.
271 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
272 SmallVectorImpl<MCFixup> &Fixups) const;
273 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups) const;
275 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const {
280 return 64 - MI.getOperand(Op).getImm();
283 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
284 SmallVectorImpl<MCFixup> &Fixups) const;
286 unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
291 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
294 SmallVectorImpl<MCFixup> &Fixups) const;
295 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
297 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
298 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
306 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups) const;
309 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
310 SmallVectorImpl<MCFixup> &Fixups) const;
312 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
314 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
316 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
317 unsigned EncodedValue) const;
319 unsigned VFPThumb2PostEncoder(const MCInst &MI,
320 unsigned EncodedValue) const;
322 void EmitByte(unsigned char C, raw_ostream &OS) const {
326 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
327 // Output the constant in little endian byte order.
328 for (unsigned i = 0; i != Size; ++i) {
329 EmitByte(Val & 255, OS);
334 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
335 SmallVectorImpl<MCFixup> &Fixups) const;
338 } // end anonymous namespace
340 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
341 const MCSubtargetInfo &STI,
343 return new ARMMCCodeEmitter(MCII, STI, Ctx);
346 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
347 /// instructions, and rewrite them to their Thumb2 form if we are currently in
349 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
350 unsigned EncodedValue) const {
352 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
353 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
355 unsigned Bit24 = EncodedValue & 0x01000000;
356 unsigned Bit28 = Bit24 << 4;
357 EncodedValue &= 0xEFFFFFFF;
358 EncodedValue |= Bit28;
359 EncodedValue |= 0x0F000000;
365 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
366 /// instructions, and rewrite them to their Thumb2 form if we are currently in
368 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
369 unsigned EncodedValue) const {
371 EncodedValue &= 0xF0FFFFFF;
372 EncodedValue |= 0x09000000;
378 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
379 /// instructions, and rewrite them to their Thumb2 form if we are currently in
381 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
382 unsigned EncodedValue) const {
384 EncodedValue &= 0x00FFFFFF;
385 EncodedValue |= 0xEE000000;
391 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
392 /// them to their Thumb2 form if we are currently in Thumb2 mode.
393 unsigned ARMMCCodeEmitter::
394 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
396 EncodedValue &= 0x0FFFFFFF;
397 EncodedValue |= 0xE0000000;
402 /// getMachineOpValue - Return binary encoding of operand. If the machine
403 /// operand requires relocation, record the relocation and return zero.
404 unsigned ARMMCCodeEmitter::
405 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
406 SmallVectorImpl<MCFixup> &Fixups) const {
408 unsigned Reg = MO.getReg();
409 unsigned RegNo = getARMRegisterNumbering(Reg);
411 // Q registers are encoded as 2x their register number.
415 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
416 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
417 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
418 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
421 } else if (MO.isImm()) {
422 return static_cast<unsigned>(MO.getImm());
423 } else if (MO.isFPImm()) {
424 return static_cast<unsigned>(APFloat(MO.getFPImm())
425 .bitcastToAPInt().getHiBits(32).getLimitedValue());
428 llvm_unreachable("Unable to encode MCOperand!");
432 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
433 bool ARMMCCodeEmitter::
434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
436 const MCOperand &MO = MI.getOperand(OpIdx);
437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
439 Reg = getARMRegisterNumbering(MO.getReg());
441 int32_t SImm = MO1.getImm();
444 // Special value for #-0
445 if (SImm == INT32_MIN) {
450 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
460 /// getBranchTargetOpValue - Helper function to get the branch target operand,
461 /// which is either an immediate or requires a fixup.
462 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
464 SmallVectorImpl<MCFixup> &Fixups) {
465 const MCOperand &MO = MI.getOperand(OpIdx);
467 // If the destination is an immediate, we have nothing to do.
468 if (MO.isImm()) return MO.getImm();
469 assert(MO.isExpr() && "Unexpected branch target type!");
470 const MCExpr *Expr = MO.getExpr();
471 MCFixupKind Kind = MCFixupKind(FixupKind);
472 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
474 // All of the information is in the fixup.
478 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
479 // determined by negating them and XOR'ing them with bit 23.
480 static int32_t encodeThumbBLOffset(int32_t offset) {
482 uint32_t S = (offset & 0x800000) >> 23;
483 uint32_t J1 = (offset & 0x400000) >> 22;
484 uint32_t J2 = (offset & 0x200000) >> 21;
497 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
498 uint32_t ARMMCCodeEmitter::
499 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
500 SmallVectorImpl<MCFixup> &Fixups) const {
501 const MCOperand MO = MI.getOperand(OpIdx);
503 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
505 return encodeThumbBLOffset(MO.getImm());
508 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
509 /// BLX branch target.
510 uint32_t ARMMCCodeEmitter::
511 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
512 SmallVectorImpl<MCFixup> &Fixups) const {
513 const MCOperand MO = MI.getOperand(OpIdx);
515 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
517 return encodeThumbBLOffset(MO.getImm());
520 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
521 uint32_t ARMMCCodeEmitter::
522 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups) const {
524 const MCOperand MO = MI.getOperand(OpIdx);
526 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
528 return (MO.getImm() >> 1);
531 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
532 uint32_t ARMMCCodeEmitter::
533 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
534 SmallVectorImpl<MCFixup> &Fixups) const {
535 const MCOperand MO = MI.getOperand(OpIdx);
537 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
539 return (MO.getImm() >> 1);
542 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
543 uint32_t ARMMCCodeEmitter::
544 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
545 SmallVectorImpl<MCFixup> &Fixups) const {
546 const MCOperand MO = MI.getOperand(OpIdx);
548 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
549 return (MO.getImm() >> 1);
552 /// Return true if this branch has a non-always predication
553 static bool HasConditionalBranch(const MCInst &MI) {
554 int NumOp = MI.getNumOperands();
556 for (int i = 0; i < NumOp-1; ++i) {
557 const MCOperand &MCOp1 = MI.getOperand(i);
558 const MCOperand &MCOp2 = MI.getOperand(i + 1);
559 if (MCOp1.isImm() && MCOp2.isReg() &&
560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
561 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
569 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
571 uint32_t ARMMCCodeEmitter::
572 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
573 SmallVectorImpl<MCFixup> &Fixups) const {
574 // FIXME: This really, really shouldn't use TargetMachine. We don't want
575 // coupling between MC and TM anywhere we can help it.
578 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
579 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
582 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
584 uint32_t ARMMCCodeEmitter::
585 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
586 SmallVectorImpl<MCFixup> &Fixups) const {
587 const MCOperand MO = MI.getOperand(OpIdx);
589 if (HasConditionalBranch(MI))
590 return ::getBranchTargetOpValue(MI, OpIdx,
591 ARM::fixup_arm_condbranch, Fixups);
592 return ::getBranchTargetOpValue(MI, OpIdx,
593 ARM::fixup_arm_uncondbranch, Fixups);
596 return MO.getImm() >> 2;
599 uint32_t ARMMCCodeEmitter::
600 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
601 SmallVectorImpl<MCFixup> &Fixups) const {
602 const MCOperand MO = MI.getOperand(OpIdx);
604 if (HasConditionalBranch(MI))
605 return ::getBranchTargetOpValue(MI, OpIdx,
606 ARM::fixup_arm_condbranch, Fixups);
607 return ::getBranchTargetOpValue(MI, OpIdx,
608 ARM::fixup_arm_uncondbranch, Fixups);
611 return MO.getImm() >> 1;
614 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
615 /// immediate branch target.
616 uint32_t ARMMCCodeEmitter::
617 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
618 SmallVectorImpl<MCFixup> &Fixups) const {
620 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
621 bool I = (Val & 0x800000);
622 bool J1 = (Val & 0x400000);
623 bool J2 = (Val & 0x200000);
637 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
639 uint32_t ARMMCCodeEmitter::
640 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
641 SmallVectorImpl<MCFixup> &Fixups) const {
642 const MCOperand MO = MI.getOperand(OpIdx);
644 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
646 int32_t offset = MO.getImm();
647 uint32_t Val = 0x2000;
656 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
658 uint32_t ARMMCCodeEmitter::
659 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
660 SmallVectorImpl<MCFixup> &Fixups) const {
661 const MCOperand MO = MI.getOperand(OpIdx);
663 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
668 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
670 uint32_t ARMMCCodeEmitter::
671 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
672 SmallVectorImpl<MCFixup> &Fixups) const {
673 const MCOperand MO = MI.getOperand(OpIdx);
675 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
680 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
682 uint32_t ARMMCCodeEmitter::
683 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
684 SmallVectorImpl<MCFixup> &) const {
688 const MCOperand &MO1 = MI.getOperand(OpIdx);
689 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
690 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
691 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
692 return (Rm << 3) | Rn;
695 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
696 uint32_t ARMMCCodeEmitter::
697 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
698 SmallVectorImpl<MCFixup> &Fixups) const {
700 // {12} = (U)nsigned (add == '1', sub == '0')
704 // If The first operand isn't a register, we have a label reference.
705 const MCOperand &MO = MI.getOperand(OpIdx);
707 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
709 isAdd = false ; // 'U' bit is set as part of the fixup.
711 assert(MO.isExpr() && "Unexpected machine operand type!");
712 const MCExpr *Expr = MO.getExpr();
716 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
718 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
719 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
721 ++MCNumCPRelocations;
723 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
725 uint32_t Binary = Imm12 & 0xfff;
726 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
729 Binary |= (Reg << 13);
733 /// getT2Imm8s4OpValue - Return encoding info for
734 /// '+/- imm8<<2' operand.
735 uint32_t ARMMCCodeEmitter::
736 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
737 SmallVectorImpl<MCFixup> &Fixups) const {
738 // FIXME: The immediate operand should have already been encoded like this
739 // before ever getting here. The encoder method should just need to combine
740 // the MI operands for the register and the offset into a single
741 // representation for the complex operand in the .td file. This isn't just
742 // style, unfortunately. As-is, we can't represent the distinct encoding
745 // {8} = (U)nsigned (add == '1', sub == '0')
747 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
748 bool isAdd = Imm8 >= 0;
750 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
757 uint32_t Binary = Imm8 & 0xff;
758 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
764 /// getT2AddrModeImm8s4OpValue - Return encoding info for
765 /// 'reg +/- imm8<<2' operand.
766 uint32_t ARMMCCodeEmitter::
767 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
768 SmallVectorImpl<MCFixup> &Fixups) const {
770 // {8} = (U)nsigned (add == '1', sub == '0')
774 // If The first operand isn't a register, we have a label reference.
775 const MCOperand &MO = MI.getOperand(OpIdx);
777 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
779 isAdd = false ; // 'U' bit is set as part of the fixup.
781 assert(MO.isExpr() && "Unexpected machine operand type!");
782 const MCExpr *Expr = MO.getExpr();
783 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
784 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
786 ++MCNumCPRelocations;
788 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
790 // FIXME: The immediate operand should have already been encoded like this
791 // before ever getting here. The encoder method should just need to combine
792 // the MI operands for the register and the offset into a single
793 // representation for the complex operand in the .td file. This isn't just
794 // style, unfortunately. As-is, we can't represent the distinct encoding
796 uint32_t Binary = (Imm8 >> 2) & 0xff;
797 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
800 Binary |= (Reg << 9);
804 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
805 /// 'reg + imm8<<2' operand.
806 uint32_t ARMMCCodeEmitter::
807 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
808 SmallVectorImpl<MCFixup> &Fixups) const {
811 const MCOperand &MO = MI.getOperand(OpIdx);
812 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
813 unsigned Reg = getARMRegisterNumbering(MO.getReg());
814 unsigned Imm8 = MO1.getImm();
815 return (Reg << 8) | Imm8;
818 // FIXME: This routine assumes that a binary
819 // expression will always result in a PCRel expression
820 // In reality, its only true if one or more subexpressions
821 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
822 // but this is good enough for now.
823 static bool EvaluateAsPCRel(const MCExpr *Expr) {
824 switch (Expr->getKind()) {
825 default: assert(0 && "Unexpected expression type");
826 case MCExpr::SymbolRef: return false;
827 case MCExpr::Binary: return true;
832 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
833 SmallVectorImpl<MCFixup> &Fixups) const {
834 // {20-16} = imm{15-12}
835 // {11-0} = imm{11-0}
836 const MCOperand &MO = MI.getOperand(OpIdx);
838 // Hi / lo 16 bits already extracted during earlier passes.
839 return static_cast<unsigned>(MO.getImm());
841 // Handle :upper16: and :lower16: assembly prefixes.
842 const MCExpr *E = MO.getExpr();
843 if (E->getKind() == MCExpr::Target) {
844 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
845 E = ARM16Expr->getSubExpr();
848 switch (ARM16Expr->getKind()) {
849 default: assert(0 && "Unsupported ARMFixup");
850 case ARMMCExpr::VK_ARM_HI16:
851 if (!isTargetDarwin() && EvaluateAsPCRel(E))
852 Kind = MCFixupKind(isThumb2()
853 ? ARM::fixup_t2_movt_hi16_pcrel
854 : ARM::fixup_arm_movt_hi16_pcrel);
856 Kind = MCFixupKind(isThumb2()
857 ? ARM::fixup_t2_movt_hi16
858 : ARM::fixup_arm_movt_hi16);
860 case ARMMCExpr::VK_ARM_LO16:
861 if (!isTargetDarwin() && EvaluateAsPCRel(E))
862 Kind = MCFixupKind(isThumb2()
863 ? ARM::fixup_t2_movw_lo16_pcrel
864 : ARM::fixup_arm_movw_lo16_pcrel);
866 Kind = MCFixupKind(isThumb2()
867 ? ARM::fixup_t2_movw_lo16
868 : ARM::fixup_arm_movw_lo16);
871 Fixups.push_back(MCFixup::Create(0, E, Kind));
875 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
879 uint32_t ARMMCCodeEmitter::
880 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
881 SmallVectorImpl<MCFixup> &Fixups) const {
882 const MCOperand &MO = MI.getOperand(OpIdx);
883 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
884 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
885 unsigned Rn = getARMRegisterNumbering(MO.getReg());
886 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
887 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
888 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
889 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
890 unsigned SBits = getShiftOp(ShOp);
899 uint32_t Binary = Rm;
901 Binary |= SBits << 5;
902 Binary |= ShImm << 7;
908 uint32_t ARMMCCodeEmitter::
909 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
910 SmallVectorImpl<MCFixup> &Fixups) const {
912 // {13} 1 == imm12, 0 == Rm
915 const MCOperand &MO = MI.getOperand(OpIdx);
916 unsigned Rn = getARMRegisterNumbering(MO.getReg());
917 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
922 uint32_t ARMMCCodeEmitter::
923 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
924 SmallVectorImpl<MCFixup> &Fixups) const {
925 // {13} 1 == imm12, 0 == Rm
928 const MCOperand &MO = MI.getOperand(OpIdx);
929 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
930 unsigned Imm = MO1.getImm();
931 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
932 bool isReg = MO.getReg() != 0;
933 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
934 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
936 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
937 Binary <<= 7; // Shift amount is bits [11:7]
938 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
939 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
941 return Binary | (isAdd << 12) | (isReg << 13);
944 uint32_t ARMMCCodeEmitter::
945 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
946 SmallVectorImpl<MCFixup> &Fixups) const {
949 const MCOperand &MO = MI.getOperand(OpIdx);
950 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
951 bool isAdd = MO1.getImm() != 0;
952 return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
955 uint32_t ARMMCCodeEmitter::
956 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
957 SmallVectorImpl<MCFixup> &Fixups) const {
958 // {9} 1 == imm8, 0 == Rm
962 const MCOperand &MO = MI.getOperand(OpIdx);
963 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
964 unsigned Imm = MO1.getImm();
965 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
966 bool isImm = MO.getReg() == 0;
967 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
968 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
970 Imm8 = getARMRegisterNumbering(MO.getReg());
971 return Imm8 | (isAdd << 8) | (isImm << 9);
974 uint32_t ARMMCCodeEmitter::
975 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
976 SmallVectorImpl<MCFixup> &Fixups) const {
977 // {13} 1 == imm8, 0 == Rm
982 const MCOperand &MO = MI.getOperand(OpIdx);
983 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
984 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
985 unsigned Rn = getARMRegisterNumbering(MO.getReg());
986 unsigned Imm = MO2.getImm();
987 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
988 bool isImm = MO1.getReg() == 0;
989 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
990 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
992 Imm8 = getARMRegisterNumbering(MO1.getReg());
993 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
996 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
997 uint32_t ARMMCCodeEmitter::
998 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
999 SmallVectorImpl<MCFixup> &Fixups) const {
1002 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1003 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1004 "Unexpected base register!");
1006 // The immediate is already shifted for the implicit zeroes, so no change
1008 return MO1.getImm() & 0xff;
1011 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1012 uint32_t ARMMCCodeEmitter::
1013 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1014 SmallVectorImpl<MCFixup> &Fixups) const {
1018 const MCOperand &MO = MI.getOperand(OpIdx);
1019 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1020 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1021 unsigned Imm5 = MO1.getImm();
1022 return ((Imm5 & 0x1f) << 3) | Rn;
1025 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1026 uint32_t ARMMCCodeEmitter::
1027 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1028 SmallVectorImpl<MCFixup> &Fixups) const {
1029 const MCOperand MO = MI.getOperand(OpIdx);
1031 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1032 return (MO.getImm() >> 2);
1035 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1036 uint32_t ARMMCCodeEmitter::
1037 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1038 SmallVectorImpl<MCFixup> &Fixups) const {
1040 // {8} = (U)nsigned (add == '1', sub == '0')
1044 // If The first operand isn't a register, we have a label reference.
1045 const MCOperand &MO = MI.getOperand(OpIdx);
1047 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1049 isAdd = false; // 'U' bit is handled as part of the fixup.
1051 assert(MO.isExpr() && "Unexpected machine operand type!");
1052 const MCExpr *Expr = MO.getExpr();
1055 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1057 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1058 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
1060 ++MCNumCPRelocations;
1062 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1063 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1066 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1067 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1070 Binary |= (Reg << 9);
1074 unsigned ARMMCCodeEmitter::
1075 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1076 SmallVectorImpl<MCFixup> &Fixups) const {
1077 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1078 // shifted. The second is Rs, the amount to shift by, and the third specifies
1079 // the type of the shift.
1087 const MCOperand &MO = MI.getOperand(OpIdx);
1088 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1089 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1090 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1093 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1095 // Encode the shift opcode.
1097 unsigned Rs = MO1.getReg();
1099 // Set shift operand (bit[7:4]).
1105 default: llvm_unreachable("Unknown shift opc!");
1106 case ARM_AM::lsl: SBits = 0x1; break;
1107 case ARM_AM::lsr: SBits = 0x3; break;
1108 case ARM_AM::asr: SBits = 0x5; break;
1109 case ARM_AM::ror: SBits = 0x7; break;
1113 Binary |= SBits << 4;
1115 // Encode the shift operation Rs.
1116 // Encode Rs bit[11:8].
1117 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1118 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1121 unsigned ARMMCCodeEmitter::
1122 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1123 SmallVectorImpl<MCFixup> &Fixups) const {
1124 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1125 // shifted. The second is the amount to shift by.
1132 const MCOperand &MO = MI.getOperand(OpIdx);
1133 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1134 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1137 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1139 // Encode the shift opcode.
1142 // Set shift operand (bit[6:4]).
1147 // RRX - 110 and bit[11:8] clear.
1149 default: llvm_unreachable("Unknown shift opc!");
1150 case ARM_AM::lsl: SBits = 0x0; break;
1151 case ARM_AM::lsr: SBits = 0x2; break;
1152 case ARM_AM::asr: SBits = 0x4; break;
1153 case ARM_AM::ror: SBits = 0x6; break;
1159 // Encode shift_imm bit[11:7].
1160 Binary |= SBits << 4;
1161 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1162 assert(Offset && "Offset must be in range 1-32!");
1163 if (Offset == 32) Offset = 0;
1164 return Binary | (Offset << 7);
1168 unsigned ARMMCCodeEmitter::
1169 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1170 SmallVectorImpl<MCFixup> &Fixups) const {
1171 const MCOperand &MO1 = MI.getOperand(OpNum);
1172 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1173 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1175 // Encoded as [Rn, Rm, imm].
1176 // FIXME: Needs fixup support.
1177 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1179 Value |= getARMRegisterNumbering(MO2.getReg());
1181 Value |= MO3.getImm();
1186 unsigned ARMMCCodeEmitter::
1187 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1188 SmallVectorImpl<MCFixup> &Fixups) const {
1189 const MCOperand &MO1 = MI.getOperand(OpNum);
1190 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1192 // FIXME: Needs fixup support.
1193 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1195 // Even though the immediate is 8 bits long, we need 9 bits in order
1196 // to represent the (inverse of the) sign bit.
1198 int32_t tmp = (int32_t)MO2.getImm();
1202 Value |= 256; // Set the ADD bit
1207 unsigned ARMMCCodeEmitter::
1208 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1209 SmallVectorImpl<MCFixup> &Fixups) const {
1210 const MCOperand &MO1 = MI.getOperand(OpNum);
1212 // FIXME: Needs fixup support.
1214 int32_t tmp = (int32_t)MO1.getImm();
1218 Value |= 256; // Set the ADD bit
1223 unsigned ARMMCCodeEmitter::
1224 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1225 SmallVectorImpl<MCFixup> &Fixups) const {
1226 const MCOperand &MO1 = MI.getOperand(OpNum);
1228 // FIXME: Needs fixup support.
1230 int32_t tmp = (int32_t)MO1.getImm();
1234 Value |= 4096; // Set the ADD bit
1235 Value |= tmp & 4095;
1239 unsigned ARMMCCodeEmitter::
1240 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1241 SmallVectorImpl<MCFixup> &Fixups) const {
1242 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1243 // shifted. The second is the amount to shift by.
1250 const MCOperand &MO = MI.getOperand(OpIdx);
1251 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1252 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1255 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1257 // Encode the shift opcode.
1259 // Set shift operand (bit[6:4]).
1265 default: llvm_unreachable("Unknown shift opc!");
1266 case ARM_AM::lsl: SBits = 0x0; break;
1267 case ARM_AM::lsr: SBits = 0x2; break;
1268 case ARM_AM::asr: SBits = 0x4; break;
1269 case ARM_AM::ror: SBits = 0x6; break;
1272 Binary |= SBits << 4;
1273 if (SOpc == ARM_AM::rrx)
1276 // Encode shift_imm bit[11:7].
1277 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1280 unsigned ARMMCCodeEmitter::
1281 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1282 SmallVectorImpl<MCFixup> &Fixups) const {
1283 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1285 const MCOperand &MO = MI.getOperand(Op);
1286 uint32_t v = ~MO.getImm();
1287 uint32_t lsb = CountTrailingZeros_32(v);
1288 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1289 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1290 return lsb | (msb << 5);
1293 unsigned ARMMCCodeEmitter::
1294 getMsbOpValue(const MCInst &MI, unsigned Op,
1295 SmallVectorImpl<MCFixup> &Fixups) const {
1297 uint32_t lsb = MI.getOperand(Op-1).getImm();
1298 uint32_t width = MI.getOperand(Op).getImm();
1299 uint32_t msb = lsb+width-1;
1300 assert (width != 0 && msb < 32 && "Illegal bit width!");
1304 unsigned ARMMCCodeEmitter::
1305 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1306 SmallVectorImpl<MCFixup> &Fixups) const {
1309 // {7-0} = Number of registers
1312 // {15-0} = Bitfield of GPRs.
1313 unsigned Reg = MI.getOperand(Op).getReg();
1314 bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1315 bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1317 unsigned Binary = 0;
1319 if (SPRRegs || DPRRegs) {
1321 unsigned RegNo = getARMRegisterNumbering(Reg);
1322 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1323 Binary |= (RegNo & 0x1f) << 8;
1327 Binary |= NumRegs * 2;
1329 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1330 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1331 Binary |= 1 << RegNo;
1338 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1339 /// with the alignment operand.
1340 unsigned ARMMCCodeEmitter::
1341 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1342 SmallVectorImpl<MCFixup> &Fixups) const {
1343 const MCOperand &Reg = MI.getOperand(Op);
1344 const MCOperand &Imm = MI.getOperand(Op + 1);
1346 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1349 switch (Imm.getImm()) {
1353 case 8: Align = 0x01; break;
1354 case 16: Align = 0x02; break;
1355 case 32: Align = 0x03; break;
1358 return RegNo | (Align << 4);
1361 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1362 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1363 unsigned ARMMCCodeEmitter::
1364 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1365 SmallVectorImpl<MCFixup> &Fixups) const {
1366 const MCOperand &Reg = MI.getOperand(Op);
1367 const MCOperand &Imm = MI.getOperand(Op + 1);
1369 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1372 switch (Imm.getImm()) {
1377 case 16: Align = 0x00; break;
1378 case 32: Align = 0x03; break;
1381 return RegNo | (Align << 4);
1385 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1386 /// alignment operand for use in VLD-dup instructions. This is the same as
1387 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1388 /// different for VLD4-dup.
1389 unsigned ARMMCCodeEmitter::
1390 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1391 SmallVectorImpl<MCFixup> &Fixups) const {
1392 const MCOperand &Reg = MI.getOperand(Op);
1393 const MCOperand &Imm = MI.getOperand(Op + 1);
1395 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1398 switch (Imm.getImm()) {
1402 case 8: Align = 0x01; break;
1403 case 16: Align = 0x03; break;
1406 return RegNo | (Align << 4);
1409 unsigned ARMMCCodeEmitter::
1410 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1411 SmallVectorImpl<MCFixup> &Fixups) const {
1412 const MCOperand &MO = MI.getOperand(Op);
1413 if (MO.getReg() == 0) return 0x0D;
1417 unsigned ARMMCCodeEmitter::
1418 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1419 SmallVectorImpl<MCFixup> &Fixups) const {
1420 return 8 - MI.getOperand(Op).getImm();
1423 unsigned ARMMCCodeEmitter::
1424 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1425 SmallVectorImpl<MCFixup> &Fixups) const {
1426 return 16 - MI.getOperand(Op).getImm();
1429 unsigned ARMMCCodeEmitter::
1430 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1431 SmallVectorImpl<MCFixup> &Fixups) const {
1432 return 32 - MI.getOperand(Op).getImm();
1435 unsigned ARMMCCodeEmitter::
1436 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1437 SmallVectorImpl<MCFixup> &Fixups) const {
1438 return 64 - MI.getOperand(Op).getImm();
1441 void ARMMCCodeEmitter::
1442 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1443 SmallVectorImpl<MCFixup> &Fixups) const {
1444 // Pseudo instructions don't get encoded.
1445 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1446 uint64_t TSFlags = Desc.TSFlags;
1447 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1451 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1452 Size = Desc.getSize();
1454 llvm_unreachable("Unexpected instruction size!");
1456 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1457 // Thumb 32-bit wide instructions need to emit the high order halfword
1459 if (isThumb() && Size == 4) {
1460 EmitConstant(Binary >> 16, 2, OS);
1461 EmitConstant(Binary & 0xffff, 2, OS);
1463 EmitConstant(Binary, Size, OS);
1464 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1467 #include "ARMGenMCCodeEmitter.inc"