1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/ARMMCTargetDesc.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 #define DEBUG_TYPE "mccodeemitter"
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
39 class ARMMCCodeEmitter : public MCCodeEmitter {
40 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
41 void operator=(const ARMMCCodeEmitter &) = delete;
42 const MCInstrInfo &MCII;
47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
51 ~ARMMCCodeEmitter() {}
53 bool isThumb(const MCSubtargetInfo &STI) const {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2(const MCSubtargetInfo &STI) const {
57 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetMachO(const MCSubtargetInfo &STI) const {
60 Triple TT(STI.getTargetTriple());
61 return TT.isOSBinFormatMachO();
64 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
66 // getBinaryCodeForInstr - TableGen'erated function for getting the
67 // binary encoding for an instruction.
68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
69 SmallVectorImpl<MCFixup> &Fixups,
70 const MCSubtargetInfo &STI) const;
72 /// getMachineOpValue - Return binary encoding of operand. If the machine
73 /// operand requires relocation, record the relocation and return zero.
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
78 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
79 /// the specified operand. This is used for operands with :lower16: and
80 /// :upper16: prefixes.
81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const;
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86 unsigned &Reg, unsigned &Imm,
87 SmallVectorImpl<MCFixup> &Fixups,
88 const MCSubtargetInfo &STI) const;
90 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI) const;
96 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
97 /// BLX branch target.
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
102 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 SmallVectorImpl<MCFixup> &Fixups,
105 const MCSubtargetInfo &STI) const;
107 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
112 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups,
115 const MCSubtargetInfo &STI) const;
117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups,
121 const MCSubtargetInfo &STI) const;
123 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
124 /// immediate Thumb2 direct branch target.
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups,
127 const MCSubtargetInfo &STI) const;
129 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
141 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
142 /// ADR label target.
143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
157 SmallVectorImpl<MCFixup> &Fixups,
158 const MCSubtargetInfo &STI) const;
160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const;
165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups,
169 const MCSubtargetInfo &STI) const;
171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
174 SmallVectorImpl<MCFixup> &Fixups,
175 const MCSubtargetInfo &STI) const;
177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const;
184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
185 /// operand as needed by load/store instructions.
186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
187 SmallVectorImpl<MCFixup> &Fixups,
188 const MCSubtargetInfo &STI) const;
190 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
192 SmallVectorImpl<MCFixup> &Fixups,
193 const MCSubtargetInfo &STI) const {
194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
196 default: llvm_unreachable("Unknown addressing sub-mode!");
197 case ARM_AM::da: return 0;
198 case ARM_AM::ia: return 1;
199 case ARM_AM::db: return 2;
200 case ARM_AM::ib: return 3;
203 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
207 case ARM_AM::no_shift:
208 case ARM_AM::lsl: return 0;
209 case ARM_AM::lsr: return 1;
210 case ARM_AM::asr: return 2;
212 case ARM_AM::rrx: return 3;
214 llvm_unreachable("Invalid ShiftOpc!");
217 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
218 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
219 SmallVectorImpl<MCFixup> &Fixups,
220 const MCSubtargetInfo &STI) const;
222 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
223 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
224 SmallVectorImpl<MCFixup> &Fixups,
225 const MCSubtargetInfo &STI) const;
227 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
228 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups,
230 const MCSubtargetInfo &STI) const;
232 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
233 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
234 SmallVectorImpl<MCFixup> &Fixups,
235 const MCSubtargetInfo &STI) const;
237 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
238 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
239 SmallVectorImpl<MCFixup> &Fixups,
240 const MCSubtargetInfo &STI) const;
242 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
244 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
245 SmallVectorImpl<MCFixup> &Fixups,
246 const MCSubtargetInfo &STI) const;
248 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
249 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const;
253 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
254 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
255 SmallVectorImpl<MCFixup> &Fixups,
256 const MCSubtargetInfo &STI) const;
258 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
259 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
260 SmallVectorImpl<MCFixup> &Fixups,
261 const MCSubtargetInfo &STI) const;
263 /// getCCOutOpValue - Return encoding of the 's' bit.
264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
265 SmallVectorImpl<MCFixup> &Fixups,
266 const MCSubtargetInfo &STI) const {
267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups,
275 const MCSubtargetInfo &STI) const {
277 const MCOperand &MO = MI.getOperand(Op);
279 // We expect MO to be an immediate or an expression,
280 // if it is an immediate - that's fine, just encode the value.
281 // Otherwise - create a Fixup.
283 const MCExpr *Expr = MO.getExpr();
284 // In instruction code this value always encoded as lowest 12 bits,
285 // so we don't have to perform any specific adjustments.
286 // Due to requirements of relocatable records we have to use FK_Data_4.
287 // See ARMELFObjectWriter::ExplicitRelSym and
288 // ARMELFObjectWriter::GetRelocTypeInner for more details.
289 MCFixupKind Kind = MCFixupKind(FK_Data_4);
290 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
294 unsigned SoImm = MO.getImm();
295 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
296 assert(SoImmVal != -1 && "Not a valid so_imm value!");
298 // Encode rotate_imm.
299 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
300 << ARMII::SoRotImmShift;
303 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
307 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
308 SmallVectorImpl<MCFixup> &Fixups,
309 const MCSubtargetInfo &ST) const {
310 const MCOperand &MO = MI.getOperand(Op);
312 // Support for fixups (MCFixup)
314 const MCExpr *Expr = MO.getExpr();
315 // In instruction code this value always encoded as lowest 12 bits,
316 // so we don't have to perform any specific adjustments.
317 // Due to requirements of relocatable records we have to use FK_Data_4.
318 // See ARMELFObjectWriter::ExplicitRelSym and
319 // ARMELFObjectWriter::GetRelocTypeInner for more details.
320 MCFixupKind Kind = MCFixupKind(FK_Data_4);
321 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
325 // Immediate is already in its encoded format
329 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
330 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const {
333 unsigned SoImm = MI.getOperand(Op).getImm();
334 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
335 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
339 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
340 SmallVectorImpl<MCFixup> &Fixups,
341 const MCSubtargetInfo &STI) const;
342 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
343 SmallVectorImpl<MCFixup> &Fixups,
344 const MCSubtargetInfo &STI) const;
345 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
346 SmallVectorImpl<MCFixup> &Fixups,
347 const MCSubtargetInfo &STI) const;
348 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
349 SmallVectorImpl<MCFixup> &Fixups,
350 const MCSubtargetInfo &STI) const;
352 /// getSORegOpValue - Return an encoded so_reg shifted register value.
353 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
354 SmallVectorImpl<MCFixup> &Fixups,
355 const MCSubtargetInfo &STI) const;
356 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
357 SmallVectorImpl<MCFixup> &Fixups,
358 const MCSubtargetInfo &STI) const;
359 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
360 SmallVectorImpl<MCFixup> &Fixups,
361 const MCSubtargetInfo &STI) const;
363 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
364 SmallVectorImpl<MCFixup> &Fixups,
365 const MCSubtargetInfo &STI) const {
366 return 64 - MI.getOperand(Op).getImm();
369 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
370 SmallVectorImpl<MCFixup> &Fixups,
371 const MCSubtargetInfo &STI) const;
373 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
374 SmallVectorImpl<MCFixup> &Fixups,
375 const MCSubtargetInfo &STI) const;
376 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
377 SmallVectorImpl<MCFixup> &Fixups,
378 const MCSubtargetInfo &STI) const;
379 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
380 SmallVectorImpl<MCFixup> &Fixups,
381 const MCSubtargetInfo &STI) const;
382 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
383 SmallVectorImpl<MCFixup> &Fixups,
384 const MCSubtargetInfo &STI) const;
385 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
386 SmallVectorImpl<MCFixup> &Fixups,
387 const MCSubtargetInfo &STI) const;
389 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
390 SmallVectorImpl<MCFixup> &Fixups,
391 const MCSubtargetInfo &STI) const;
392 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
393 SmallVectorImpl<MCFixup> &Fixups,
394 const MCSubtargetInfo &STI) const;
395 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
396 SmallVectorImpl<MCFixup> &Fixups,
397 const MCSubtargetInfo &STI) const;
398 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
399 SmallVectorImpl<MCFixup> &Fixups,
400 const MCSubtargetInfo &STI) const;
402 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
403 SmallVectorImpl<MCFixup> &Fixups,
404 const MCSubtargetInfo &STI) const;
406 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
407 unsigned EncodedValue,
408 const MCSubtargetInfo &STI) const;
409 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
410 unsigned EncodedValue,
411 const MCSubtargetInfo &STI) const;
412 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
413 unsigned EncodedValue,
414 const MCSubtargetInfo &STI) const;
415 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
416 unsigned EncodedValue,
417 const MCSubtargetInfo &STI) const;
419 unsigned VFPThumb2PostEncoder(const MCInst &MI,
420 unsigned EncodedValue,
421 const MCSubtargetInfo &STI) const;
423 void EmitByte(unsigned char C, raw_ostream &OS) const {
427 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
428 // Output the constant in little endian byte order.
429 for (unsigned i = 0; i != Size; ++i) {
430 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
431 EmitByte((Val >> Shift) & 0xff, OS);
435 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
436 SmallVectorImpl<MCFixup> &Fixups,
437 const MCSubtargetInfo &STI) const override;
440 } // end anonymous namespace
442 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
443 const MCRegisterInfo &MRI,
444 const MCSubtargetInfo &STI,
446 return new ARMMCCodeEmitter(MCII, Ctx, true);
449 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
450 const MCRegisterInfo &MRI,
451 const MCSubtargetInfo &STI,
453 return new ARMMCCodeEmitter(MCII, Ctx, false);
456 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
457 /// instructions, and rewrite them to their Thumb2 form if we are currently in
459 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
460 unsigned EncodedValue,
461 const MCSubtargetInfo &STI) const {
463 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
464 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
466 unsigned Bit24 = EncodedValue & 0x01000000;
467 unsigned Bit28 = Bit24 << 4;
468 EncodedValue &= 0xEFFFFFFF;
469 EncodedValue |= Bit28;
470 EncodedValue |= 0x0F000000;
476 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
477 /// instructions, and rewrite them to their Thumb2 form if we are currently in
479 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
480 unsigned EncodedValue,
481 const MCSubtargetInfo &STI) const {
483 EncodedValue &= 0xF0FFFFFF;
484 EncodedValue |= 0x09000000;
490 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
491 /// instructions, and rewrite them to their Thumb2 form if we are currently in
493 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
494 unsigned EncodedValue,
495 const MCSubtargetInfo &STI) const {
497 EncodedValue &= 0x00FFFFFF;
498 EncodedValue |= 0xEE000000;
504 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
505 /// if we are in Thumb2.
506 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
507 unsigned EncodedValue,
508 const MCSubtargetInfo &STI) const {
510 EncodedValue |= 0xC000000; // Set bits 27-26
516 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
517 /// them to their Thumb2 form if we are currently in Thumb2 mode.
518 unsigned ARMMCCodeEmitter::
519 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
520 const MCSubtargetInfo &STI) const {
522 EncodedValue &= 0x0FFFFFFF;
523 EncodedValue |= 0xE0000000;
528 /// getMachineOpValue - Return binary encoding of operand. If the machine
529 /// operand requires relocation, record the relocation and return zero.
530 unsigned ARMMCCodeEmitter::
531 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
532 SmallVectorImpl<MCFixup> &Fixups,
533 const MCSubtargetInfo &STI) const {
535 unsigned Reg = MO.getReg();
536 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
538 // Q registers are encoded as 2x their register number.
542 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
543 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
544 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
545 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
548 } else if (MO.isImm()) {
549 return static_cast<unsigned>(MO.getImm());
550 } else if (MO.isFPImm()) {
551 return static_cast<unsigned>(APFloat(MO.getFPImm())
552 .bitcastToAPInt().getHiBits(32).getLimitedValue());
555 llvm_unreachable("Unable to encode MCOperand!");
558 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
559 bool ARMMCCodeEmitter::
560 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
561 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
562 const MCSubtargetInfo &STI) const {
563 const MCOperand &MO = MI.getOperand(OpIdx);
564 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
566 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
568 int32_t SImm = MO1.getImm();
571 // Special value for #-0
572 if (SImm == INT32_MIN) {
577 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
587 /// getBranchTargetOpValue - Helper function to get the branch target operand,
588 /// which is either an immediate or requires a fixup.
589 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
591 SmallVectorImpl<MCFixup> &Fixups,
592 const MCSubtargetInfo &STI) {
593 const MCOperand &MO = MI.getOperand(OpIdx);
595 // If the destination is an immediate, we have nothing to do.
596 if (MO.isImm()) return MO.getImm();
597 assert(MO.isExpr() && "Unexpected branch target type!");
598 const MCExpr *Expr = MO.getExpr();
599 MCFixupKind Kind = MCFixupKind(FixupKind);
600 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
602 // All of the information is in the fixup.
606 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
607 // determined by negating them and XOR'ing them with bit 23.
608 static int32_t encodeThumbBLOffset(int32_t offset) {
610 uint32_t S = (offset & 0x800000) >> 23;
611 uint32_t J1 = (offset & 0x400000) >> 22;
612 uint32_t J2 = (offset & 0x200000) >> 21;
625 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
626 uint32_t ARMMCCodeEmitter::
627 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
628 SmallVectorImpl<MCFixup> &Fixups,
629 const MCSubtargetInfo &STI) const {
630 const MCOperand MO = MI.getOperand(OpIdx);
632 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
634 return encodeThumbBLOffset(MO.getImm());
637 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
638 /// BLX branch target.
639 uint32_t ARMMCCodeEmitter::
640 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
641 SmallVectorImpl<MCFixup> &Fixups,
642 const MCSubtargetInfo &STI) const {
643 const MCOperand MO = MI.getOperand(OpIdx);
645 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
647 return encodeThumbBLOffset(MO.getImm());
650 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
651 uint32_t ARMMCCodeEmitter::
652 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
653 SmallVectorImpl<MCFixup> &Fixups,
654 const MCSubtargetInfo &STI) const {
655 const MCOperand MO = MI.getOperand(OpIdx);
657 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
659 return (MO.getImm() >> 1);
662 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
663 uint32_t ARMMCCodeEmitter::
664 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
665 SmallVectorImpl<MCFixup> &Fixups,
666 const MCSubtargetInfo &STI) const {
667 const MCOperand MO = MI.getOperand(OpIdx);
669 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
671 return (MO.getImm() >> 1);
674 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
675 uint32_t ARMMCCodeEmitter::
676 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
677 SmallVectorImpl<MCFixup> &Fixups,
678 const MCSubtargetInfo &STI) const {
679 const MCOperand MO = MI.getOperand(OpIdx);
681 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
682 return (MO.getImm() >> 1);
685 /// Return true if this branch has a non-always predication
686 static bool HasConditionalBranch(const MCInst &MI) {
687 int NumOp = MI.getNumOperands();
689 for (int i = 0; i < NumOp-1; ++i) {
690 const MCOperand &MCOp1 = MI.getOperand(i);
691 const MCOperand &MCOp2 = MI.getOperand(i + 1);
692 if (MCOp1.isImm() && MCOp2.isReg() &&
693 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
694 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
702 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
704 uint32_t ARMMCCodeEmitter::
705 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
706 SmallVectorImpl<MCFixup> &Fixups,
707 const MCSubtargetInfo &STI) const {
708 // FIXME: This really, really shouldn't use TargetMachine. We don't want
709 // coupling between MC and TM anywhere we can help it.
712 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
713 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
716 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
718 uint32_t ARMMCCodeEmitter::
719 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
720 SmallVectorImpl<MCFixup> &Fixups,
721 const MCSubtargetInfo &STI) const {
722 const MCOperand MO = MI.getOperand(OpIdx);
724 if (HasConditionalBranch(MI))
725 return ::getBranchTargetOpValue(MI, OpIdx,
726 ARM::fixup_arm_condbranch, Fixups, STI);
727 return ::getBranchTargetOpValue(MI, OpIdx,
728 ARM::fixup_arm_uncondbranch, Fixups, STI);
731 return MO.getImm() >> 2;
734 uint32_t ARMMCCodeEmitter::
735 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
736 SmallVectorImpl<MCFixup> &Fixups,
737 const MCSubtargetInfo &STI) const {
738 const MCOperand MO = MI.getOperand(OpIdx);
740 if (HasConditionalBranch(MI))
741 return ::getBranchTargetOpValue(MI, OpIdx,
742 ARM::fixup_arm_condbl, Fixups, STI);
743 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
746 return MO.getImm() >> 2;
749 uint32_t ARMMCCodeEmitter::
750 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
751 SmallVectorImpl<MCFixup> &Fixups,
752 const MCSubtargetInfo &STI) const {
753 const MCOperand MO = MI.getOperand(OpIdx);
755 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
757 return MO.getImm() >> 1;
760 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
761 /// immediate branch target.
762 uint32_t ARMMCCodeEmitter::
763 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
764 SmallVectorImpl<MCFixup> &Fixups,
765 const MCSubtargetInfo &STI) const {
767 const MCOperand MO = MI.getOperand(OpIdx);
770 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
772 Val = MO.getImm() >> 1;
774 bool I = (Val & 0x800000);
775 bool J1 = (Val & 0x400000);
776 bool J2 = (Val & 0x200000);
790 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
791 /// ADR label target.
792 uint32_t ARMMCCodeEmitter::
793 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
794 SmallVectorImpl<MCFixup> &Fixups,
795 const MCSubtargetInfo &STI) const {
796 const MCOperand MO = MI.getOperand(OpIdx);
798 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
800 int64_t offset = MO.getImm();
801 uint32_t Val = 0x2000;
804 if (offset == INT32_MIN) {
807 } else if (offset < 0) {
810 SoImmVal = ARM_AM::getSOImmVal(offset);
814 SoImmVal = ARM_AM::getSOImmVal(offset);
817 SoImmVal = ARM_AM::getSOImmVal(offset);
821 SoImmVal = ARM_AM::getSOImmVal(offset);
825 assert(SoImmVal != -1 && "Not a valid so_imm value!");
831 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
833 uint32_t ARMMCCodeEmitter::
834 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
835 SmallVectorImpl<MCFixup> &Fixups,
836 const MCSubtargetInfo &STI) const {
837 const MCOperand MO = MI.getOperand(OpIdx);
839 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
841 int32_t Val = MO.getImm();
842 if (Val == INT32_MIN)
851 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
853 uint32_t ARMMCCodeEmitter::
854 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
855 SmallVectorImpl<MCFixup> &Fixups,
856 const MCSubtargetInfo &STI) const {
857 const MCOperand MO = MI.getOperand(OpIdx);
859 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
864 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
866 uint32_t ARMMCCodeEmitter::
867 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
868 SmallVectorImpl<MCFixup> &,
869 const MCSubtargetInfo &STI) const {
873 const MCOperand &MO1 = MI.getOperand(OpIdx);
874 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
875 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
876 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
877 return (Rm << 3) | Rn;
880 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
881 uint32_t ARMMCCodeEmitter::
882 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
883 SmallVectorImpl<MCFixup> &Fixups,
884 const MCSubtargetInfo &STI) const {
886 // {12} = (U)nsigned (add == '1', sub == '0')
890 // If The first operand isn't a register, we have a label reference.
891 const MCOperand &MO = MI.getOperand(OpIdx);
893 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
897 const MCExpr *Expr = MO.getExpr();
898 isAdd = false ; // 'U' bit is set as part of the fixup.
902 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
904 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
905 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
907 ++MCNumCPRelocations;
910 int32_t Offset = MO.getImm();
911 if (Offset == INT32_MIN) {
914 } else if (Offset < 0) {
921 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
923 uint32_t Binary = Imm12 & 0xfff;
924 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
927 Binary |= (Reg << 13);
931 /// getT2Imm8s4OpValue - Return encoding info for
932 /// '+/- imm8<<2' operand.
933 uint32_t ARMMCCodeEmitter::
934 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
935 SmallVectorImpl<MCFixup> &Fixups,
936 const MCSubtargetInfo &STI) const {
937 // FIXME: The immediate operand should have already been encoded like this
938 // before ever getting here. The encoder method should just need to combine
939 // the MI operands for the register and the offset into a single
940 // representation for the complex operand in the .td file. This isn't just
941 // style, unfortunately. As-is, we can't represent the distinct encoding
944 // {8} = (U)nsigned (add == '1', sub == '0')
946 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
947 bool isAdd = Imm8 >= 0;
949 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
951 Imm8 = -(uint32_t)Imm8;
956 uint32_t Binary = Imm8 & 0xff;
957 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
963 /// getT2AddrModeImm8s4OpValue - Return encoding info for
964 /// 'reg +/- imm8<<2' operand.
965 uint32_t ARMMCCodeEmitter::
966 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
967 SmallVectorImpl<MCFixup> &Fixups,
968 const MCSubtargetInfo &STI) const {
970 // {8} = (U)nsigned (add == '1', sub == '0')
974 // If The first operand isn't a register, we have a label reference.
975 const MCOperand &MO = MI.getOperand(OpIdx);
977 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
979 isAdd = false ; // 'U' bit is set as part of the fixup.
981 assert(MO.isExpr() && "Unexpected machine operand type!");
982 const MCExpr *Expr = MO.getExpr();
983 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
984 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
986 ++MCNumCPRelocations;
988 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
990 // FIXME: The immediate operand should have already been encoded like this
991 // before ever getting here. The encoder method should just need to combine
992 // the MI operands for the register and the offset into a single
993 // representation for the complex operand in the .td file. This isn't just
994 // style, unfortunately. As-is, we can't represent the distinct encoding
996 uint32_t Binary = (Imm8 >> 2) & 0xff;
997 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1000 Binary |= (Reg << 9);
1004 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1005 /// 'reg + imm8<<2' operand.
1006 uint32_t ARMMCCodeEmitter::
1007 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1008 SmallVectorImpl<MCFixup> &Fixups,
1009 const MCSubtargetInfo &STI) const {
1012 const MCOperand &MO = MI.getOperand(OpIdx);
1013 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1014 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1015 unsigned Imm8 = MO1.getImm();
1016 return (Reg << 8) | Imm8;
1020 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1021 SmallVectorImpl<MCFixup> &Fixups,
1022 const MCSubtargetInfo &STI) const {
1023 // {20-16} = imm{15-12}
1024 // {11-0} = imm{11-0}
1025 const MCOperand &MO = MI.getOperand(OpIdx);
1027 // Hi / lo 16 bits already extracted during earlier passes.
1028 return static_cast<unsigned>(MO.getImm());
1030 // Handle :upper16: and :lower16: assembly prefixes.
1031 const MCExpr *E = MO.getExpr();
1033 if (E->getKind() == MCExpr::Target) {
1034 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1035 E = ARM16Expr->getSubExpr();
1037 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1038 const int64_t Value = MCE->getValue();
1039 if (Value > UINT32_MAX)
1040 report_fatal_error("constant value truncated (limited to 32-bit)");
1042 switch (ARM16Expr->getKind()) {
1043 case ARMMCExpr::VK_ARM_HI16:
1044 return (int32_t(Value) & 0xffff0000) >> 16;
1045 case ARMMCExpr::VK_ARM_LO16:
1046 return (int32_t(Value) & 0x0000ffff);
1047 default: llvm_unreachable("Unsupported ARMFixup");
1051 switch (ARM16Expr->getKind()) {
1052 default: llvm_unreachable("Unsupported ARMFixup");
1053 case ARMMCExpr::VK_ARM_HI16:
1054 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16
1055 : ARM::fixup_arm_movt_hi16);
1057 case ARMMCExpr::VK_ARM_LO16:
1058 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16
1059 : ARM::fixup_arm_movw_lo16);
1063 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
1066 // If the expression doesn't have :upper16: or :lower16: on it,
1067 // it's just a plain immediate expression, previously those evaluated to
1068 // the lower 16 bits of the expression regardless of whether
1069 // we have a movt or a movw, but that led to misleadingly results.
1070 // This is now disallowed in the the AsmParser in validateInstruction()
1071 // so this should never happen.
1072 llvm_unreachable("expression without :upper16: or :lower16:");
1075 uint32_t ARMMCCodeEmitter::
1076 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1077 SmallVectorImpl<MCFixup> &Fixups,
1078 const MCSubtargetInfo &STI) const {
1079 const MCOperand &MO = MI.getOperand(OpIdx);
1080 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1081 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1082 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1083 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1084 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1085 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1086 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1087 unsigned SBits = getShiftOp(ShOp);
1089 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1090 // amount. However, it would be an easy mistake to make so check here.
1091 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1100 uint32_t Binary = Rm;
1102 Binary |= SBits << 5;
1103 Binary |= ShImm << 7;
1109 uint32_t ARMMCCodeEmitter::
1110 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1111 SmallVectorImpl<MCFixup> &Fixups,
1112 const MCSubtargetInfo &STI) const {
1114 // {13} 1 == imm12, 0 == Rm
1117 const MCOperand &MO = MI.getOperand(OpIdx);
1118 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1119 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1124 uint32_t ARMMCCodeEmitter::
1125 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1126 SmallVectorImpl<MCFixup> &Fixups,
1127 const MCSubtargetInfo &STI) const {
1128 // {13} 1 == imm12, 0 == Rm
1131 const MCOperand &MO = MI.getOperand(OpIdx);
1132 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1133 unsigned Imm = MO1.getImm();
1134 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1135 bool isReg = MO.getReg() != 0;
1136 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1137 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1139 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1140 Binary <<= 7; // Shift amount is bits [11:7]
1141 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1142 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1144 return Binary | (isAdd << 12) | (isReg << 13);
1147 uint32_t ARMMCCodeEmitter::
1148 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1149 SmallVectorImpl<MCFixup> &Fixups,
1150 const MCSubtargetInfo &STI) const {
1153 const MCOperand &MO = MI.getOperand(OpIdx);
1154 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1155 bool isAdd = MO1.getImm() != 0;
1156 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1159 uint32_t ARMMCCodeEmitter::
1160 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1161 SmallVectorImpl<MCFixup> &Fixups,
1162 const MCSubtargetInfo &STI) const {
1163 // {9} 1 == imm8, 0 == Rm
1165 // {7-4} imm7_4/zero
1167 const MCOperand &MO = MI.getOperand(OpIdx);
1168 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1169 unsigned Imm = MO1.getImm();
1170 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1171 bool isImm = MO.getReg() == 0;
1172 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1173 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1175 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1176 return Imm8 | (isAdd << 8) | (isImm << 9);
1179 uint32_t ARMMCCodeEmitter::
1180 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1181 SmallVectorImpl<MCFixup> &Fixups,
1182 const MCSubtargetInfo &STI) const {
1183 // {13} 1 == imm8, 0 == Rm
1186 // {7-4} imm7_4/zero
1188 const MCOperand &MO = MI.getOperand(OpIdx);
1189 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1190 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1192 // If The first operand isn't a register, we have a label reference.
1194 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1196 assert(MO.isExpr() && "Unexpected machine operand type!");
1197 const MCExpr *Expr = MO.getExpr();
1198 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1199 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1201 ++MCNumCPRelocations;
1202 return (Rn << 9) | (1 << 13);
1204 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1205 unsigned Imm = MO2.getImm();
1206 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1207 bool isImm = MO1.getReg() == 0;
1208 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1209 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1211 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1212 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1215 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1216 uint32_t ARMMCCodeEmitter::
1217 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1218 SmallVectorImpl<MCFixup> &Fixups,
1219 const MCSubtargetInfo &STI) const {
1222 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1223 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1224 "Unexpected base register!");
1226 // The immediate is already shifted for the implicit zeroes, so no change
1228 return MO1.getImm() & 0xff;
1231 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1232 uint32_t ARMMCCodeEmitter::
1233 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1234 SmallVectorImpl<MCFixup> &Fixups,
1235 const MCSubtargetInfo &STI) const {
1239 const MCOperand &MO = MI.getOperand(OpIdx);
1240 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1241 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1242 unsigned Imm5 = MO1.getImm();
1243 return ((Imm5 & 0x1f) << 3) | Rn;
1246 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1247 uint32_t ARMMCCodeEmitter::
1248 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1249 SmallVectorImpl<MCFixup> &Fixups,
1250 const MCSubtargetInfo &STI) const {
1251 const MCOperand MO = MI.getOperand(OpIdx);
1253 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1254 return (MO.getImm() >> 2);
1257 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1258 uint32_t ARMMCCodeEmitter::
1259 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1260 SmallVectorImpl<MCFixup> &Fixups,
1261 const MCSubtargetInfo &STI) const {
1263 // {8} = (U)nsigned (add == '1', sub == '0')
1267 // If The first operand isn't a register, we have a label reference.
1268 const MCOperand &MO = MI.getOperand(OpIdx);
1270 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1272 isAdd = false; // 'U' bit is handled as part of the fixup.
1274 assert(MO.isExpr() && "Unexpected machine operand type!");
1275 const MCExpr *Expr = MO.getExpr();
1278 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1280 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1281 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1283 ++MCNumCPRelocations;
1285 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1286 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1289 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1290 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1293 Binary |= (Reg << 9);
1297 unsigned ARMMCCodeEmitter::
1298 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1299 SmallVectorImpl<MCFixup> &Fixups,
1300 const MCSubtargetInfo &STI) const {
1301 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1302 // shifted. The second is Rs, the amount to shift by, and the third specifies
1303 // the type of the shift.
1311 const MCOperand &MO = MI.getOperand(OpIdx);
1312 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1313 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1314 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1317 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1319 // Encode the shift opcode.
1321 unsigned Rs = MO1.getReg();
1323 // Set shift operand (bit[7:4]).
1329 default: llvm_unreachable("Unknown shift opc!");
1330 case ARM_AM::lsl: SBits = 0x1; break;
1331 case ARM_AM::lsr: SBits = 0x3; break;
1332 case ARM_AM::asr: SBits = 0x5; break;
1333 case ARM_AM::ror: SBits = 0x7; break;
1337 Binary |= SBits << 4;
1339 // Encode the shift operation Rs.
1340 // Encode Rs bit[11:8].
1341 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1342 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1345 unsigned ARMMCCodeEmitter::
1346 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1347 SmallVectorImpl<MCFixup> &Fixups,
1348 const MCSubtargetInfo &STI) const {
1349 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1350 // shifted. The second is the amount to shift by.
1357 const MCOperand &MO = MI.getOperand(OpIdx);
1358 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1359 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1362 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1364 // Encode the shift opcode.
1367 // Set shift operand (bit[6:4]).
1372 // RRX - 110 and bit[11:8] clear.
1374 default: llvm_unreachable("Unknown shift opc!");
1375 case ARM_AM::lsl: SBits = 0x0; break;
1376 case ARM_AM::lsr: SBits = 0x2; break;
1377 case ARM_AM::asr: SBits = 0x4; break;
1378 case ARM_AM::ror: SBits = 0x6; break;
1384 // Encode shift_imm bit[11:7].
1385 Binary |= SBits << 4;
1386 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1387 assert(Offset < 32 && "Offset must be in range 0-31!");
1388 return Binary | (Offset << 7);
1392 unsigned ARMMCCodeEmitter::
1393 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1394 SmallVectorImpl<MCFixup> &Fixups,
1395 const MCSubtargetInfo &STI) const {
1396 const MCOperand &MO1 = MI.getOperand(OpNum);
1397 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1398 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1400 // Encoded as [Rn, Rm, imm].
1401 // FIXME: Needs fixup support.
1402 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1404 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1406 Value |= MO3.getImm();
1411 unsigned ARMMCCodeEmitter::
1412 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1413 SmallVectorImpl<MCFixup> &Fixups,
1414 const MCSubtargetInfo &STI) const {
1415 const MCOperand &MO1 = MI.getOperand(OpNum);
1416 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1418 // FIXME: Needs fixup support.
1419 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1421 // Even though the immediate is 8 bits long, we need 9 bits in order
1422 // to represent the (inverse of the) sign bit.
1424 int32_t tmp = (int32_t)MO2.getImm();
1428 Value |= 256; // Set the ADD bit
1433 unsigned ARMMCCodeEmitter::
1434 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1435 SmallVectorImpl<MCFixup> &Fixups,
1436 const MCSubtargetInfo &STI) const {
1437 const MCOperand &MO1 = MI.getOperand(OpNum);
1439 // FIXME: Needs fixup support.
1441 int32_t tmp = (int32_t)MO1.getImm();
1445 Value |= 256; // Set the ADD bit
1450 unsigned ARMMCCodeEmitter::
1451 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1452 SmallVectorImpl<MCFixup> &Fixups,
1453 const MCSubtargetInfo &STI) const {
1454 const MCOperand &MO1 = MI.getOperand(OpNum);
1456 // FIXME: Needs fixup support.
1458 int32_t tmp = (int32_t)MO1.getImm();
1462 Value |= 4096; // Set the ADD bit
1463 Value |= tmp & 4095;
1467 unsigned ARMMCCodeEmitter::
1468 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1469 SmallVectorImpl<MCFixup> &Fixups,
1470 const MCSubtargetInfo &STI) const {
1471 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1472 // shifted. The second is the amount to shift by.
1479 const MCOperand &MO = MI.getOperand(OpIdx);
1480 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1481 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1484 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1486 // Encode the shift opcode.
1488 // Set shift operand (bit[6:4]).
1494 default: llvm_unreachable("Unknown shift opc!");
1495 case ARM_AM::lsl: SBits = 0x0; break;
1496 case ARM_AM::lsr: SBits = 0x2; break;
1497 case ARM_AM::asr: SBits = 0x4; break;
1498 case ARM_AM::rrx: // FALLTHROUGH
1499 case ARM_AM::ror: SBits = 0x6; break;
1502 Binary |= SBits << 4;
1503 if (SOpc == ARM_AM::rrx)
1506 // Encode shift_imm bit[11:7].
1507 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1510 unsigned ARMMCCodeEmitter::
1511 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1512 SmallVectorImpl<MCFixup> &Fixups,
1513 const MCSubtargetInfo &STI) const {
1514 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1516 const MCOperand &MO = MI.getOperand(Op);
1517 uint32_t v = ~MO.getImm();
1518 uint32_t lsb = countTrailingZeros(v);
1519 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1520 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1521 return lsb | (msb << 5);
1524 unsigned ARMMCCodeEmitter::
1525 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1526 SmallVectorImpl<MCFixup> &Fixups,
1527 const MCSubtargetInfo &STI) const {
1530 // {7-0} = Number of registers
1533 // {15-0} = Bitfield of GPRs.
1534 unsigned Reg = MI.getOperand(Op).getReg();
1535 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1536 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1538 unsigned Binary = 0;
1540 if (SPRRegs || DPRRegs) {
1542 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1543 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1544 Binary |= (RegNo & 0x1f) << 8;
1548 Binary |= NumRegs * 2;
1550 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1551 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1552 Binary |= 1 << RegNo;
1559 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1560 /// with the alignment operand.
1561 unsigned ARMMCCodeEmitter::
1562 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1563 SmallVectorImpl<MCFixup> &Fixups,
1564 const MCSubtargetInfo &STI) const {
1565 const MCOperand &Reg = MI.getOperand(Op);
1566 const MCOperand &Imm = MI.getOperand(Op + 1);
1568 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1571 switch (Imm.getImm()) {
1575 case 8: Align = 0x01; break;
1576 case 16: Align = 0x02; break;
1577 case 32: Align = 0x03; break;
1580 return RegNo | (Align << 4);
1583 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1584 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1585 unsigned ARMMCCodeEmitter::
1586 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1587 SmallVectorImpl<MCFixup> &Fixups,
1588 const MCSubtargetInfo &STI) const {
1589 const MCOperand &Reg = MI.getOperand(Op);
1590 const MCOperand &Imm = MI.getOperand(Op + 1);
1592 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1595 switch (Imm.getImm()) {
1599 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1600 case 2: Align = 0x00; break;
1601 case 4: Align = 0x03; break;
1604 return RegNo | (Align << 4);
1608 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1609 /// alignment operand for use in VLD-dup instructions. This is the same as
1610 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1611 /// different for VLD4-dup.
1612 unsigned ARMMCCodeEmitter::
1613 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1614 SmallVectorImpl<MCFixup> &Fixups,
1615 const MCSubtargetInfo &STI) const {
1616 const MCOperand &Reg = MI.getOperand(Op);
1617 const MCOperand &Imm = MI.getOperand(Op + 1);
1619 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1622 switch (Imm.getImm()) {
1626 case 8: Align = 0x01; break;
1627 case 16: Align = 0x03; break;
1630 return RegNo | (Align << 4);
1633 unsigned ARMMCCodeEmitter::
1634 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1635 SmallVectorImpl<MCFixup> &Fixups,
1636 const MCSubtargetInfo &STI) const {
1637 const MCOperand &MO = MI.getOperand(Op);
1638 if (MO.getReg() == 0) return 0x0D;
1639 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1642 unsigned ARMMCCodeEmitter::
1643 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1644 SmallVectorImpl<MCFixup> &Fixups,
1645 const MCSubtargetInfo &STI) const {
1646 return 8 - MI.getOperand(Op).getImm();
1649 unsigned ARMMCCodeEmitter::
1650 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1651 SmallVectorImpl<MCFixup> &Fixups,
1652 const MCSubtargetInfo &STI) const {
1653 return 16 - MI.getOperand(Op).getImm();
1656 unsigned ARMMCCodeEmitter::
1657 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1658 SmallVectorImpl<MCFixup> &Fixups,
1659 const MCSubtargetInfo &STI) const {
1660 return 32 - MI.getOperand(Op).getImm();
1663 unsigned ARMMCCodeEmitter::
1664 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1665 SmallVectorImpl<MCFixup> &Fixups,
1666 const MCSubtargetInfo &STI) const {
1667 return 64 - MI.getOperand(Op).getImm();
1670 void ARMMCCodeEmitter::
1671 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1672 SmallVectorImpl<MCFixup> &Fixups,
1673 const MCSubtargetInfo &STI) const {
1674 // Pseudo instructions don't get encoded.
1675 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1676 uint64_t TSFlags = Desc.TSFlags;
1677 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1681 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1682 Size = Desc.getSize();
1684 llvm_unreachable("Unexpected instruction size!");
1686 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1687 // Thumb 32-bit wide instructions need to emit the high order halfword
1689 if (isThumb(STI) && Size == 4) {
1690 EmitConstant(Binary >> 16, 2, OS);
1691 EmitConstant(Binary & 0xffff, 2, OS);
1693 EmitConstant(Binary, Size, OS);
1694 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1697 #include "ARMGenMCCodeEmitter.inc"