1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMELFStreamer.h"
16 #include "ARMMCAsmInfo.h"
17 #include "ARMMCTargetDesc.h"
18 #include "InstPrinter/ARMInstPrinter.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCCodeGenInfo.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
29 #define GET_REGINFO_MC_DESC
30 #include "ARMGenRegisterInfo.inc"
32 #define GET_INSTRINFO_MC_DESC
33 #include "ARMGenInstrInfo.inc"
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "ARMGenSubtargetInfo.inc"
40 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
43 // Set the boolean corresponding to the current target triple, or the default
44 // if one cannot be determined, to true.
45 unsigned Len = TT.size();
48 // FIXME: Enhance Triple helper class to extract ARM version.
50 if (Len >= 5 && TT.substr(0, 4) == "armv")
52 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
54 if (Len >= 7 && TT[5] == 'v')
58 bool NoCPU = CPU == "generic" || CPU.empty();
59 std::string ARMArchFeature;
61 unsigned SubVer = TT[Idx];
62 if (SubVer >= '7' && SubVer <= '9') {
63 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
65 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
66 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
68 // Use CPU to figure out the exact features.
69 ARMArchFeature = "+v7";
70 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
72 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
73 // FeatureT2XtPk, FeatureMClass
74 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
76 // Use CPU to figure out the exact features.
77 ARMArchFeature = "+v7";
78 } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
80 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
82 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
84 // Use CPU to figure out the exact features.
85 ARMArchFeature = "+v7";
87 // v7 CPUs have lots of different feature sets. If no CPU is specified,
88 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
89 // the "minimum" feature set and use CPU string to figure out the exact
92 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
93 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
95 // Use CPU to figure out the exact features.
96 ARMArchFeature = "+v7";
98 } else if (SubVer == '6') {
99 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
100 ARMArchFeature = "+v6t2";
101 else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
103 // v6m: FeatureNoARM, FeatureMClass
104 ARMArchFeature = "+v6,+noarm,+mclass";
106 ARMArchFeature = "+v6";
108 ARMArchFeature = "+v6";
109 } else if (SubVer == '5') {
110 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
111 ARMArchFeature = "+v5te";
113 ARMArchFeature = "+v5t";
114 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
115 ARMArchFeature = "+v4t";
119 if (ARMArchFeature.empty())
120 ARMArchFeature = "+thumb-mode";
122 ARMArchFeature += ",+thumb-mode";
125 if (triple.isOSNaCl()) {
126 if (ARMArchFeature.empty())
127 ARMArchFeature = "+nacl-trap";
129 ARMArchFeature += ",+nacl-trap";
132 return ARMArchFeature;
135 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
137 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
140 ArchFS = ArchFS + "," + FS.str();
145 MCSubtargetInfo *X = new MCSubtargetInfo();
146 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
150 static MCInstrInfo *createARMMCInstrInfo() {
151 MCInstrInfo *X = new MCInstrInfo();
152 InitARMMCInstrInfo(X);
156 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
157 MCRegisterInfo *X = new MCRegisterInfo();
158 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
162 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
163 Triple TheTriple(TT);
165 if (TheTriple.isOSDarwin())
166 return new ARMMCAsmInfoDarwin();
168 return new ARMELFMCAsmInfo();
171 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
173 CodeGenOpt::Level OL) {
174 MCCodeGenInfo *X = new MCCodeGenInfo();
175 if (RM == Reloc::Default) {
176 Triple TheTriple(TT);
177 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
178 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
180 X->InitMCCodeGenInfo(RM, CM, OL);
184 // This is duplicated code. Refactor this.
185 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
186 MCContext &Ctx, MCAsmBackend &MAB,
188 MCCodeEmitter *Emitter,
191 Triple TheTriple(TT);
193 if (TheTriple.isOSDarwin())
194 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
196 if (TheTriple.isOSWindows()) {
197 llvm_unreachable("ARM does not support Windows COFF format");
200 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
201 TheTriple.getArch() == Triple::thumb);
204 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
205 unsigned SyntaxVariant,
206 const MCAsmInfo &MAI,
207 const MCInstrInfo &MII,
208 const MCRegisterInfo &MRI,
209 const MCSubtargetInfo &STI) {
210 if (SyntaxVariant == 0)
211 return new ARMInstPrinter(MAI, MII, MRI, STI);
215 static MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) {
216 Triple TheTriple(TT);
217 if (TheTriple.isEnvironmentMachO())
218 return createARMMachORelocationInfo(Ctx);
219 // Default to the stock relocation info.
220 return llvm::createMCRelocationInfo(Ctx);
225 class ARMMCInstrAnalysis : public MCInstrAnalysis {
227 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
229 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
230 // BCCs with the "always" predicate are unconditional branches.
231 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
233 return MCInstrAnalysis::isUnconditionalBranch(Inst);
236 virtual bool isConditionalBranch(const MCInst &Inst) const {
237 // BCCs with the "always" predicate are unconditional branches.
238 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
240 return MCInstrAnalysis::isConditionalBranch(Inst);
243 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
244 uint64_t Size) const {
245 // We only handle PCRel branches for now.
246 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
249 int64_t Imm = Inst.getOperand(0).getImm();
250 // FIXME: This is not right for thumb.
251 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
257 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
258 return new ARMMCInstrAnalysis(Info);
261 // Force static initialization.
262 extern "C" void LLVMInitializeARMTargetMC() {
263 // Register the MC asm info.
264 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
265 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
267 // Register the MC codegen info.
268 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
269 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
271 // Register the MC instruction info.
272 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
273 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
275 // Register the MC register info.
276 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
277 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
279 // Register the MC subtarget info.
280 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
281 ARM_MC::createARMMCSubtargetInfo);
282 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
283 ARM_MC::createARMMCSubtargetInfo);
285 // Register the MC instruction analyzer.
286 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
287 createARMMCInstrAnalysis);
288 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
289 createARMMCInstrAnalysis);
291 // Register the MC Code Emitter
292 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
293 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
295 // Register the asm backend.
296 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
297 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
299 // Register the object streamer.
300 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
301 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
303 // Register the MCInstPrinter.
304 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
305 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
307 // Register the MC relocation info.
308 TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
309 createMCRelocationInfo);
310 TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
311 createMCRelocationInfo);