lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInfo.h"
  15 #include "ARMMCAsmInfo.h"
  16 #include "ARMMCTargetDesc.h"
  17 #include "InstPrinter/ARMInstPrinter.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCELFStreamer.h"
  21 #include "llvm/MC/MCInstrAnalysis.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28
  29 using namespace llvm;
  30
  31 #define GET_REGINFO_MC_DESC
  32 #include "ARMGenRegisterInfo.inc"
  33
  34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  35                                   std::string &Info) {
  36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
  37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
  38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
  39       // Checks for the deprecated CP15ISB encoding:
  40       // mcr p15, #0, rX, c7, c5, #4
  41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
  42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
  43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
  44         Info = "deprecated since v7, use 'isb'";
  45         return true;
  46       }
  47
  48       // Checks for the deprecated CP15DSB encoding:
  49       // mcr p15, #0, rX, c7, c10, #4
  50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
  51         Info = "deprecated since v7, use 'dsb'";
  52         return true;
  53       }
  54     }
  55     // Checks for the deprecated CP15DMB encoding:
  56     // mcr p15, #0, rX, c7, c10, #5
  57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
  58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
  59       Info = "deprecated since v7, use 'dmb'";
  60       return true;
  61     }
  62   }
  63   return false;
  64 }
  65
  66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  67                                   std::string &Info) {
  68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
  69       MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
  70     Info = "applying IT instruction to more than one subsequent instruction is deprecated";
  71     return true;
  72   }
  73
  74   return false;
  75 }
  76
  77 #define GET_INSTRINFO_MC_DESC
  78 #include "ARMGenInstrInfo.inc"
  79
  80 #define GET_SUBTARGETINFO_MC_DESC
  81 #include "ARMGenSubtargetInfo.inc"
  82
  83
  84 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
  85   Triple triple(TT);
  86
  87   bool isThumb = triple.getArch() == Triple::thumb ||
  88                  triple.getArch() == Triple::thumbeb;
  89
  90   bool NoCPU = CPU == "generic" || CPU.empty();
  91   std::string ARMArchFeature;
  92   switch (triple.getSubArch()) {
  93   case Triple::ARMSubArch_v8:
  94     if (NoCPU)
  95       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
  96       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
  97       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
  98       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
  99                        "+trustzone,+t2xtpk,+crypto,+crc";
 100     else
 101       // Use CPU to figure out the exact features
 102       ARMArchFeature = "+v8";
 103     break;
 104   case Triple::ARMSubArch_v7m:
 105     isThumb = true;
 106     if (NoCPU)
 107       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
 108       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
 109     else
 110       // Use CPU to figure out the exact features.
 111       ARMArchFeature = "+v7";
 112     break;
 113   case Triple::ARMSubArch_v7em:
 114     if (NoCPU)
 115       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
 116       //       FeatureT2XtPk, FeatureMClass
 117       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
 118     else
 119       // Use CPU to figure out the exact features.
 120       ARMArchFeature = "+v7";
 121     break;
 122   case Triple::ARMSubArch_v7s:
 123     if (NoCPU)
 124       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
 125       //      Swift
 126       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
 127     else
 128       // Use CPU to figure out the exact features.
 129       ARMArchFeature = "+v7";
 130     break;
 131   case Triple::ARMSubArch_v7:
 132     // v7 CPUs have lots of different feature sets. If no CPU is specified,
 133     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
 134     // the "minimum" feature set and use CPU string to figure out the exact
 135     // features.
 136     if (NoCPU)
 137       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
 138       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
 139     else
 140       // Use CPU to figure out the exact features.
 141       ARMArchFeature = "+v7";
 142     break;
 143   case Triple::ARMSubArch_v6t2:
 144     ARMArchFeature = "+v6t2";
 145     break;
 146   case Triple::ARMSubArch_v6m:
 147     isThumb = true;
 148     if (NoCPU)
 149       // v6m: FeatureNoARM, FeatureMClass
 150       ARMArchFeature = "+v6m,+noarm,+mclass";
 151     else
 152       ARMArchFeature = "+v6";
 153     break;
 154   case Triple::ARMSubArch_v6:
 155     ARMArchFeature = "+v6";
 156     break;
 157   case Triple::ARMSubArch_v5te:
 158     ARMArchFeature = "+v5te";
 159     break;
 160   case Triple::ARMSubArch_v5:
 161     ARMArchFeature = "+v5t";
 162     break;
 163   case Triple::ARMSubArch_v4t:
 164     ARMArchFeature = "+v4t";
 165     break;
 166   }
 167
 168   if (isThumb) {
 169     if (ARMArchFeature.empty())
 170       ARMArchFeature = "+thumb-mode";
 171     else
 172       ARMArchFeature += ",+thumb-mode";
 173   }
 174
 175   if (triple.isOSNaCl()) {
 176     if (ARMArchFeature.empty())
 177       ARMArchFeature = "+nacl-trap";
 178     else
 179       ARMArchFeature += ",+nacl-trap";
 180   }
 181
 182   return ARMArchFeature;
 183 }
 184
 185 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 186                                                   StringRef FS) {
 187   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 188   if (!FS.empty()) {
 189     if (!ArchFS.empty())
 190       ArchFS = ArchFS + "," + FS.str();
 191     else
 192       ArchFS = FS;
 193   }
 194
 195   MCSubtargetInfo *X = new MCSubtargetInfo();
 196   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 197   return X;
 198 }
 199
 200 static MCInstrInfo *createARMMCInstrInfo() {
 201   MCInstrInfo *X = new MCInstrInfo();
 202   InitARMMCInstrInfo(X);
 203   return X;
 204 }
 205
 206 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 207   MCRegisterInfo *X = new MCRegisterInfo();
 208   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 209   return X;
 210 }
 211
 212 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
 213   Triple TheTriple(TT);
 214
 215   MCAsmInfo *MAI;
 216   switch (TheTriple.getOS()) {
 217   case llvm::Triple::Darwin:
 218   case llvm::Triple::IOS:
 219   case llvm::Triple::MacOSX:
 220     MAI = new ARMMCAsmInfoDarwin(TT);
 221     break;
 222   case llvm::Triple::Win32:
 223     switch (TheTriple.getEnvironment()) {
 224     case llvm::Triple::Itanium:
 225       MAI = new ARMCOFFMCAsmInfoGNU();
 226       break;
 227     case llvm::Triple::MSVC:
 228       MAI = new ARMCOFFMCAsmInfoMicrosoft();
 229       break;
 230     default:
 231       llvm_unreachable("invalid environment");
 232     }
 233     break;
 234   default:
 235     if (TheTriple.isOSBinFormatMachO())
 236       MAI = new ARMMCAsmInfoDarwin(TT);
 237     else
 238       MAI = new ARMELFMCAsmInfo(TT);
 239     break;
 240   }
 241
 242   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
 243   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 244
 245   return MAI;
 246 }
 247
 248 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 249                                              CodeModel::Model CM,
 250                                              CodeGenOpt::Level OL) {
 251   MCCodeGenInfo *X = new MCCodeGenInfo();
 252   if (RM == Reloc::Default) {
 253     Triple TheTriple(TT);
 254     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 255     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 256   }
 257   X->InitMCCodeGenInfo(RM, CM, OL);
 258   return X;
 259 }
 260
 261 // This is duplicated code. Refactor this.
 262 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 263                                     MCContext &Ctx, MCAsmBackend &MAB,
 264                                     raw_ostream &OS,
 265                                     MCCodeEmitter *Emitter,
 266                                     const MCSubtargetInfo &STI,
 267                                     bool RelaxAll,
 268                                     bool NoExecStack) {
 269   Triple TheTriple(TT);
 270
 271   switch (TheTriple.getObjectFormat()) {
 272   default: llvm_unreachable("unsupported object format");
 273   case Triple::MachO: {
 274     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 275     new ARMTargetStreamer(*S);
 276     return S;
 277   }
 278   case Triple::COFF:
 279     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
 280     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
 281   case Triple::ELF:
 282     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
 283                                 TheTriple.getArch() == Triple::thumb);
 284   }
 285 }
 286
 287 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 288                                              unsigned SyntaxVariant,
 289                                              const MCAsmInfo &MAI,
 290                                              const MCInstrInfo &MII,
 291                                              const MCRegisterInfo &MRI,
 292                                              const MCSubtargetInfo &STI) {
 293   if (SyntaxVariant == 0)
 294     return new ARMInstPrinter(MAI, MII, MRI, STI);
 295   return nullptr;
 296 }
 297
 298 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
 299                                                    MCContext &Ctx) {
 300   Triple TheTriple(TT);
 301   if (TheTriple.isOSBinFormatMachO())
 302     return createARMMachORelocationInfo(Ctx);
 303   // Default to the stock relocation info.
 304   return llvm::createMCRelocationInfo(TT, Ctx);
 305 }
 306
 307 namespace {
 308
 309 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 310 public:
 311   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 312
 313   bool isUnconditionalBranch(const MCInst &Inst) const override {
 314     // BCCs with the "always" predicate are unconditional branches.
 315     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 316       return true;
 317     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 318   }
 319
 320   bool isConditionalBranch(const MCInst &Inst) const override {
 321     // BCCs with the "always" predicate are unconditional branches.
 322     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 323       return false;
 324     return MCInstrAnalysis::isConditionalBranch(Inst);
 325   }
 326
 327   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
 328                       uint64_t Size, uint64_t &Target) const override {
 329     // We only handle PCRel branches for now.
 330     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 331       return false;
 332
 333     int64_t Imm = Inst.getOperand(0).getImm();
 334     // FIXME: This is not right for thumb.
 335     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 336     return true;
 337   }
 338 };
 339
 340 }
 341
 342 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 343   return new ARMMCInstrAnalysis(Info);
 344 }
 345
 346 // Force static initialization.
 347 extern "C" void LLVMInitializeARMTargetMC() {
 348   // Register the MC asm info.
 349   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
 350   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
 351   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
 352   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
 353
 354   // Register the MC codegen info.
 355   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
 356   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
 357   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget, createARMMCCodeGenInfo);
 358   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget, createARMMCCodeGenInfo);
 359
 360   // Register the MC instruction info.
 361   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
 362   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
 363   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
 364   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
 365
 366   // Register the MC register info.
 367   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
 368   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
 369   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
 370   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
 371
 372   // Register the MC subtarget info.
 373   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
 374                                           ARM_MC::createARMMCSubtargetInfo);
 375   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
 376                                           ARM_MC::createARMMCSubtargetInfo);
 377   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
 378                                           ARM_MC::createARMMCSubtargetInfo);
 379   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
 380                                           ARM_MC::createARMMCSubtargetInfo);
 381
 382   // Register the MC instruction analyzer.
 383   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
 384                                           createARMMCInstrAnalysis);
 385   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
 386                                           createARMMCInstrAnalysis);
 387   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
 388                                           createARMMCInstrAnalysis);
 389   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
 390                                           createARMMCInstrAnalysis);
 391
 392   // Register the MC Code Emitter
 393   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
 394                                         createARMLEMCCodeEmitter);
 395   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
 396                                         createARMBEMCCodeEmitter);
 397   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
 398                                         createARMLEMCCodeEmitter);
 399   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
 400                                         createARMBEMCCodeEmitter);
 401
 402   // Register the asm backend.
 403   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
 404   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
 405   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
 406                                        createThumbLEAsmBackend);
 407   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
 408                                        createThumbBEAsmBackend);
 409
 410   // Register the object streamer.
 411   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
 412   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
 413   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
 414   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
 415
 416   // Register the asm streamer.
 417   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
 418   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
 419   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
 420   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
 421
 422   // Register the null streamer.
 423   TargetRegistry::RegisterNullStreamer(TheARMLETarget, createARMNullStreamer);
 424   TargetRegistry::RegisterNullStreamer(TheARMBETarget, createARMNullStreamer);
 425   TargetRegistry::RegisterNullStreamer(TheThumbLETarget, createARMNullStreamer);
 426   TargetRegistry::RegisterNullStreamer(TheThumbBETarget, createARMNullStreamer);
 427
 428   // Register the MCInstPrinter.
 429   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
 430   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
 431   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
 432                                         createARMMCInstPrinter);
 433   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
 434                                         createARMMCInstPrinter);
 435
 436   // Register the MC relocation info.
 437   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
 438                                            createARMMCRelocationInfo);
 439   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
 440                                            createARMMCRelocationInfo);
 441   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
 442                                            createARMMCRelocationInfo);
 443   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
 444                                            createARMMCRelocationInfo);
 445 }