1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMELFStreamer.h"
16 #include "ARMMCAsmInfo.h"
17 #include "ARMMCTargetDesc.h"
18 #include "InstPrinter/ARMInstPrinter.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCCodeGenInfo.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
36 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39 // Checks for the deprecated CP15ISB encoding:
40 // mcr p15, #0, rX, c7, c5, #4
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44 Info = "deprecated since v7, use 'isb'";
48 // Checks for the deprecated CP15DSB encoding:
49 // mcr p15, #0, rX, c7, c10, #4
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51 Info = "deprecated since v7, use 'dsb'";
55 // Checks for the deprecated CP15DMB encoding:
56 // mcr p15, #0, rX, c7, c10, #5
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59 Info = "deprecated since v7, use 'dmb'";
66 #define GET_INSTRINFO_MC_DESC
67 #include "ARMGenInstrInfo.inc"
69 #define GET_SUBTARGETINFO_MC_DESC
70 #include "ARMGenSubtargetInfo.inc"
73 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
76 // Set the boolean corresponding to the current target triple, or the default
77 // if one cannot be determined, to true.
78 unsigned Len = TT.size();
81 // FIXME: Enhance Triple helper class to extract ARM version.
83 if (Len >= 5 && TT.substr(0, 4) == "armv")
85 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
87 if (Len >= 7 && TT[5] == 'v')
91 bool NoCPU = CPU == "generic" || CPU.empty();
92 std::string ARMArchFeature;
94 unsigned SubVer = TT[Idx];
96 // FIXME: Parse v8 features
97 ARMArchFeature = "+v8";
98 } else if (SubVer == '7') {
99 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
102 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
103 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
105 // Use CPU to figure out the exact features.
106 ARMArchFeature = "+v7";
107 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
109 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
110 // FeatureT2XtPk, FeatureMClass
111 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
113 // Use CPU to figure out the exact features.
114 ARMArchFeature = "+v7";
115 } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
117 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
119 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
121 // Use CPU to figure out the exact features.
122 ARMArchFeature = "+v7";
124 // v7 CPUs have lots of different feature sets. If no CPU is specified,
125 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
126 // the "minimum" feature set and use CPU string to figure out the exact
129 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
130 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
132 // Use CPU to figure out the exact features.
133 ARMArchFeature = "+v7";
135 } else if (SubVer == '6') {
136 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
137 ARMArchFeature = "+v6t2";
138 else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
141 // v6m: FeatureNoARM, FeatureMClass
142 ARMArchFeature = "+v6,+noarm,+mclass";
144 ARMArchFeature = "+v6";
146 ARMArchFeature = "+v6";
147 } else if (SubVer == '5') {
148 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
149 ARMArchFeature = "+v5te";
151 ARMArchFeature = "+v5t";
152 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
153 ARMArchFeature = "+v4t";
157 if (ARMArchFeature.empty())
158 ARMArchFeature = "+thumb-mode";
160 ARMArchFeature += ",+thumb-mode";
163 if (triple.isOSNaCl()) {
164 if (ARMArchFeature.empty())
165 ARMArchFeature = "+nacl-trap";
167 ARMArchFeature += ",+nacl-trap";
170 return ARMArchFeature;
173 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
175 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
178 ArchFS = ArchFS + "," + FS.str();
183 MCSubtargetInfo *X = new MCSubtargetInfo();
184 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
188 static MCInstrInfo *createARMMCInstrInfo() {
189 MCInstrInfo *X = new MCInstrInfo();
190 InitARMMCInstrInfo(X);
194 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
195 MCRegisterInfo *X = new MCRegisterInfo();
196 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
200 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
201 Triple TheTriple(TT);
203 if (TheTriple.isOSDarwin())
204 return new ARMMCAsmInfoDarwin();
206 return new ARMELFMCAsmInfo();
209 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
211 CodeGenOpt::Level OL) {
212 MCCodeGenInfo *X = new MCCodeGenInfo();
213 if (RM == Reloc::Default) {
214 Triple TheTriple(TT);
215 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
216 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
218 X->InitMCCodeGenInfo(RM, CM, OL);
222 // This is duplicated code. Refactor this.
223 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
224 MCContext &Ctx, MCAsmBackend &MAB,
226 MCCodeEmitter *Emitter,
229 Triple TheTriple(TT);
231 if (TheTriple.isOSDarwin())
232 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
234 if (TheTriple.isOSWindows()) {
235 llvm_unreachable("ARM does not support Windows COFF format");
238 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
239 TheTriple.getArch() == Triple::thumb);
242 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
243 unsigned SyntaxVariant,
244 const MCAsmInfo &MAI,
245 const MCInstrInfo &MII,
246 const MCRegisterInfo &MRI,
247 const MCSubtargetInfo &STI) {
248 if (SyntaxVariant == 0)
249 return new ARMInstPrinter(MAI, MII, MRI, STI);
253 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
255 Triple TheTriple(TT);
256 if (TheTriple.isEnvironmentMachO())
257 return createARMMachORelocationInfo(Ctx);
258 // Default to the stock relocation info.
259 return llvm::createMCRelocationInfo(TT, Ctx);
264 class ARMMCInstrAnalysis : public MCInstrAnalysis {
266 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
268 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
269 // BCCs with the "always" predicate are unconditional branches.
270 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
272 return MCInstrAnalysis::isUnconditionalBranch(Inst);
275 virtual bool isConditionalBranch(const MCInst &Inst) const {
276 // BCCs with the "always" predicate are unconditional branches.
277 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
279 return MCInstrAnalysis::isConditionalBranch(Inst);
282 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
283 uint64_t Size, uint64_t &Target) const {
284 // We only handle PCRel branches for now.
285 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
288 int64_t Imm = Inst.getOperand(0).getImm();
289 // FIXME: This is not right for thumb.
290 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
297 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
298 return new ARMMCInstrAnalysis(Info);
301 // Force static initialization.
302 extern "C" void LLVMInitializeARMTargetMC() {
303 // Register the MC asm info.
304 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
305 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
307 // Register the MC codegen info.
308 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
309 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
311 // Register the MC instruction info.
312 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
313 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
315 // Register the MC register info.
316 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
317 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
319 // Register the MC subtarget info.
320 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
321 ARM_MC::createARMMCSubtargetInfo);
322 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
323 ARM_MC::createARMMCSubtargetInfo);
325 // Register the MC instruction analyzer.
326 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
327 createARMMCInstrAnalysis);
328 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
329 createARMMCInstrAnalysis);
331 // Register the MC Code Emitter
332 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
333 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
335 // Register the asm backend.
336 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
337 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
339 // Register the object streamer.
340 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
341 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
343 // Register the MCInstPrinter.
344 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
345 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
347 // Register the MC relocation info.
348 TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
349 createARMMCRelocationInfo);
350 TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
351 createARMMCRelocationInfo);