1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMMCTARGETDESC_H
15 #define ARMMCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
21 class formatted_raw_ostream;
29 class MCSubtargetInfo;
31 class MCRelocationInfo;
36 extern Target TheARMLETarget, TheThumbLETarget;
37 extern Target TheARMBETarget, TheThumbBETarget;
40 std::string ParseARMTriple(StringRef TT, StringRef CPU);
42 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
43 /// This is exposed so Asm parser, etc. do not need to go through
45 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
49 MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
50 bool isVerboseAsm, bool useDwarfDirectory,
51 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
52 MCAsmBackend *TAB, bool ShowInst);
54 MCStreamer *createARMNullStreamer(MCContext &Ctx);
56 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
57 const MCRegisterInfo &MRI,
58 const MCSubtargetInfo &STI,
61 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI,
66 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
67 StringRef TT, StringRef CPU,
70 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 StringRef TT, StringRef CPU);
73 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 StringRef TT, StringRef CPU);
76 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
77 StringRef TT, StringRef CPU);
79 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
80 StringRef TT, StringRef CPU);
82 /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which
83 /// will generate a PE/COFF object file.
84 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
85 MCCodeEmitter &Emitter, raw_ostream &OS);
87 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
88 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
92 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
93 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
98 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
99 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
101 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
102 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
103 } // End llvm namespace
105 // Defines symbolic names for ARM registers. This defines a mapping from
106 // register name to register number.
108 #define GET_REGINFO_ENUM
109 #include "ARMGenRegisterInfo.inc"
111 // Defines symbolic names for the ARM instructions.
113 #define GET_INSTRINFO_ENUM
114 #include "ARMGenInstrInfo.inc"
116 #define GET_SUBTARGETINFO_ENUM
117 #include "ARMGenSubtargetInfo.inc"